JPS56118367A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS56118367A
JPS56118367A JP2140980A JP2140980A JPS56118367A JP S56118367 A JPS56118367 A JP S56118367A JP 2140980 A JP2140980 A JP 2140980A JP 2140980 A JP2140980 A JP 2140980A JP S56118367 A JPS56118367 A JP S56118367A
Authority
JP
Japan
Prior art keywords
film
substrate
sio2
mask
ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2140980A
Other languages
Japanese (ja)
Inventor
Izumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2140980A priority Critical patent/JPS56118367A/en
Publication of JPS56118367A publication Critical patent/JPS56118367A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the defects from taking place and growing on the substrate during the high temperature heat treatment and to improve the properties, by forming new defectless SiO2 film and the well region after removing the damaged SiO2 film owing to etching and ions implantation. CONSTITUTION:An SiO2 2 and CVD Si3N4 3 are stacked on an N type Si substrate 1 and a resist-mask 10 is formed. Plasma etching by means of CF4 gas and etching by means of HF solution are performed to form an opening. Then a resist-mask 4 is again formed and B ions are implanted into the substrate through the Si3N4 film 3. The mask 4 is removed and after treatment at the temperature of about 1,000 deg.C and coverage by an SiO2 film 11, a P well 5 is formed by heat treatment in N2 at the temperature of 1,200 deg.C. Thereafter, according to the normal method, to the part where a field oxidized film is to be formed around the parts where a P channel device and N channel device are to be formed, P and B ions are respectively implanted to form channel stoppers 8, 7 and a field oxidized film 6. Because the newly formed SiO2 film is defectless and with no pinhole, the substrate 1 is free from defects.
JP2140980A 1980-02-22 1980-02-22 Preparation of semiconductor device Pending JPS56118367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2140980A JPS56118367A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2140980A JPS56118367A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56118367A true JPS56118367A (en) 1981-09-17

Family

ID=12054224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2140980A Pending JPS56118367A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56118367A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58202562A (en) * 1982-04-08 1983-11-25 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Method of producing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58202562A (en) * 1982-04-08 1983-11-25 エス・ジ−・エス−アテス・コンポネンチ・エレツトロニシ・ソシエタ・ペル・アチオニ Method of producing semiconductor device
JPH0479142B2 (en) * 1982-04-08 1992-12-15 Etsuse Jii Etsuse Atesu Konhonentei Eretsutoronishi Spa

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