KR910005384A - 반도체 디바이스 내의 코프래너한 자기- 정합 접촉 구조물의 제조방법 - Google Patents
반도체 디바이스 내의 코프래너한 자기- 정합 접촉 구조물의 제조방법 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims 5
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 14
- 238000000034 method Methods 0.000 claims 13
- 238000000137 annealing Methods 0.000 claims 6
- 238000005530 etching Methods 0.000 claims 6
- 239000000758 substrate Substances 0.000 claims 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 claims 4
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 230000000149 penetrating effect Effects 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 3
- 229920005591 polysilicon Polymers 0.000 claims 3
- 230000006641 stabilisation Effects 0.000 claims 3
- 238000011105 stabilization Methods 0.000 claims 3
- 239000003870 refractory metal Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제12도는 그 홀에 금속을 증착시킨 후에 제11도의 디바이스를 도시한 도면.
Claims (13)
- 반도체 디바이스내의 코플래너 자기-정합 접촉 구조물을 형성하는 방법에 있어서, 기판의 플라나 면내에 기판의 섬 영역에 의해 서로 분리되는 제1및 제2필드 산화물영역들을 형성하는 스텝, 섬 영역의 플라나 표면내에 게이트 산화물 층을 형성하는 스텝, 제1패드가 제1필드 산화물 영역위에 놓이고, 제2패드가 제2팰드 산화물 영역위에 놓이며, 제3패드가 게이트를 정하기 위해 게이트 산화물 영역 위에 놓인 3개의 코플레너 폴리실리콘 패드를 형성하는 스텝, 게이트 영역과 제1필드 산화물 영역 사이의 소오스 확산 영역 및 게이트 영역과 제2필드 산화물 영역사이의 드레인 확산영역인 섬 영역을 형성하는 스텝, 내화 금속으로 패드들 및 기판을 코팅하는 스텝, 반응성 층으로 금속을 코팅하는 스텝, 금속 및 반응성층들로부터 각각, 소오스 및 드레인 영역과 전기적으로 접촉하고, 제1및 제2패드 위로 연장되는 제1및 제2 도체를 형성하는 스텝, 및 패드들을 덮는 도체 부분들과의 전기적인 접촉부들을 설정하는 스텝을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 도체를 형성하는 스텝이, 제1패드 위에 놓이고, 그로부터 소오스 영역의 일부분 위로 연장되는 제1도전성 스트립 및 제2패드위에 놓이고 그로부터 드레인 영역의 일부분 위로 연장되는 제2스트립을 형성하기 위해 반응 층을 에칭하는 스텝, 및 도체들을 형성하기 위해 아닐링하는 스텝을 포함하는 것을 특징으로 하는 방법.
- 제2항에 있어서, 반응층이 비결정질 실리콘으로 구성되는 것을 특징으로 하는 방법.
- 제3항에 있어서, 아닐링 스텝이, 비결정질 실리콘으로된 비결정질 실리콘 스트립에 의해 덮인 이 부분의 금속을 반응시키고, 기판의 소오스 및 드레인 영역들을 덮고 기판과 함께 비결정질 실리콘에 의해 덮이지 않는 이 부분의 금속을 반응시키기 위한 비교적 저온에서의 아닐링 스텝, 소정의 무반응 금속을 제거하는 스텝, 및 비교적 고온에서의 아닐링 스텝을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 도체를 형성하는 스텝이, 디바이스의 산화물 부분위에 질화물 및 실리콘 부분위에 실리콘 화합물을 형성하기 위한 비교적 저온에서의 아닐링 스텝, 제1패드위에 놓이고, 그로부터 소오스 영역의 일부분위로 연장되는 제1도전성 스트립 및 제2패드 위에 놓이고 그로부터 일부분으로 및 드레인 영역의 일부분 위로 연장되는 제2스트립을 형성하기 위한 에칭스텝 및 비교적 고온에서의 아닐링 스텝을 포함하는 것을 특징으로 하는 방법.
- 제5항에 있어서, 내화 금속이 타타늄으로 구성되고 반응 층이 티타늄질화물 층으로 구성되는 것을 특징으로하는 방법.
- 제1항에 있어서, 확산 영역들을 형성하는 스텝이, 유전체 층으로 패드들 및 기판을 코팅하는 스텝, 패드들을 주변에 산화물 스페이서들을 제공하기 위해 유전체 층을 방향성으로 에칭하는 스텝, 및 확산 영역들을 형성하기 위해 이온 주입 및 드라이브-인을 수행하는 스텝을 포함하는 것으를 특징으로 하는 방법.
- 제1항에 있어서, 3개의 패드들을 형성하는 스텝이 섬 영역 및 각각의 필드 산화물 영역들의 일부분 위에 폴리실리콘 층을 형성하고 폴리실리콘응 및 하부에 놓인 게이트 산화물 층을 에칭하는 스텝을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 전기 접촉부를 설정하는 스텝이, 도체 위에 표면안정화 층을 형성하는 스텝, 거의 유사한 깊이인 제1도체에 대한 제1패드위의 표면안정화 층을 관통하는 제1홀 및 제2도체에 대한 제2접촉 패드위의 표면 안정화 층을 관통하는 제2홀을 제조하는 스텝, 및 도체들과의 접촉을 홀의 저부에 설정하기 위해 각각의 홀에 금속을 증착시키는 스텝을 포함하는 것을 특징으로 하는 방법.
- 제1항에 있어서, 전기적 접촉부들을 설정하는 스텝이, 제1유전체 층에 의해 패드들위에 놓인 도체 부분들을 제외한 반도체를 덮는 스텝, 제2유전체층에 의해 제1층 및 도체의 노출된 부분을 덮는 스텝, 거의 유사한 깊이인 제1도체에 대한 제1패드위에 제2유전체 층을 관통하는 제1홀 및 제2도체에 대한 제2패드위의 제2유전체 층을 관통하는 제2홀을 제조하는 스텝, 및 도체들과의 접촉을 홀의 저부에 설정하기 위해 각각의 홀에 금속을 증착시키는 스텝을 포함하는 것을 특징으로 하는 방법.
- 제10항에 있어서, 제1유전체 층에 의해 반도체를 덮는 스텝이 제1유전체 층에 의해 전체 반도체를 덮고, 제1유전체층 위의 두꺼운 포토레지스트를 스피닝하며, 패드들위에 놓인 도체 부분의 레벨에 대해 하부로 유전체층을 플라나화 하기 위해 다시 에칭하는 스텝를 포함하는 것을 특징으로 하는 방법.
- 제10항에 있어서, 홀들을 제조하는 스텝이 제1유전체층 상에서 보다 제2유전체 층 상에서 최소한 10배이상 신속하게 반응하는 에천트에 의해 에칭하는 스텝를 포함하는 것을 특징으로 하는 방법.
- 제10항에 있어서, 홀들 중에서 1개의 홀이 하부에 있는 패드보다 넣은 것을 특징으로 하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US400,609 | 1989-08-30 | ||
US07/400,609 US4994402A (en) | 1987-06-26 | 1989-08-30 | Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device |
Publications (1)
Publication Number | Publication Date |
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KR910005384A true KR910005384A (ko) | 1991-03-30 |
Family
ID=23584293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900013358A KR910005384A (ko) | 1989-08-30 | 1990-08-29 | 반도체 디바이스 내의 코프래너한 자기- 정합 접촉 구조물의 제조방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US4994402A (ko) |
EP (1) | EP0415528A3 (ko) |
JP (1) | JPH0391930A (ko) |
KR (1) | KR910005384A (ko) |
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KR0175030B1 (ko) * | 1995-12-07 | 1999-04-01 | 김광호 | 반도체 소자의 고내열 금속 배선 구조 및 그 형성 방법 |
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KR100451042B1 (ko) * | 1997-06-27 | 2004-12-03 | 주식회사 하이닉스반도체 | 반도체소자의콘택형성방법 |
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US6019906A (en) * | 1998-05-29 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming patterned oxygen containing plasma etchable layer |
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US7855422B2 (en) * | 2006-05-31 | 2010-12-21 | Alpha & Omega Semiconductor, Ltd. | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process |
US8278176B2 (en) | 2006-06-07 | 2012-10-02 | Asm America, Inc. | Selective epitaxial formation of semiconductor films |
US8367548B2 (en) | 2007-03-16 | 2013-02-05 | Asm America, Inc. | Stable silicide films and methods for making the same |
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CN101621030B (zh) * | 2008-07-02 | 2011-01-12 | 中芯国际集成电路制造(上海)有限公司 | 具有多晶硅接触的自对准mos结构 |
US7927942B2 (en) | 2008-12-19 | 2011-04-19 | Asm International N.V. | Selective silicide process |
US9379011B2 (en) | 2008-12-19 | 2016-06-28 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
JP2011029610A (ja) * | 2009-06-26 | 2011-02-10 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
JP5658916B2 (ja) * | 2009-06-26 | 2015-01-28 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US8367528B2 (en) * | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
US8871617B2 (en) | 2011-04-22 | 2014-10-28 | Asm Ip Holding B.V. | Deposition and reduction of mixed metal oxide thin films |
US8809170B2 (en) | 2011-05-19 | 2014-08-19 | Asm America Inc. | High throughput cyclical epitaxial deposition and etch process |
US9607842B1 (en) | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
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JPS5329088A (en) * | 1976-08-30 | 1978-03-17 | Nec Corp | Production of semiconductor integrated circuit device |
US4208781A (en) * | 1976-09-27 | 1980-06-24 | Texas Instruments Incorporated | Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer |
JPS53105989A (en) * | 1977-02-28 | 1978-09-14 | Hitachi Ltd | Semiconductor device |
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US4333225A (en) * | 1978-12-18 | 1982-06-08 | Xerox Corporation | Method of making a circular high voltage field effect transistor |
US4305200A (en) * | 1979-11-06 | 1981-12-15 | Hewlett-Packard Company | Method of forming self-registering source, drain, and gate contacts for FET transistor structures |
JPS574141A (en) * | 1980-06-10 | 1982-01-09 | Sanyo Electric Co Ltd | Wiring structure in semiconductor device |
US4402126A (en) * | 1981-05-18 | 1983-09-06 | Texas Instruments Incorporated | Method for fabrication of a non-volatile JRAM cell |
DE3132809A1 (de) * | 1981-08-19 | 1983-03-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene |
US4422885A (en) * | 1981-12-18 | 1983-12-27 | Ncr Corporation | Polysilicon-doped-first CMOS process |
US4443930A (en) * | 1982-11-30 | 1984-04-24 | Ncr Corporation | Manufacturing method of silicide gates and interconnects for integrated circuits |
FR2588418B1 (fr) * | 1985-10-03 | 1988-07-29 | Bull Sa | Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant |
JPH061776B2 (ja) * | 1985-11-29 | 1994-01-05 | 三菱電機株式会社 | 半導体集積回路装置及びその製造方法 |
US4767724A (en) * | 1986-03-27 | 1988-08-30 | General Electric Company | Unframed via interconnection with dielectric etch stop |
US4788160A (en) * | 1987-03-31 | 1988-11-29 | Texas Instruments Incorporated | Process for formation of shallow silicided junctions |
EP0296718A3 (en) * | 1987-06-26 | 1990-05-02 | Hewlett-Packard Company | A coplanar and self-aligned contact structure |
US4822749A (en) * | 1987-08-27 | 1989-04-18 | North American Philips Corporation, Signetics Division | Self-aligned metallization for semiconductor device and process using selectively deposited tungsten |
-
1989
- 1989-08-30 US US07/400,609 patent/US4994402A/en not_active Expired - Fee Related
-
1990
- 1990-07-04 EP EP19900307322 patent/EP0415528A3/en not_active Withdrawn
- 1990-08-29 KR KR1019900013358A patent/KR910005384A/ko not_active Application Discontinuation
- 1990-08-29 JP JP2227859A patent/JPH0391930A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH0391930A (ja) | 1991-04-17 |
EP0415528A2 (en) | 1991-03-06 |
US4994402A (en) | 1991-02-19 |
EP0415528A3 (en) | 1992-12-30 |
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