KR19990057943A - 반도체 장치의 콘택홀 형성방법 - Google Patents

반도체 장치의 콘택홀 형성방법 Download PDF

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KR19990057943A
KR19990057943A KR1019970078022A KR19970078022A KR19990057943A KR 19990057943 A KR19990057943 A KR 19990057943A KR 1019970078022 A KR1019970078022 A KR 1019970078022A KR 19970078022 A KR19970078022 A KR 19970078022A KR 19990057943 A KR19990057943 A KR 19990057943A
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contact hole
forming
junction region
gate electrode
present
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KR1019970078022A
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KR100278273B1 (ko
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박재범
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치를 구성하는 층간의 수직 배선을 위한 콘택홀 형성 공정에 관한 것이며, 접합 영역의 손상 없이 접합 영역 및 게이트 전극에의 콘택을 위한 두 종류의 콘택홀을 동시에 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다. 본 발명은 콘택홀 식각시 층간절연막과 높은 식각 선택비를 갖는 식각 방지막을 접합 영역 상의 콘택 부분에만 선택적으로 형성함으로써 접합 영역에 자기정렬 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성할 수 있다. 즉, 접합 영역의 손상이 유발되지 않고 두 종류의 콘택홀을 동시에 식각할 수 있다.

Description

반도체 장치의 콘택홀 형성방법
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치를 구성하는 층간의 수직 배선을 위한 콘택홀 형성 공정에 관한 것이다.
반도체 장치가 고집적화에 따라 패턴의 선폭 및 패턴간의 거리가 좁아지고 있으며, 이에 따라 반도체 장치를 구성하는 층간의 수직 배선을 위한 콘택홀 형성시의 공정 마진이 줄어들고 있다. 이러한 공정 마진을 확보하기 위하여 서로 다른 절연막간의 식각 선택비를 이용한 자기정렬 방식의 콘택홀 형성 공정이 일반화되고 있다.
이하, 첨부된 도 1a 내지 도 1c를 참조하여 종래기술에 따른 콘택홀 형성 공정 및 그 문제점을 살펴본다.
먼저, 도 1a에 도시된 바와 같이 실리콘 기판(11) 상에 소자 분리막(12)을 형성하고, 전체구조 상부에 게이트 산화막(13)을 성장시킨 다음, 그 상부에 게이트 전극(14)을 형성한다. 이때, 게이트 전극은 후속 자기정렬 콘택 공정을 위하여 그 상부의 마스크 질화막(15)과 그 측벽 부분의 스페이서 질화막(17)으로 덮여 있다. 이어서, 전체구조 상부에 평탄화된 층간절연막(18)을 형성한다. 여기서, 도면 부호 '16'은 접합 영역을 나타낸 것이다.
계속하여, 도 1b에 도시된 바와 같이 마스크 공정 및 식각 공정을 진행하여 층간절연막(18)을 선택 식각함으로써 접합 영역(16)을 노출시키는 자기정렬 콘택홀을 형성한다.
다음으로, 도 1c에 도시된 바와 같이 게이트 전극(14)에의 콘택을 이루기 위하여 다시 마스크 공정 및 식각 공정을 진행하여 층간절연막(18)을 선택 식각함으로써 게이트 전극(14)을 노출시키는 콘택홀을 형성한다.
상술한 바와 같이 진행되는 종래의 콘택홀 형성 공정은 접합 영역 및 게이트 전극에의 콘택을 위하여 각각의 콘택홀 형성을 위한 2 회의 마스크 공정 및 식각 공정을 필요로 하여 공정을 복잡화하는 단점이 있다. 이는 층간절연막에 비해 식각 속도가 훨씬 느린 질화막이 게이트 전극 상부를 덮고 있어 두 종류의 콘택홀을 동시에 식각할 경우, 접합 영역의 손상이 유발되기 때문이다.
본 발명은 접합 영역의 손상 없이 접합 영역 및 게이트 전극에의 콘택을 위한 두 종류의 콘택홀을 동시에 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다.
도 1a 내지 도 1c는 종래기술에 따른 콘택홀 형성 공정도.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 콘택홀 형성 공정도.
* 도면의 주요 부분에 대한 부호의 설명
21 : 실리콘 기판 22 : 소자 분리막
23 : 게이트 산화막 24 : 폴리실리콘막
25 : 마스크 산화막 26 : 접합 영역
27 : 스페이서 산화막 28 : 질화막
29 : 층간절연막
본 발명은 콘택홀 식각시 층간절연막과 높은 식각 선택비를 갖는 식각 방지막을 접합 영역 상의 콘택 부분에만 선택적으로 형성함으로써 접합 영역에 자기정렬 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성할 수 있다. 즉, 접합 영역의 손상이 유발되지 않고 두 종류의 콘택홀을 동시에 식각할 수 있다.
상술한 본 발명의 기술적 원리로부터 제공되는 특징적인 반도체 장치의 콘택홀 형성방법은 게이트 절연막이 형성된 반도체 기판에 그 상부 및 그 측벽 부분이 절연된 게이트 전극 및 접합 영역을 형성하는 단계; 전체구조 상부에 식각 방지막을 형성하는 단계; 상기 게이트 전극 중 콘택이 이루어질 게이트 전극 상부의 상기 식각 방지막을 선택 식각하는 단계; 전체구조 상부에 층간절연막을 형성하는 단계; 및 상기 접합 영역 상부에 오버랩되는 층간절연막 및 식각 방지막을 차례로 선택 식각하여 접합 영역을 노출시키는 제1 콘택홀을 형성하는 동시에 상기 게이트 전극을 노출시키는 제2 콘택홀을 형성하는 단계를 포함하여 이루어진다.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 소개한다.
첨부된 도면 도 2a 내지 도 2d는 본 발명의 일실시예에 따른 콘택홀 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 설명한다.
우선, 도 2a에 도시된 바와 같이 실리콘 기판(21) 상에 소자 분리막(22)을 형성한 다음, 전체구조 상부에 게이트 산화막(23), 폴리실리콘막(24) 및 마스크 산화막(25)을 차례로 형성하고, 게이트 전극 형성을 위한 식각 마스크를 사용하여 마스크 산화막(25) 및 폴리실리콘막(24)을 차례로 선택 식각하여 게이트 전극을 형성한다. 이어서, LDD(Lightly Doped Drain) 구조 형성을 위한 저농도의 도전형 불순물 이온주입을 실시하고, 게이트 전극 측벽 부분에 스페이서 산화막(27)을 형성한 다음, 고농도의 도전형 불순물 이온주입을 실시하여 접합 영역(26)을 형성한다.
계속하여, 도 2b에 도시된 바와 같이 후속 층간절연막 식각시 높은 선택비를 갖는 식각 방지막으로써 질화막(28)을 전체구조 상부에 증착한다.
다음으로. 도 2c에 도시된 바와 같이 질화막(28)을 선택 식각하여 후속 게이트 전극에의 콘택을 위한 콘택홀이 형성될 부분의 질화막(28)을 제거한다.
계속하여, 도 2d에 도시된 바와 같이 전체구조 상부에 산화막계 층간절연막(29)을 증착하고, 층간절연막(29) 및 질화막(28)을 선택 식각하여 접합 영역(26) 및 게이트 전극을 노출시키는 콘택홀을 형성한다. 이때, 접합 영역(26)을 노출시키는 콘택홀은 자기정렬 방식으로 형성되고, 게이트 전극 상부에는 질화막(28)이 존재하지 않기 때문에 마스크 산화막(25)이 선택 식각되며, 따라서 접합 영역(26)의 손상을 방지할 수 있다.
상술한 일실시예에서는 식각 방지막으로서 질화막을 한정하여 설명하였으나, 이는 본 발명의 바람직한 실시예를 나타낸 것으로, 본 발명은 질화막을 대신하여 층간절연막과 식각 선택비를 가지는 다른 절연막을 사용할 수 있다.
그리고, 게이트 전극을 덮고 있는 마스크 산화막 및 스페이서 산화막 또한, 다른 절연막으로 대체하여 사용할 수 있다.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.
이상에서와 같이 본 발명은 접합 영역의 손상 없이 접합 영역에 자기정렬 방식으로 콘택홀을 형성함과 동시에 게이트 전극에도 콘택홀을 형성함으로써 반도체 장치 제조 공정을 단순화하는 효과가 있다.

Claims (3)

  1. 게이트 절연막이 형성된 반도체 기판에 그 상부 및 그 측벽 부분이 절연된 게이트 전극 및 접합 영역을 형성하는 단계;
    전체구조 상부에 식각 방지막을 형성하는 단계;
    상기 게이트 전극 중 콘택이 이루어질 게이트 전극 상부의 상기 식각 방지막을 선택 식각하는 단계;
    전체구조 상부에 층간절연막을 형성하는 단계; 및
    상기 접합 영역 상부에 오버랩되는 층간절연막 및 식각 방지막을 차례로 선택 식각하여 접합 영역을 노출시키는 제1 콘택홀을 형성하는 동시에 상기 게이트 전극을 노출시키는 제2 콘택홀을 형성하는 단계
    를 포함하여 이루어진 반도체 장치의 콘택홀 형성방법.
  2. 제 1 항에 있어서,
    상기 식각 방지막이 질화막인 반도체 장치의 콘택홀 형성방법.
  3. 제 1 항 또는 제 2 항에 있어서,
    상기 게이트 전극 상부 및 측벽 부분이 산화막 또는 질화막으로 절연된 반도체 장치의 콘택홀 형성방법.
KR1019970078022A 1997-12-30 1997-12-30 반도체장치의콘택홀형성방법 KR100278273B1 (ko)

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KR19990057943A true KR19990057943A (ko) 1999-07-15
KR100278273B1 KR100278273B1 (ko) 2001-02-01

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