GB2128021A - CMOS structure including deep region and process for fabrication - Google Patents

CMOS structure including deep region and process for fabrication Download PDF

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Publication number
GB2128021A
GB2128021A GB08315618A GB8315618A GB2128021A GB 2128021 A GB2128021 A GB 2128021A GB 08315618 A GB08315618 A GB 08315618A GB 8315618 A GB8315618 A GB 8315618A GB 2128021 A GB2128021 A GB 2128021A
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Prior art keywords
tub
region
substrate
integrated circuit
conductivity type
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GB08315618A
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GB8315618D0 (en
Inventor
Richard C Foss
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Standard Microsystems LLC
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Standard Microsystems LLC
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Publication of GB8315618D0 publication Critical patent/GB8315618D0/en
Publication of GB2128021A publication Critical patent/GB2128021A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

A CMOS structure includes a tube 28 or well of a first conductivity type formed in an opposite conductivity-type substrate. Source 44 and drain 42 regions of a first MOS device are formed in the tub and a second complementary MOS device is formed in the substrate. and spaced from the tub. A deep region 16c of the first conductivity type and at a higher impurity concentration than that of the tub extends into the substrate and surrounds and contacts the perimeter of the tub. The deep region serves as a guard ring and is effective to prevent the occurrence of latchup. Also disclosed is a process for fabricating the structure. <IMAGE>

Description

SPECIFICATION CMOS structure including deep region and process for fabrication The present invention relates generally to semiconductor integrated circuits, and more particularly to an improved CMOS integrated circuit.
In recent years the use of CMOS integrated circuits has increased considerably, particularly in high-density static RAMs. In one widely used CMOS process, atub orwell of one conductivity type is formed at a selected portion of a substrate of an opposite conductivity type. Source and drain regions are then formed in the tub to form an MOS device of one conductivity type. Complementary, that is, opposite-conductivity-type, MOS devices, are formed in other portions of the same substrate.
Although this CMOS construction has several advantages, it is subject to several undesirable phenomena, which have become more prominent as the dimensions and the impurity concentrations of CMOS devices have steadily decreased in recent years. First, CMOS circuits of this type are subject to the deleterious effects of bulk substrate minority carriers. Moreover, the proximity of the complementary MOS devices creates the likelihood of latch up effects caused by the establishment of parasitic bipolar devices between two adjacent complementary MOS devices.
Various techniques have been proposed and employed in CMOS integrated circuits in an attempt to prevent or minimize these problems. While some of these techniques have proven to be of some effectiveness, they require the use of additional masking and photolithographic steps in the fabrication of the integrated circuit, which increases the cost of fabrication and reduces the yield of useful devices.
It is therefore an object of the invention to provide a CMOS integrated circuit and a process for its fabrication, which requires fewer masking steps.
It is a further object of the invention to provide a CMOS integrated circuit of the type described in which the above described adverse effects of known CMOS integrated circuits are reliably overcome.
To these ends, the present invention provides a CMOS integrated circuit structure which includes a tub or well of afirstconductivitytypeformed in an opposite conductivity type substrate. Source and drain regions of an MOS device are formed in the tub and a second complementary MOS device is formed in the substrate spaced from the tub. A deep region of the first conductivity type extends into the substrate and surrounds and contacts the perimeter of the tub to serve as a guard ring and to prevent the occurrence of latchup.
To the accomplishment of the above and such further objects as may hereinafter appear the present invention relates to a CMOS integrated circuit and a method for its fabrication, substantially as defined in the appended claims, and as described in the following specification as considered with the accompanying drawings in which: Figures 16 are cross-sectional diagrams of a CMOS integrated circuit according to the present invention as viewed during several steps of its fabrication, Figure 6 illustrating a completed CMOS integrated circuit; and Figure 7 is a cross section of a capacitor formed in an MOS circuit employing the principles of the invention.
The fabrication of the CMOS integrated structure of the invention, as in the embodiment shown, starts with a high-resistivity p-type silicon substrate 10. Substrate 10 may comprise an epitaxial p-type layer on a p+ base layer, or, alternatively, it may be, as shown in Figure 1, a simple bulk high-resistivity p-type wafer. The substrate 10 is then covered with a silicon dioxide film 12 in which openings 14 are formed at selected locations. A diffusion, or, alternatively an implantation, procedure is then carried out of n-type (phosphorous or arsenic) to form a series of deep (in the order of 2 microns) n+ regions 16, three of which 16a, b, and care shown in Figure 2, in the upper surface of the substrate at the locations of openings 14. At least the region 1 6c may be in the form of an annulus or ring as viewed in plan.Each of the deep n regions 16 has an impurity concentration in excess of 1018 atoms/cm3, and preferably in the range of 1020 atoms /cm3. When an epitaxial substrate is employed, the n regions 16 or their depletion regions preferably extend to the base layer.
The oxide film 12 is then removed, and, as shown in Figure 2, an oxide growth-inhibiting layer made up of an upper silicon nitride layer (Si3N4) 18 and a relatively thin lower silicon dioxide (SiO2) layer 20 and covered by atop layer 22 of oxide or photoresist is formed and selectively patterned on the upper surface of the substrate to define the field region of the circuit.An implantation of p-type (e.g. boron) ions is then carried out using the oxide-nitride layer as an implantation barrier to form a p-type implanted field region 24 having a concentration of p-type impurities in the range of 1016 atoms/cm3 to 1018 atoms/cm3 to prevent the inversion of the field underlying the field oxide by a positive potential applied to a conductor overlying the field oxide, except at the locations of the deep n+ region 16a-c, which are of a higher concentration of n-type impurities than the concentration of p-type impurities in the field region 24. The opposite ends of the field region 24 terminate at the deep n regions 16a and 16c, and, as shown in Figure 2, the implant region may be separated into two portions by one of the deep n regions 16b.
A thick field oxide layer 26 is then formed by a known technique employing layer 22 as a mask, after which, the thick field oxide layer 26 is used as a mask to counterdope the substrate with n-type impurities to provide an n-type tub 28 having a net impurity concentration less than that of the deep n regions, in the range between 1015 atoms/ cm3 and 1018 atoms/cm3. As seen in Figure 3, the tub 28 is thus self-aligned with the thick field oxide layer 26 and its perimeter is surrounded by and in contact with the ring or annulus n region 16c. The annular n region 1 6c may, as shown, extend substantially to the depth of the tub 28. As described below, this arrangement provides several benefits to the completed CMOS circuit.
Thereafter, using the same mask that was used to form the n-type tub 28, a p-gate implant is performed as indicated at 30 at the location of the n tub 28 to establish the p-channel threshold voltage for the active device that is to be formed in the tub. Similarly, a separate implant, as indicated at 32, is performed with a resist mask (not shown) over then tub region to control the threshold voltage of the left-hand (as viewed in Figure 3) active MOS region. A thin oxide layer 34 is then grown over the active device regions.
If it is desired to effect direct contact between the polysilicon and diffusion regions, an opening is formed in the thin oxide layer 34. A doped polysilicon layer 36 is deposited overthe overall structure, as shown in Figure 4.
Thereafter, the polysilicon layer 36 is patterned, as shown in Figure 5, and, as shown in Figure 6, with the use of two masking operations, n+ source and drain regions 38,40 are formed in the left-hand n-channel active MOS device, and p+ source and drain regions 42,44 are formed in the tub 28 to form a complementary p-channel active MOS device in the tub. As seen in Figure 6, the n deep regions 16 extend into the substrate to a depth several times that of the depth of field region 24 and the source and drain regions 42,44 of the MOS device formed in tub 28.
A phosphorous-doped silicon dioxide layer 46 is then deposited and patterned along with a metallization layer 48, which makes contact, as shown, to drain region 44 through an opening formed in layer46 and in thin oxide layer 34. The entire structure is then covered with a passivation layer 50 to complete the fabrication process.
As viewed in Figure 6, deep n region 1 6c is interposed between the field region 24 and contacts the left end of n-tub 28 and terminates at field region 24 and drain 42.
Deep n region 1 6c also contacts the right end of tub 28, as viewed in Figure 6, but is spaced from source 44. Another of the deep n regions 1 6a is interposed between the left end, as viewed in Figure 6. of the field region 24 and the source 40 of the complementary MOS device, and another deep n region 1 6b is formed at or near the central portion of the field region 24.
The deep n region 1 6c interposed between then tub 28 and the field region 24 provides several significant functions in the CMOS circuit of Figure 6.
First, the deep n region 1 6c serves as a guard ring or guard band to provide protection for the MOS device formed in tub 28 against substrate minority carrier effects.
Second, the deep n region 1 6c serves as a field threshold controlling region between p-channel active regions.
Third, the deep n region 1 6c overdopes the field implant regions 24 and thereby prevents the drain 42 from shorting to the p substrate 10, which, in the absence ofthe deep n region 1 6c, would require a separate mask operation. Fourth, the deep n region 1 6c provides a low resistance strap for the n-tub 28, thereby minimizing potential latch-up effects. In addition, one of the other deep n regions, e.g., region 1 6b, may serve as an extra rail to provide a connection to Vss in a static RAM, eras an additional interconnect formed without an additional masking operation.
Figure 7 illustrates a capacitor which may be formed in the CMOS structure of Figure 6 by the formation of an additional deep n region 1 6d during the step illustrated in Figure 1 at a location on the substrate removed from the complementary MOS device. The n deep region 1 6d extends between n regions 52 and 54 and forms with a polysilicon electrode 36 the two plates of a capacitor.
It will be appreciated that the novel CMOS integrated circuit described hereinabove effectively prevents or minimizes several potential problems in the operation of high-density CMOS circuits. It will be further understood that although the CMOS circuit of the invention and the method of its fabrication have been described with reference to a single embodiment, variations may be made thereto without necessarily departing from the spirit and scope of the invention. such as, for example, reversing the polarities (n and p) in the embodiment shown.

Claims (12)

1. In a CMOS integrated circuit structure comprising a substrate of a first conductivity type, a tub of a second opposite-conductivity type formed in a major surface of said substrate, spaced source and drain regions of said first conductivity type formed in said tub and defining a part of a first MOS active device, and a second complementary MOS active device formed in said surface of said substrate and spaced from said first MOS active device; the improvement which comprises a deep region of said second conductivity type but of a higher impurity concentration than that of said tub formed in said substrate surface between said first and second MOS active devices and substantially surrounding and contacting the outer periphery of said tub.
2. The CMOS integrated circuit of claim 1, in which said deep region extends into said substrate to a depth substantially equal to that of said tub.
3. The CMOS integrated circuit of claim 1, further comprising a thick field oxide region overlying a portion of said substrate and extending between said first and second MOS active devices, said tub being self-aligned with said thick field oxide region, said deep region being formed, at least in part, beneath the outer end of said thick field oxide region.
4. The CMOS integrated circuit of claim 3, further comprising a field region intermediate said first and second active MOS devices and underlying and selfaligned with said thick oxide region, said deep region being interposed intermediate one end of said field region and said first active MOS device and said tub.
5. The CMOS integrated circuit device of claim 4, in which said deep region extends into said substrate to a depth greater than that of said field region and to a depth substantially equal to that of said tub.
6. The CMOS integrated circuit of claim 5, further comprising a second deep region of said second conductivity type interposed between the other end of said field region and said, second. complementary active MOS device.
7. The CMOS integrated circuit of claim 1, in which said substrate includes an epitaxial layer of said first conductivity type on a base layer of said first conductivity type and at a higher impurity concentration, said deep region extending substantially to said base layer.
8. The CMOS integrated circuit of claim 6, further comprising a third deep region of said second conductivity type formed in said surface at a location spaced from said tub and from said second MOS device, said third deep region forming a capacitor with an overlying polysilicon electrode.
9. A processforfabricating aCMOS integrated circuit structure comprising the steps of providing a substrate of a first conductivity type, selectively forming a deep region of a second opposite conductivity type in an upper surface of said substrate, forming a tub of said second conduct ivity type but of a lower impurity concentration than that of said deep region, said deep region surrounding and in contact with the perimeter of said tub, forming a first active MOS device in said tub, and forming a second comple mentary active MOS device in said upper surface of said substrate and spaced from said tub, said deep region being interposed between said first and second active MOS devices.
10. The process of claim 9, further comprising the step of forming a field region of said first conductivity but at a higher impurity concentration than said substrate in the region intermediate said tub and said second active MOS device, at least one end of said field region terminating at and contacting one of said deep regions.
11. The process of claim 9, further comprising the step of forming a thick field oxide layer over said substrate, and employing said thick field oxide layer as a mask in the formation of said tub, whereby said tub is self-aligned with said thick field oxide layer.
12. A CMOS integrated circuit structure, or a process for fabricating the same, substantially as herein described with reference to the accompanying drawings.
GB08315618A 1982-09-13 1983-06-07 CMOS structure including deep region and process for fabrication Withdrawn GB2128021A (en)

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US41745682A 1982-09-13 1982-09-13

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GB2128021A true GB2128021A (en) 1984-04-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2218568B (en) * 1988-05-13 1993-01-20 Mitsubishi Electric Corp Semiconductor device and production method therefor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1359979A (en) * 1972-03-27 1974-07-17 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
GB1529297A (en) * 1975-05-08 1978-10-18 Nat Semiconductor Corp Self-aligned cmos process for bulk silicon device
GB2005092A (en) * 1977-10-03 1979-04-11 Motorola Inc Polyrity reversal circuit
GB1558142A (en) * 1976-02-25 1979-12-19 Intel Corp High density cmos process
GB1559583A (en) * 1975-07-18 1980-01-23 Tokyo Shibaura Electric Co Complementary mosfet device and method of manufacturing the same
EP0009782A1 (en) * 1978-09-28 1980-04-16 Kabushiki Kaisha Toshiba CMOS Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1359979A (en) * 1972-03-27 1974-07-17 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
GB1529297A (en) * 1975-05-08 1978-10-18 Nat Semiconductor Corp Self-aligned cmos process for bulk silicon device
GB1559583A (en) * 1975-07-18 1980-01-23 Tokyo Shibaura Electric Co Complementary mosfet device and method of manufacturing the same
GB1558142A (en) * 1976-02-25 1979-12-19 Intel Corp High density cmos process
GB2005092A (en) * 1977-10-03 1979-04-11 Motorola Inc Polyrity reversal circuit
EP0009782A1 (en) * 1978-09-28 1980-04-16 Kabushiki Kaisha Toshiba CMOS Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2218568B (en) * 1988-05-13 1993-01-20 Mitsubishi Electric Corp Semiconductor device and production method therefor

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Publication number Publication date
GB8315618D0 (en) 1983-07-13
JPS5961168A (en) 1984-04-07

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