US6855618B2 - Radiation hardened semiconductor device - Google Patents

Radiation hardened semiconductor device Download PDF

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US6855618B2
US6855618B2 US10/284,230 US28423002A US6855618B2 US 6855618 B2 US6855618 B2 US 6855618B2 US 28423002 A US28423002 A US 28423002A US 6855618 B2 US6855618 B2 US 6855618B2
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implant
region
isolation region
blocking layer
layer
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US20040166648A1 (en
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Richard L. Woodruff
Scott M. Tyson
John T. Chaffee
David B. Kerwin
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Frontgrade Colorado Springs LLC
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Aeroflex Colorado Springs Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Definitions

  • This invention relates to radiation hardening of semiconductor devices and more particularly to radiation hardening of the birds beak region to prevent formation of leakage paths in high radiation environments.
  • Electron-hole pairs generated in the bulk silicon do not present a severe problem, as the electrons and holes recombine rapidly.
  • Electron-hole pairs formed in silicon dioxide are more difficult to deal with because the electrons are far more mobile than the holes and may become separated from the holes, making recombination more difficult and resulting in an accumulation of net positive charge in the silicon dioxide, or other dielectric film.
  • the conventional process for laterally isolating semiconductor circuits uses a field oxide between the active regions.
  • the most common method of producing this field oxide is the localized oxidation of silicon (LOCOS) process. This results in a thick oxide layer separating adjacent semiconductor devices. This thick oxide layer is extremely susceptible to trapping positive charge in an ionizing environment. This effect is cumulative and eventually results in lowering of the threshold voltage of the parasitic field oxide transistors occurring under the field oxide, so that adjacent transistors are no longer isolated from one another.
  • LOC localized oxidation of silicon
  • N-Channel transistors formed in a P-Well, separated by field oxide, are particularly affected by this phenomenon.
  • the trapped positive charge in the field oxide repels positively charged carriers (holes) and attracts negatively charged carriers (electrons) in the surface of the underlying silicon layer.
  • This accumulation of negatively charged carriers in the P-Well adjacent to the field oxide causes inversion of the P-type silicon and creates a conductive channel or leakage path between N-doped drain and source regions of adjacent N-Channel transistors.
  • the accumulated negative charge in the P-Well region can also create a leakage path from the source to drain of a single N-Channel transistor, thus shorting out the N-Channel transistor.
  • Another possible leakage path occurs between a P-Well active region adjacent to an N-Well active region, especially where polysilicon is used as an interconnect between both active regions. Thus, these undesirable parasitic transistors dominate circuit behavior and the circuit can no longer function as designed.
  • the area that will be the field oxide region is implanted before growth of the field oxide with an ion dose that is calculated to suppress the operation of parasitic transistors under normal (no ionizing radiation) environments and operating conditions.
  • the field oxide is conventionally grown by a wet thermal process, using a LOCOS process or variations thereof. With the field implant process, there is a dopant gradient extending down into the substrate, with a high concentration at the surface changing to a background bulk concentration at some depth below the surface.
  • the nature of the bulk silicon underlying the semiconductor circuit will depend on the nature of the process used to fabricate the circuit, such as NMOS, PMOS, or CMOS processes. Through the use of this method it is not possible to obtain the doping concentrations necessary to produce radiation hardened devices with acceptable performance for radiation doses greater than about 10 to 20 krad(Si).
  • An object of the present invention is to produce a radiation hardened semiconductor device that can perform in an ionizing radiation environment.
  • a further object of the present invention is to produce a radiation hardened semiconductor device compatible with commercial manufacturing processes.
  • Another object of the present invention is to suppress the operation of parasitic transistors in the bird's beak region of a field oxide in a radiation environment.
  • a radiation hardened semiconductor device is formed by modifying a conventional semiconductor manufacturing process.
  • a LOGOS process, or variants thereof, are used in many conventional semiconductor manufacturing processes for isolating adjacent transistors in a semiconductor device.
  • LOCOS results in a transition region formed at the edges of the active region known as a bird's beak which is particularly susceptible to the formation of parasitic transistors.
  • the bird's beak region is implanted with an implant, such as germanium, and the implant is annealed.
  • An implant blocking layer is then applied to the active area, again exposing the bird's beak region.
  • the bird's beak region is then implanted with a dopant such as boron.
  • the implant blocking layer is then removed. Further processing of the semiconductor can then be performed in accordance with conventional techniques.
  • the present invention has the utility of producing a radiation hardened semiconductor device that can perform in a high radiation environment.
  • the present invention has the further utility of producing radiation hardened semiconductor devices compatible with commercial manufacturing processes.
  • the present invention also has the utility of suppressing the operation of parasitic transistors in the bird's beak region of a field oxide in a high radiation environment.
  • FIG. 1 illustrates a cross sectional area of a semiconductor substrate with an active area and a LOCOS field isolation in place;
  • FIG. 2 illustrates a plan view of a semiconductor substrate with an implant blocking layer, according to the current invention, disposed on an upper surface thereof;
  • FIG. 3 illustrates a cross sectional area of the implant blocking layer taken along line 3 — 3 of FIG. 2 ;
  • FIG. 4 illustrates a plan view of a semiconductor substrate with a second type of implant blocking layer, according to the present invention, disposed on an upper surface thereof;
  • FIG. 5 illustrates a cross sectional area of the implant blocking layer taken along line 5 — 5 of FIG. 4 ;
  • FIG. 6 illustrates a cross sectional area of the implant blocking layer taken along line 6 — 6 of FIG. 4 .
  • FIG. 7 illustrates a cross-sectional area of a semiconductor substrate with an active area and a LOCOS isolation in place, and a doped epitaxial layer underlying the active and isolation regions.
  • an N-channel insulating gate field effect transistor (IGFET) in the early stages of manufacture is illustrated.
  • the bulk silicon 10 has been doped with a P-type dopant.
  • This bulk silicon region may have been formed in an epitaxially grown silicon layer on a substrate that may be N-type or P-type silicon, or an epitaxial layer of silicon on an N-type or P-type bulk silicon, or an insulating substrate such as but not limited to sapphire, silicon-on-insulator (SOI), or other compatible insulating substrate.
  • the active regions 20 are defined as are the isolation regions 30 .
  • a field oxide 100 has been formed in the isolation region 30 through a conventional LOCOS process, or variations thereof such as, but not limited to, polysilicon buffered LOCOS techniques, or recessed LOCOS techniques.
  • the field oxide 100 has a thickness of within a range of 1,000 to 10,000 Angstroms.
  • a masking layer 102 such as silicon nitride is located superadjacent a pad oxide 101 , which is located superadjacent the active region 20 .
  • the pad oxide 101 can be either deposited or grown in accordance with known methods and has a thickness of within a range of 50 to 800 Angstroms.
  • the silicon nitride layer 102 overlying the edges of the active region 20 is forced upward as the silicon is oxidized, forming a tapered region known as the bird's beak region 104 .
  • the silicon nitride layer 102 is selectively removed by conventional means, such as chemical wet etch or plasma etch processes.
  • the thickness of the pad oxide, used to prevent channeling during the subsequent implant is 50 to 800 Angstroms; however, the pad oxide 101 may also be removed prior to subsequent processing.
  • FIG. 2 illustrates the active regions 20 with an implant blocking layer 60 disposed on an upper surface thereof.
  • N-portions 40 and P-portions 50 indicate areas of the active region 20 that will subsequently be implanted with N and P dopant respectively, for the eventual formation of an N-Channel IGFET.
  • N-portions 40 when implanted, will become the source and drain regions, while P-portions 50 will become the channel well region.
  • a gate layer (not shown) will be formed overlying substantially all of P-portion 50 .
  • the gate layer is comprised of a thin dielectric layer, including but not limited to silicon oxide, and a layer of overlying metallic or semiconducting material, including but not limited to polysilicon.
  • first implant is performed without any implant barrier layer.
  • first implant is germanium and is implanted at a dose within a range of 1 ⁇ 10 15 ions/cm 2 to 1 ⁇ 10 17 ions/cm 2 at an energy level of within a range 50 keV to 500 keV.
  • the preferred species of germanium are 74 Ge + , 72 Ge + , 74 Ge ++ and 72 Ge ++ .
  • the preferred implant angle is within a range of 0° to 45°.
  • the pad oxide 101 and a portion of the field oxide 100 are then removed by conventional means, such as chemical wet etch or plasma etch processes.
  • the semiconductor device 5 is then annealed at a temperature within a range of 550° C. to 1,100° C. for a time within a range of 1 minute to 100 hours, in an ambient gas including but not limited to nitrogen, argon, and/or oxygen, to incorporate the first implant into the lattice (not shown) of the semiconductor 5 .
  • a screening oxide (not shown) is grown or deposited over the active region 20 .
  • the screening oxide serves to prevent channeling of the subsequent second implant; however, the subsequent second implant may be performed without formation of the screening oxide.
  • FIG. 2 illustrates the pattern according to the first embodiment wherein the implant barrier layer 60 remains over the active area 20 while exposing the implant area 70 .
  • the implant area 70 is defined as the active portion of area 20 that comprises the bird's beak region 104 of the field oxide 100 .
  • the isolation region 30 is also exposed.
  • An implant of the implant area 70 and the isolation region 30 is performed using a P-type dopant such as boron.
  • a P-type dopant such as boron.
  • the boron is implanted at a dose within a range of 1 ⁇ 10 11 ion/cm 2 to 5 ⁇ 10 14 ions/cm 2 at an energy level within a range 20 keV to 100 keV at an implant angle of 0 to 45° with a preferred angle of 0°.
  • the preferred boron-containing species are 11 B + and BF 2 + .
  • the implant barrier layer 60 is then removed by conventional means, such as an ashing process followed by a wet chemical clean.
  • the screening oxide is then removed by conventional means, such as wet chemical etch. Further processing of the semiconductor 5 are performed in accordance with conventional techniques.
  • the process follows the same steps as the preferred embodiment with the exception that an implant barrier 60 is applied prior to the first implant.
  • the cross section of the implant barrier 60 is shown in FIG 3 .
  • the implant barrier 60 is removed prior to annealing the first implant.
  • FIGS. 4 through 6 A third and fourth embodiment of the subject invention are illustrated in FIGS. 4 through 6 .
  • the process for the third embodiment follows the same steps as the preferred embodiment with the exception that the implant barrier 108 is defined to expose a portion of the active area 20 that comprises the bird's beak region 104 that will subsequently underlie the gate layer.
  • the process of the fourth embodiment follows the same steps of second embodiment with the exception that the implant barrier 108 is defined to expose a portion of the active area 20 that comprises the bird's beak region 104 that will subsequently underlie the gate layer.
  • the process follows the same steps as the preferred embodiment with the exception that the first implant and the anneal are omitted.
  • the implant that would have been used in the first implant has been previously incorporated into an epitaxial silicon layer 80 of the substrate as shown in FIG. 7 using conventional techniques such as but not limited to molecular beam epitaxy or thermal chemical vapor deposition epitaxy.
  • the preferred implant concentration is within a range of 1 ⁇ 10 16 cm ⁇ 3 to 8 ⁇ 10 22 cm ⁇ 3 .
  • This embodiment accrues additional advantages for radiation hardness when the substrate is insulating (such as SOI wherein the insulation can be sapphire or silicon oxide), and the bottom of the field oxide abuts the insulating substrate. In this case, the parasitic transistor between adjacent IGFET's is eliminated. The parasitic bird's beak leakage path still exists, but its operation under irradiation is suppressed by the processing steps of this embodiment.
  • the process follows the same steps as the third embodiment with the exception that the first implant and the anneal are omitted.
  • the implant that would have been used in the first implant has been previously incorporated into an epitaxial silicon layer following the method of the fifth embodiment.
  • the method of the first embodiment is followed with the exception that the first implant is performed before the field oxide 100 is formed, using the LOCOS hard mask 102 as the implant barrier for said first implant.
  • the formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam.
  • the preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
  • the method of the first embodiment is followed with the exception that a first implant is performed before the field oxide 100 is formed, using the LOCOS hard mask 102 as the implant barrier for said first implant, in addition to a second implant of the first implant that occurs after the field oxide has been formed following the method of the first embodiment.
  • the formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam.
  • the preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
  • the method of the second embodiment is followed with the exception that the first implant is performed before the field oxide 100 is formed using the LOCOS hard mask 102 as the implant barrier for said first implant.
  • the formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam.
  • the preferred absolute pressure is between 0.5 and 40 atmospheres, with partial steam between 0.1 and 40 atmospheres.
  • the method of the second embodiment is followed with the exception that a first implant is performed before the field oxide 100 informed, using the LOCOS hard mask 102 as the implant barrier for said first implant, in addition to a second implant of the first implant that occurs after the field oxide has been formed using the implant barrier 60 , following the method of the first embodiment.
  • the formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam.
  • the preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
  • the first, second, third, fourth, seventh, eighth, ninth, and tenth embodiments can be further modified such that the anneal of the first implant is omitted.
  • the second, third, fourth, eighth, and tenth embodiments can be further modified such that the implant barriers 60 and 108 for the first and second implants may be interchanged.
  • the fifth and sixth embodiments can be modified by performing an implant of the first implant after the field oxide has been formed in addition to the previous incorporation of the first implant into the epitaxial layer.

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Abstract

A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is implanted with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The implanted area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Description

This is a divisional application of application Ser. No. 09/072,932, filed May 5, 1998, now U.S. Pat. No. 6,511,893.
TECHNICAL FIELD
This invention relates to radiation hardening of semiconductor devices and more particularly to radiation hardening of the birds beak region to prevent formation of leakage paths in high radiation environments.
BACKGROUND ART
The field of radiation hardening in semiconductor devices deals in part with the problem of electron-hole pairs generated by the passage of ionizing radiation through the semiconductor devices. Electron-hole pairs generated in the bulk silicon do not present a severe problem, as the electrons and holes recombine rapidly. Electron-hole pairs formed in silicon dioxide are more difficult to deal with because the electrons are far more mobile than the holes and may become separated from the holes, making recombination more difficult and resulting in an accumulation of net positive charge in the silicon dioxide, or other dielectric film.
The conventional process for laterally isolating semiconductor circuits uses a field oxide between the active regions. The most common method of producing this field oxide is the localized oxidation of silicon (LOCOS) process. This results in a thick oxide layer separating adjacent semiconductor devices. This thick oxide layer is extremely susceptible to trapping positive charge in an ionizing environment. This effect is cumulative and eventually results in lowering of the threshold voltage of the parasitic field oxide transistors occurring under the field oxide, so that adjacent transistors are no longer isolated from one another.
N-Channel transistors, formed in a P-Well, separated by field oxide, are particularly affected by this phenomenon. The trapped positive charge in the field oxide repels positively charged carriers (holes) and attracts negatively charged carriers (electrons) in the surface of the underlying silicon layer. This accumulation of negatively charged carriers in the P-Well adjacent to the field oxide causes inversion of the P-type silicon and creates a conductive channel or leakage path between N-doped drain and source regions of adjacent N-Channel transistors. The accumulated negative charge in the P-Well region can also create a leakage path from the source to drain of a single N-Channel transistor, thus shorting out the N-Channel transistor. Another possible leakage path occurs between a P-Well active region adjacent to an N-Well active region, especially where polysilicon is used as an interconnect between both active regions. Thus, these undesirable parasitic transistors dominate circuit behavior and the circuit can no longer function as designed.
Conventionally, the area that will be the field oxide region is implanted before growth of the field oxide with an ion dose that is calculated to suppress the operation of parasitic transistors under normal (no ionizing radiation) environments and operating conditions. The field oxide is conventionally grown by a wet thermal process, using a LOCOS process or variations thereof. With the field implant process, there is a dopant gradient extending down into the substrate, with a high concentration at the surface changing to a background bulk concentration at some depth below the surface. The nature of the bulk silicon underlying the semiconductor circuit will depend on the nature of the process used to fabricate the circuit, such as NMOS, PMOS, or CMOS processes. Through the use of this method it is not possible to obtain the doping concentrations necessary to produce radiation hardened devices with acceptable performance for radiation doses greater than about 10 to 20 krad(Si).
Another known method is described in commonly owned U.S. Pat. No. 5,037,781 which teaches a process wherein a first high quality oxide layer is deposited over the silicon substrate. This first layer acts as a diffusion barrier. A second layer of a thick heavily doped oxide, containing recombination sites for the electrons and holes, is then deposited over the first layer. A second diffusion barrier of silicon dioxide is then deposited over the thick heavily doped layer. This art requires a unique manufacturing process which is substantially different from most commercial manufacturing processes and therefore adversely impacts the cost of radiation hardened devices.
Therefore, there exists a need for a radiation hardened semiconductor device capable of functioning in an ionizing radiation environment of approximately 100 krad(Si).
Furthermore, there exists a need for producing such a radiation hardened semiconductor device through modification of existing commercial semiconductor manufacturing processes.
DISCLOSURE OF INVENTION
An object of the present invention is to produce a radiation hardened semiconductor device that can perform in an ionizing radiation environment.
A further object of the present invention is to produce a radiation hardened semiconductor device compatible with commercial manufacturing processes.
Another object of the present invention is to suppress the operation of parasitic transistors in the bird's beak region of a field oxide in a radiation environment.
According to the present invention, a radiation hardened semiconductor device is formed by modifying a conventional semiconductor manufacturing process. A LOGOS process, or variants thereof, are used in many conventional semiconductor manufacturing processes for isolating adjacent transistors in a semiconductor device. LOCOS results in a transition region formed at the edges of the active region known as a bird's beak which is particularly susceptible to the formation of parasitic transistors. According to the present invention, the bird's beak region is implanted with an implant, such as germanium, and the implant is annealed. An implant blocking layer is then applied to the active area, again exposing the bird's beak region. The bird's beak region is then implanted with a dopant such as boron. The implant blocking layer is then removed. Further processing of the semiconductor can then be performed in accordance with conventional techniques.
The present invention has the utility of producing a radiation hardened semiconductor device that can perform in a high radiation environment. The present invention has the further utility of producing radiation hardened semiconductor devices compatible with commercial manufacturing processes. The present invention also has the utility of suppressing the operation of parasitic transistors in the bird's beak region of a field oxide in a high radiation environment.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 illustrates a cross sectional area of a semiconductor substrate with an active area and a LOCOS field isolation in place;
FIG. 2 illustrates a plan view of a semiconductor substrate with an implant blocking layer, according to the current invention, disposed on an upper surface thereof;
FIG. 3 illustrates a cross sectional area of the implant blocking layer taken along line 3—3 of FIG. 2;
FIG. 4 illustrates a plan view of a semiconductor substrate with a second type of implant blocking layer, according to the present invention, disposed on an upper surface thereof;
FIG. 5 illustrates a cross sectional area of the implant blocking layer taken along line 5—5 of FIG. 4;
FIG. 6 illustrates a cross sectional area of the implant blocking layer taken along line 6—6 of FIG. 4.
FIG. 7 illustrates a cross-sectional area of a semiconductor substrate with an active area and a LOCOS isolation in place, and a doped epitaxial layer underlying the active and isolation regions.
 BEST MODE FOR CARRYING OUT THE INVENTION
The process steps necessary for radiation hardening a semiconductor device and those commonly known process steps necessary for illustrating the claimed invention are described herein.
Referring to FIG. 1, an N-channel insulating gate field effect transistor (IGFET) in the early stages of manufacture is illustrated. The bulk silicon 10 has been doped with a P-type dopant. This bulk silicon region may have been formed in an epitaxially grown silicon layer on a substrate that may be N-type or P-type silicon, or an epitaxial layer of silicon on an N-type or P-type bulk silicon, or an insulating substrate such as but not limited to sapphire, silicon-on-insulator (SOI), or other compatible insulating substrate. The active regions 20 are defined as are the isolation regions 30. A field oxide 100 has been formed in the isolation region 30 through a conventional LOCOS process, or variations thereof such as, but not limited to, polysilicon buffered LOCOS techniques, or recessed LOCOS techniques. The field oxide 100 has a thickness of within a range of 1,000 to 10,000 Angstroms. A masking layer 102 such as silicon nitride is located superadjacent a pad oxide 101, which is located superadjacent the active region 20. The pad oxide 101 can be either deposited or grown in accordance with known methods and has a thickness of within a range of 50 to 800 Angstroms.
During formation of the field oxide 100 a portion of the active region 20 underlying the silicon nitride is converted from silicon to silicon oxide (SixOy). Because the molecular volume of silicon oxide is approximately twice that of the atomic volume of silicon, the silicon nitride layer 102 overlying the edges of the active region 20 is forced upward as the silicon is oxidized, forming a tapered region known as the bird's beak region 104.
The silicon nitride layer 102 is selectively removed by conventional means, such as chemical wet etch or plasma etch processes. In the preferred embodiment, the thickness of the pad oxide, used to prevent channeling during the subsequent implant, is 50 to 800 Angstroms; however, the pad oxide 101 may also be removed prior to subsequent processing.
FIG. 2 illustrates the active regions 20 with an implant blocking layer 60 disposed on an upper surface thereof. N-portions 40 and P-portions 50, indicate areas of the active region 20 that will subsequently be implanted with N and P dopant respectively, for the eventual formation of an N-Channel IGFET. N-portions 40, when implanted, will become the source and drain regions, while P-portions 50 will become the channel well region. During further processing a gate layer (not shown) will be formed overlying substantially all of P-portion 50. The gate layer is comprised of a thin dielectric layer, including but not limited to silicon oxide, and a layer of overlying metallic or semiconducting material, including but not limited to polysilicon.
In the preferred embodiment, the first implant is performed without any implant barrier layer. In the preferred embodiment, first implant is germanium and is implanted at a dose within a range of 1×1015ions/cm2 to 1×1017 ions/cm2 at an energy level of within a range 50 keV to 500 keV. The preferred species of germanium are 74Ge+, 72Ge+, 74Ge++ and 72Ge++. The preferred implant angle is within a range of 0° to 45°.
After the first implant, the pad oxide 101 and a portion of the field oxide 100 are then removed by conventional means, such as chemical wet etch or plasma etch processes. The semiconductor device 5 is then annealed at a temperature within a range of 550° C. to 1,100° C. for a time within a range of 1 minute to 100 hours, in an ambient gas including but not limited to nitrogen, argon, and/or oxygen, to incorporate the first implant into the lattice (not shown) of the semiconductor 5.
After the anneal of the first implant a screening oxide (not shown) is grown or deposited over the active region 20. The screening oxide serves to prevent channeling of the subsequent second implant; however, the subsequent second implant may be performed without formation of the screening oxide.
An implant barrier layer 60 is then applied to the upper surface of the field oxide 100 and the active area 20. In the preferred embodiment, the implant barrier layer 60 is photoresist, although any material that can be selectively etched relative to both silicon and silicon dioxide, and block the implant of the dopants to be implanted, may be used. FIG. 2 illustrates the pattern according to the first embodiment wherein the implant barrier layer 60 remains over the active area 20 while exposing the implant area 70. The implant area 70 is defined as the active portion of area 20 that comprises the bird's beak region 104 of the field oxide 100. The isolation region 30 is also exposed.
An implant of the implant area 70 and the isolation region 30 is performed using a P-type dopant such as boron. In the preferred embodiment the boron is implanted at a dose within a range of 1×1011 ion/cm2 to 5×1014 ions/cm2 at an energy level within a range 20 keV to 100 keV at an implant angle of 0 to 45° with a preferred angle of 0°. The preferred boron-containing species are 11B+ and BF2 +.
The implant barrier layer 60 is then removed by conventional means, such as an ashing process followed by a wet chemical clean. The screening oxide is then removed by conventional means, such as wet chemical etch. Further processing of the semiconductor 5 are performed in accordance with conventional techniques.
In a second embodiment of the subject invention, the process follows the same steps as the preferred embodiment with the exception that an implant barrier 60 is applied prior to the first implant. The cross section of the implant barrier 60 is shown in FIG 3. The implant barrier 60 is removed prior to annealing the first implant.
A third and fourth embodiment of the subject invention are illustrated in FIGS. 4 through 6. The process for the third embodiment follows the same steps as the preferred embodiment with the exception that the implant barrier 108 is defined to expose a portion of the active area 20 that comprises the bird's beak region 104 that will subsequently underlie the gate layer.
The process of the fourth embodiment follows the same steps of second embodiment with the exception that the implant barrier 108 is defined to expose a portion of the active area 20 that comprises the bird's beak region 104 that will subsequently underlie the gate layer.
In a fifth embodiment of the subject invention, the process follows the same steps as the preferred embodiment with the exception that the first implant and the anneal are omitted. In this embodiment, the implant that would have been used in the first implant has been previously incorporated into an epitaxial silicon layer 80 of the substrate as shown in FIG. 7 using conventional techniques such as but not limited to molecular beam epitaxy or thermal chemical vapor deposition epitaxy. In this embodiment, the preferred implant concentration is within a range of 1×1016 cm−3 to 8×1022 cm−3. This embodiment accrues additional advantages for radiation hardness when the substrate is insulating (such as SOI wherein the insulation can be sapphire or silicon oxide), and the bottom of the field oxide abuts the insulating substrate. In this case, the parasitic transistor between adjacent IGFET's is eliminated. The parasitic bird's beak leakage path still exists, but its operation under irradiation is suppressed by the processing steps of this embodiment.
In a sixth embodiment of the subject invention, the process follows the same steps as the third embodiment with the exception that the first implant and the anneal are omitted. In this embodiment, the implant that would have been used in the first implant has been previously incorporated into an epitaxial silicon layer following the method of the fifth embodiment.
In a seventh embodiment of the subject invention, the method of the first embodiment is followed with the exception that the first implant is performed before the field oxide 100 is formed, using the LOCOS hard mask 102 as the implant barrier for said first implant. The formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam. The preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
In an eighth embodiment of the subject invention, the method of the first embodiment is followed with the exception that a first implant is performed before the field oxide 100 is formed, using the LOCOS hard mask 102 as the implant barrier for said first implant, in addition to a second implant of the first implant that occurs after the field oxide has been formed following the method of the first embodiment. The formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam. The preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
In a ninth embodiment of the subject invention, the method of the second embodiment is followed with the exception that the first implant is performed before the field oxide 100 is formed using the LOCOS hard mask 102 as the implant barrier for said first implant. The formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam. The preferred absolute pressure is between 0.5 and 40 atmospheres, with partial steam between 0.1 and 40 atmospheres.
In a tenth embodiment of the subject invention, the method of the second embodiment is followed with the exception that a first implant is performed before the field oxide 100 informed, using the LOCOS hard mask 102 as the implant barrier for said first implant, in addition to a second implant of the first implant that occurs after the field oxide has been formed using the implant barrier 60, following the method of the first embodiment. The formation of the field oxide in this embodiment is accomplished by atmospheric or high pressure thermal oxidation in an ambient containing a certain partial pressure of steam. The preferred absolute pressure is between 0.5 and 40 atmospheres, with partial pressure of steam between 0.1 and 40 atmospheres.
The first, second, third, fourth, seventh, eighth, ninth, and tenth embodiments can be further modified such that the anneal of the first implant is omitted. The second, third, fourth, eighth, and tenth embodiments can be further modified such that the implant barriers 60 and 108 for the first and second implants may be interchanged. The fifth and sixth embodiments can be modified by performing an implant of the first implant after the field oxide has been formed in addition to the previous incorporation of the first implant into the epitaxial layer.
It should be understood by those skilled in the art that obvious process modification can be made without departing from the spirit of the invention such as but not limited to alternate mask geometries for implant barriers and multiple implants within the same energy range as taught herein. Accordingly, reference should be made primarily to the accompanying claims, rather than the foregoing specification, to determine the scope of the subject invention.

Claims (19)

1. A method of manufacturing a radiation hardened semiconductor device including a substrate and epitaxial layer, wherein the epitaxial layer includes germanium, the epitaxial layer including an active region and an isolation region therein, the active region including an upper surface and the isolation region including an upper surface, the active region further including a bird's beak therein, comprising:
depositing a first implant blocking layer on the upper surface of the isolation region and the upper surface of the active region;
removing a section of said first implant blocking layer to expose at least a portion of the upper surface of the isolation region and the bird's beak;
implanting the exposed portion of the isolation region and the bird's beak with a dopant; and
removing said first implant blocking layer.
2. The method of claim 1 wherein the said germanium comprises at least one of 74Ge+, 72Ge+, 74Ge++ and 72Ge++.
3. The method of claim 2 wherein the dopant is implanted at a dose within a range of 1×1010 cm−2 to 5×1014 cm−2 at an energy within a range of 20 keV to 100 keV.
4. The method of claim 3 wherein the implant comprises at least one of 74Ge+, 72Ge+, 74Ge++ and 72Ge++.
5. The method of claim 4 wherein the dopant is implanted at a dose within a range of 1×1011 cm−2 to 5×1014 cm−2 at an energy within a range of 20 keV to 100 keV.
6. The method of claim 1 wherein the dopant comprises boron.
7. The method of claim 1 wherein the implant has a concentration within a range of 1×1016 cm−3 to 8×1022 cm−3.
8. The method of claim 1 wherein a pad oxide is located on the upper surface of the active region, prior to applying said first implant blocking layer, further comprising:
removing the pad oxide; and
growing a screening oxide on the upper surface of the active region.
9. The method of claim 8 wherein the dopant comprises boron.
10. The method of claim 8 wherein the implant has a concentration within a range of 1×1016 cm−3 to 8×1022 cm−3.
11. The method of claim 1 wherein the substrate includes an upper surface in contact with the epitaxial layer, said upper surface comprising an insulating material.
12. The method of claim 11 wherein said insulating material comprises silicon oxide.
13. The method of claim 11 wherein said insulating material comprises sapphire.
14. The method of claim 1 wherein said section of said first implant blocking layer is removed to expose the upper surface of the isolation region and a portion of the bird's beak region, adapted to be covered by a gate layer.
15. A method of forming a radiation hardened semiconductor device including a semiconductor substrate having an upper surface, comprising:
depositing a masking layer on the upper surface;
removing a portion of said masking layer to expose an isolation region, wherein a remaining portion of said masking layer defines an active region;
implanting an upper surface of the isolation region with an implant comprising germanium;
oxidizing said isolation region to form a field oxide, wherein a portion of said implant is incorporated into said field oxide, and wherein a portion of said field oxide underlies the active region, said portion of said field oxide known as a bird's beak;
removing said remaining portion of said masking layer;
applying a first implant blocking layer on said upper surface of the isolation region and an upper surface of the active region;
removing a section of said first implant blocking layer to expose at least a portion of said upper surface of said isolation region and said bird's beak
implanting said exposed portion of said isolation region and said bird's beak with a dopant; and
removing said first implant blocking layer.
16. The method of claim 15, prior to applying said first implant blocking layer, further comprising implanting said isolation region and said active region with said implant.
17. The method of claim 16, prior to the step of implanting said first dopant, further comprising the steps of:
applying a second implant blocking layer to said upper surface of said isolation region and said upper surface of said active region; and
removing a section of said second implant blocking layer and exposing said isolation and said bird's beak region; and
removing said second implant blocking layer after the step if implanting said first dopant.
18. The method of claim 17 wherein said section of said first implant blocking layer is removed to expose said upper surface of said isolation region and a portion of said bird's beak region adapted to be covered by a gate layer and wherein said section of said second implant blocking layer is removed to expose said upper surface of said isolation region and a portion of said bird's beak region adapted to be covered by a gate layer.
19. The method of claim 15 wherein said section of said first implant blocking layer is removed to expose said upper surface of said isolation region and a portion of said bird's beak region adapted to be covered by a gate layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8223918B2 (en) 2006-11-21 2012-07-17 Varian Medical Systems, Inc. Radiation scanning and disabling of hazardous targets in containers

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170147B2 (en) * 2003-07-28 2007-01-30 Lucent Technologies Inc. Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames
JP4673072B2 (en) * 2005-01-24 2011-04-20 Ｏｋｉセミコンダクタ株式会社 Manufacturing method of semiconductor device
US7518218B2 (en) * 2005-03-03 2009-04-14 Aeroflex Colorado Springs, Inc. Total ionizing dose suppression transistor architecture
US7809973B2 (en) 2005-11-16 2010-10-05 Cypress Semiconductor Corporation Spread spectrum clock for USB
WO2013078439A2 (en) 2011-11-22 2013-05-30 Silicon Space Technology Corporation Memory circuit incorporating radiation hardened memory scrub engine
US9667240B2 (en) 2011-12-02 2017-05-30 Cypress Semiconductor Corporation Systems and methods for starting up analog circuits
US9268637B2 (en) 2013-03-15 2016-02-23 Silicon Space Technology Corporation Memory circuit incorporating error detection and correction (EDAC), method of operation, and system
CN111863607B (en) * 2020-07-28 2023-05-05 哈尔滨工业大学 Anti-radiation power transistor and preparation method thereof

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179311A (en) 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
US4442591A (en) 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
US4728619A (en) 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
US4748131A (en) 1987-02-06 1988-05-31 The Aerospace Corporation Method for increasing radiation hardness of MOS gate oxides
EP0273702A2 (en) 1986-12-29 1988-07-06 General Electric Company Radiation hardening techniques for metal-oxide silicon devices
EP0313777A2 (en) 1987-10-30 1989-05-03 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US4849366A (en) 1988-01-15 1989-07-18 Industrial Technology Research Institute Method of making a gated isolated structure
WO1990005993A1 (en) 1988-11-21 1990-05-31 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5047356A (en) 1990-02-16 1991-09-10 Hughes Aircraft Company High speed silicon-on-insulator device and process of fabricating same
US5126278A (en) 1989-11-21 1992-06-30 Kabushiki Kaisha Toshiba Method of manufacturing bipolar transistor by implanting intrinsic impurities
US5173438A (en) 1991-02-13 1992-12-22 Micron Technology, Inc. Method of performing a field implant subsequent to field oxide fabrication by utilizing selective tungsten deposition to produce encroachment-free isolation
US5192712A (en) 1992-04-15 1993-03-09 National Semiconductor Corporation Control and moderation of aluminum in silicon using germanium and germanium with boron
US5242849A (en) 1991-05-24 1993-09-07 Nippon Steel Corporation Method for the fabrication of MOS devices
US5247199A (en) 1986-01-15 1993-09-21 Harris Corporation Process for forming twin well CMOS integrated circuits
US5358890A (en) 1993-04-19 1994-10-25 Motorola Inc. Process for fabricating isolation regions in a semiconductor device
US5474940A (en) 1992-01-08 1995-12-12 Sony Corporation Method of fabricating a semiconductor device having shallow junctions in source-drain regions and a gate electrode with a low resistance silicide layer
US5604370A (en) 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
US6008098A (en) 1996-10-04 1999-12-28 Advanced Micro Devices, Inc. Ultra shallow junction formation using amorphous silicon layer

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4179311A (en) 1977-01-17 1979-12-18 Mostek Corporation Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides
US4442591A (en) 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
US5247199A (en) 1986-01-15 1993-09-21 Harris Corporation Process for forming twin well CMOS integrated circuits
US5429958A (en) 1986-01-15 1995-07-04 Harris Corporation Process for forming twin well CMOS integrated circuits
EP0273702A2 (en) 1986-12-29 1988-07-06 General Electric Company Radiation hardening techniques for metal-oxide silicon devices
US4748131A (en) 1987-02-06 1988-05-31 The Aerospace Corporation Method for increasing radiation hardness of MOS gate oxides
US4728619A (en) 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
EP0313777A2 (en) 1987-10-30 1989-05-03 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices
US4849366A (en) 1988-01-15 1989-07-18 Industrial Technology Research Institute Method of making a gated isolated structure
WO1990005993A1 (en) 1988-11-21 1990-05-31 Micron Technology, Inc. High performance sub-micron p-channel transistor with germanium implant
US5126278A (en) 1989-11-21 1992-06-30 Kabushiki Kaisha Toshiba Method of manufacturing bipolar transistor by implanting intrinsic impurities
US5047356A (en) 1990-02-16 1991-09-10 Hughes Aircraft Company High speed silicon-on-insulator device and process of fabricating same
US5173438A (en) 1991-02-13 1992-12-22 Micron Technology, Inc. Method of performing a field implant subsequent to field oxide fabrication by utilizing selective tungsten deposition to produce encroachment-free isolation
US5242849A (en) 1991-05-24 1993-09-07 Nippon Steel Corporation Method for the fabrication of MOS devices
US5474940A (en) 1992-01-08 1995-12-12 Sony Corporation Method of fabricating a semiconductor device having shallow junctions in source-drain regions and a gate electrode with a low resistance silicide layer
US5192712A (en) 1992-04-15 1993-03-09 National Semiconductor Corporation Control and moderation of aluminum in silicon using germanium and germanium with boron
US5358890A (en) 1993-04-19 1994-10-25 Motorola Inc. Process for fabricating isolation regions in a semiconductor device
US5604370A (en) 1995-07-11 1997-02-18 Advanced Micro Devices, Inc. Field implant for semiconductor device
US6008098A (en) 1996-10-04 1999-12-28 Advanced Micro Devices, Inc. Ultra shallow junction formation using amorphous silicon layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8223918B2 (en) 2006-11-21 2012-07-17 Varian Medical Systems, Inc. Radiation scanning and disabling of hazardous targets in containers
US9103925B2 (en) 2006-11-21 2015-08-11 Varian Medical Systems, Inc. Radiation scanning and disabling of hazardous targets in containers

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