JP7456042B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

2. Description of the Related Art A technique for constructing a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is an integrated circuit (
It is widely applied to electronic devices such as IC) and image display devices (display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) as an active layer of the transistor has been disclosed (see Patent Document 1).

Japanese Patent Application Publication No. 2006-165528

When the on-characteristics (for example, on-state current and field-effect mobility) of a transistor are improved, a semiconductor device can respond quickly to an input signal and drive at high speed, making it possible to realize a semiconductor device with higher performance. On the other hand, in order to reduce the power consumption of a semiconductor device, it is required that the off-state current of a transistor be sufficiently low. As described above, the electrical characteristics required of a transistor vary depending on the use and purpose, and it is beneficial to control the electrical characteristics with more precision.

One of the subjects to be solved is a transistor structure and a method for manufacturing the same, which can achieve a so-called normally-off switching element by making the threshold voltage of the electrical characteristics of a transistor using an oxide semiconductor in the channel formation region positive.

It is desirable that the channel of the transistor be formed with a gate voltage as close to 0V as possible, a positive threshold voltage. If the threshold voltage value of the transistor is negative, even if the gate voltage is 0V, a current flows between the source electrode and the drain electrode, which is likely to cause a so-called normally-on state. In LSIs, CPUs, and memories, the electrical characteristics of transistors forming the circuit are important, and these electrical characteristics influence the power consumption of the semiconductor device. In particular, among the electrical characteristics of a transistor, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is negative, it is difficult to control it as a circuit. A transistor in which a channel is formed and a drain current flows even under a negative voltage state is not suitable as a transistor for use in an integrated circuit of a semiconductor device.

In addition, even if the fabricated transistor does not become normally-off depending on the material and manufacturing conditions, it is important to make it close to normally-off characteristics, and the so-called normal-off transistor with a negative threshold voltage value is important. One of the challenges is to provide a structure and a method for manufacturing the same that can bring the threshold voltage of a transistor close to zero even if it is a marion.

In addition, in order to realize higher-performance semiconductor devices, we are developing structures and fabrication methods that improve the on-characteristics (for example, on-current and field-effect mobility) of transistors to achieve high-speed response and high-speed driving of semiconductor devices. One of the challenges is to provide such information.

As described above, one object of the present invention is to provide a transistor using an oxide semiconductor layer that has electrical characteristics required depending on the intended use, and a semiconductor device including the transistor.

The object is to solve at least one of the above problems.

In a transistor with a bottom gate structure in which at least a gate electrode layer, a gate insulating film, and a semiconductor layer are laminated in this order, at least two semiconductor layers having different energy gaps may be used.
An oxide semiconductor stack including two oxide semiconductor layers is used.

When the oxide semiconductor stack has a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer, the first oxide semiconductor layer and the second oxide semiconductor layer each have an energy gap of The stacking order is not limited as long as they are different, and the layer in contact with the gate insulating film may be a layer with a larger energy gap or a layer with a smaller energy gap.

Specifically, in the oxide semiconductor stack, one oxide semiconductor layer has an energy gap of 3 eV or more, and the other oxide semiconductor layer has an energy gap of less than 3 eV. In addition, in this specification, the term "energy gap" refers to "band gap" or "
It is used interchangeably with "forbidden band width."

When the oxide semiconductor stack has a stacked structure of three or more layers, all the oxide semiconductor layers may have different energy gaps, or multiple oxide semiconductor layers may have substantially the same energy gaps. It may also be used during semiconductor stacking.

For example, when the oxide semiconductor stack has a stacked structure of a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer, the energy gap of the second oxide semiconductor layer is
The energy gap is made smaller than the energy gap between the oxide semiconductor layer and the third oxide semiconductor layer. Alternatively, the electron affinity of the second oxide semiconductor layer is made larger than the electron affinity of the first oxide semiconductor layer and the third oxide semiconductor layer. In this case, the first oxide semiconductor layer and the third oxide semiconductor layer can have the same energy gap and electron affinity. By forming a structure in which the second oxide semiconductor layer with a small energy gap is sandwiched between the first oxide semiconductor layer and the third oxide semiconductor layer with a large energy gap, the off-state current (leakage current) of the transistor can be further reduced. The effect of reducing this can be obtained. Here, the electron affinity represents the energy difference between the vacuum level and the conduction band of the oxide semiconductor.

In a transistor using an oxide semiconductor layer, the energy gap of the oxide semiconductor layer affects the electrical characteristics of the transistor. For example, in a transistor using an oxide semiconductor layer, when the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, on-state current and field effect mobility) are improved; If it is large, the off-state current can be reduced.

In the case of a single-layer oxide semiconductor layer, the electrical characteristics of the transistor are almost determined by the size of the energy gap of the oxide semiconductor layer, so it is difficult to impart desired electrical characteristics to the transistor.

By using an oxide semiconductor stack that includes multiple oxide semiconductor layers with different energy gaps, it is possible to control the electrical characteristics of a transistor with more precision, and it is possible to impart desired electrical characteristics to the transistor. Become.

Therefore, it is possible to provide semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption.

One embodiment of the structure of the invention disclosed in this specification includes a gate insulating film over the gate electrode layer, a first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps over the gate insulating film overlapping the gate electrode layer. This semiconductor device includes an oxide semiconductor stack including a semiconductor layer, and a source electrode layer and a drain electrode layer on the oxide semiconductor stack.

One embodiment of the structure of the invention disclosed in this specification includes a gate insulating film over the gate electrode layer, a first oxide semiconductor layer, a second oxide semiconductor layer over the gate insulating film overlapping with the gate electrode layer, and third
an oxide semiconductor stack including, in order, oxide semiconductor layers, and a source electrode layer and a drain electrode layer on the oxide semiconductor stack, and the second oxide semiconductor layer includes the first oxide semiconductor layer and the drain electrode layer. This is a semiconductor device having an energy gap smaller than that of the oxide semiconductor layer No. 3.

One embodiment of the structure of the invention disclosed in this specification includes a gate insulating film on a gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating film, and a gate insulating film, a source electrode layer, and a drain electrode layer. The semiconductor device includes an oxide semiconductor stack layer overlapping a gate electrode layer and including a first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps.

One embodiment of the structure of the invention disclosed in this specification includes a gate insulating film on a gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating film, a gate insulating film overlapping with the gate electrode layer, and a source electrode layer. , and an oxide semiconductor stack including, in order, a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer on the drain electrode layer, and a second oxide semiconductor layer. teeth,
The semiconductor device has an energy gap smaller than an energy gap between the first oxide semiconductor layer and the third oxide semiconductor layer.

In the oxide semiconductor stack, the upper oxide semiconductor layer may cover the top and side surfaces of the lower oxide semiconductor layer. For example, in the above structure, the second oxide semiconductor layer
a structure that covers the top surface and side surfaces of the oxide semiconductor layer, or a third oxide semiconductor layer that covers the top surface of the second oxide semiconductor layer and the second oxide semiconductor layer (or the first oxide semiconductor layer and The structure can be such that the side surface of the second oxide semiconductor layer (second oxide semiconductor layer) is covered.

Further, in the oxide semiconductor stack, a region that does not overlap with the source electrode layer or the drain electrode layer may have a higher oxygen concentration than a region that overlaps with the source electrode layer or the drain electrode layer.

Further, in the oxide semiconductor stack, a region that does not overlap with the gate electrode layer may contain a dopant and may have a low resistance region.

In one embodiment of the structure of the invention disclosed in this specification, a gate insulating film is formed over the gate electrode layer, and a first oxide semiconductor layer and a second oxide semiconductor layer having different energy gaps are formed on the gate insulating film overlapping with the gate electrode layer. This is a method for manufacturing a semiconductor device, in which an oxide semiconductor stack including oxide semiconductor layers is formed, and a source electrode layer and a drain electrode layer are formed on the oxide semiconductor stack.

In one embodiment of the structure of the invention disclosed in this specification, a gate insulating film is formed over the gate electrode layer, a first oxide semiconductor layer is formed over the gate insulating film overlapping with the gate electrode layer, and a first oxide semiconductor layer is formed over the gate insulating film overlapping the gate electrode layer. A second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer is formed on the oxide semiconductor layer, and a third oxide semiconductor layer has a larger energy gap than the second oxide semiconductor layer. This is a method for manufacturing a semiconductor device in which an oxide semiconductor stack is formed as a film, and a source electrode layer and a drain electrode layer are formed on the oxide semiconductor stack.

In one embodiment of the structure of the invention disclosed in this specification, a gate insulating film is formed on the gate electrode layer, a source electrode layer and a drain electrode layer are formed on the gate insulating film, and the gate insulating film overlaps with the gate electrode layer. , a method for manufacturing a semiconductor device in which an oxide semiconductor stack including a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps is formed on a source electrode layer and a drain electrode layer.

In one embodiment of the structure of the invention disclosed in this specification, a gate insulating film is formed on the gate electrode layer, a source electrode layer and a drain electrode layer are formed on the gate insulating film, and the gate insulating film overlaps with the gate electrode layer. , a first oxide semiconductor layer is formed on the source electrode layer and the drain electrode layer, and a second oxide semiconductor layer having a smaller energy gap than the first oxide semiconductor layer is formed on the first oxide semiconductor layer. This is a method for manufacturing a semiconductor device in which a third oxide semiconductor layer having a larger energy gap than a second oxide semiconductor layer is formed to form an oxide semiconductor stack.

Alternatively, a dopant may be selectively introduced into the oxide semiconductor stack to form a low resistance region containing the dopant and having a lower resistance than the channel formation region across the channel formation region in the oxide semiconductor stack. A dopant is an impurity that changes the conductivity of the oxide semiconductor stack.
As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used.

By having an oxide semiconductor stack including low resistance regions sandwiching a channel formation region in the channel length direction, the transistor has high on characteristics (for example, on current and field effect mobility), and is capable of high-speed operation and high-speed response. becomes.

Alternatively, heat treatment (dehydration or dehydrogenation treatment) may be performed to release hydrogen or water from the oxide semiconductor layer. The dehydration or dehydrogenation treatment can also serve as the heat treatment that forms the mixed region. Further, when a crystalline oxide semiconductor layer is used as the oxide semiconductor layer, heat treatment for forming a mixed region can also serve as heat treatment for crystallization.

Further, due to the dehydration or dehydrogenation treatment, there is a possibility that oxygen, which is the main component material constituting the oxide semiconductor, is simultaneously desorbed and reduced. In the oxide semiconductor film, oxygen vacancies exist at locations where oxygen is released, and the oxygen vacancies generate donor levels that cause changes in the electrical characteristics of the transistor.

Therefore, it is preferable to supply oxygen to the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor layer, oxygen vacancies in the film can be compensated for.

For example, by providing an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, in contact with an oxide semiconductor layer, oxygen can be supplied from the oxide insulating film to the oxide semiconductor layer. . In the above structure, oxygen is supplied to the oxide semiconductor layer by performing heat treatment with the oxide semiconductor layer and the oxide insulating film, which have been heat treated as dehydration or dehydrogenation treatment, at least partially in contact with each other. You may do so.

Alternatively, oxygen (containing at least oxygen radicals, oxygen atoms, or oxygen ions) may be introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. good. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

Furthermore, preferably, the oxide semiconductor layer provided in the transistor includes a region in which the oxygen content is in excess of the stoichiometric composition ratio when the oxide semiconductor is in a crystalline state. In this case, the content of oxygen is set to a level exceeding the content in the stoichiometric composition ratio of the oxide semiconductor. Alternatively, the oxygen content is set to an extent that exceeds the amount of oxygen in the case of a single crystal. Oxygen may exist between the lattices of the oxide semiconductor.

Hydrogen or water is removed from the oxide semiconductor to make it highly purified so that it contains as few impurities as possible,
By supplying oxygen to compensate for oxygen vacancies, type I (intrinsic) oxide semiconductors or type I (
The oxide semiconductor can be made into an oxide semiconductor that is extremely close to (intrinsic). By doing so, the Fermi level (Ef) of the oxide semiconductor can be brought to the same level as the intrinsic Fermi level (Ei). Therefore, by using the oxide semiconductor layer in a transistor, variations in the threshold voltage Vth of the transistor and shift ΔVth in the threshold voltage caused by oxygen vacancies can be reduced.

One embodiment of the present invention relates to a semiconductor device having a transistor or a circuit including a transistor. For example, the present invention relates to a semiconductor device including a transistor or a circuit including a transistor in which a channel formation region is formed using an oxide semiconductor. For example, LSIs, CPUs, power devices installed in power supply circuits, memories, thyristors,
The present invention relates to electronic equipment equipped with semiconductor integrated circuits including converters, image sensors, etc., electro-optical devices such as liquid crystal display panels, and light-emitting display devices having light-emitting elements as components.

By using an oxide semiconductor stack that includes multiple oxide semiconductor layers with different energy gaps, it is possible to control the electrical characteristics of a transistor with more precision, and it is possible to impart desired electrical characteristics to the transistor. Become.

Therefore, it is possible to provide semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption.

FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device and a method for manufacturing the semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device and a method for manufacturing the semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device and a method for manufacturing the semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. FIG. 1 is a diagram illustrating one form of a semiconductor device. A diagram showing an electronic device. 1 is a TEM photograph of the sample in Example 1 and its schematic diagram. 1 is a TEM photograph of the sample in Example 1 and its schematic diagram. A diagram showing ionization potential. A diagram showing an energy band diagram. A diagram showing ionization potential. A diagram showing an energy band diagram. FIG. 3 is a diagram showing off-state current values of transistors. FIG. 3 is a diagram showing field effect mobility of a transistor. FIG. 3 is a diagram showing off-state current values of transistors. FIG. 3 is a diagram showing field effect mobility of a transistor.

Below, embodiments of the invention disclosed in this specification will be described in detail using the drawings.
However, those skilled in the art will easily understand that the invention disclosed in this specification is not limited to the following description, and that its form and details can be changed in various ways. Further, the invention disclosed in this specification is not to be interpreted as being limited to the contents described in the embodiments shown below. Note that the ordinal numbers added as first and second are used for convenience and do not indicate the order of steps or the order of lamination. Furthermore, this specification does not indicate a specific name as a matter for specifying the invention.

(Embodiment 1)
In this embodiment, one embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 3. In this embodiment, a transistor including an oxide semiconductor film is shown as an example of a semiconductor device.

The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type may be used in which two gate electrode layers are placed above and below the channel forming region with a gate insulating film interposed therebetween.

A transistor 440a and a transistor 440b illustrated in FIGS. 1A and 1B are examples of inverted staggered transistors having a bottom gate structure.

As shown in FIGS. 1A and 1B, a transistor 440a and a transistor 440b include a gate electrode layer 401 and a gate insulating film 402, which are provided in this order over a substrate 400 having an insulating surface.
, a first oxide semiconductor layer 101 and a second oxide semiconductor layer 1 with different energy gaps.
02, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 407 is formed over the transistor 440a and the transistor 440b.

Note that in FIG. 1, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is illustrated by a dotted line, which schematically shows the oxide semiconductor stack 403. .
Depending on the material, film formation conditions, and heat treatment, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may become unclear. In cases where it is unclear, a portion that can be called a mixed region or mixed layer of a plurality of different oxide semiconductor layers may be formed. This also applies to other drawings in this specification.

For example, a mixed region 1 is formed between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102.
A transistor 449 having a voltage of 0.05 is shown in FIG. 3C.

In the oxide semiconductor stack 403 of the transistor 449, the interface between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 is unclear; A mixed region 105 is present between the layers 102 . Note that the interface is unclear.
For example, cross-sectional observation of the oxide semiconductor stack 403 using a high-resolution transmission electron microscope (TEM image)
Refers to a case where a clear and continuous linear interface cannot be observed between stacked oxide semiconductor layers.

The mixed region 105 includes the first oxide semiconductor layer 101 and the second oxide semiconductor layer 10 stacked together.
The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different compositions of at least the constituent elements. For example, when the oxide semiconductor stack 403 has a stacked structure of a first oxide semiconductor layer containing indium, tin, and zinc and a second oxide semiconductor layer containing indium, gallium, and zinc, the first oxide semiconductor layer 403 A mixed region 105 containing indium, tin, gallium, and zinc can be formed between the oxide semiconductor layer and the second oxide semiconductor layer. In addition, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 contain the same element but have a different composition (composition ratio) in the mixed region 105.
can be formed. Therefore, the energy gap of the mixed region 105 is also the same as that of the first
The energy gap of the mixed region 105 is different from the energy gap of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 . The value is between the energy gap of .

Therefore, by providing the mixed region 105, the oxide semiconductor stack 403 becomes a continuous junction in the energy band diagram, and scattering at the interface between the stacked first oxide semiconductor layer 101 and second oxide semiconductor layer 102 is suppressed. be able to. Since interface scattering can be suppressed, a transistor 449 using an oxide semiconductor stack 403 provided with a mixed region 105
can improve field effect mobility.

By providing the mixed region 105, in the energy band diagram, the first oxide semiconductor layer 10
A gradient can be formed between the oxide semiconductor layer 1 and the second oxide semiconductor layer 102. The slope may be stepped.

Note that the first oxide semiconductor layer 101, the mixed region 105, and the second oxide semiconductor layer 102
The interface is shown by a dotted line, but this is because the interface is unclear in the oxide semiconductor stack 403 (
This diagram schematically shows that

The mixed region 105 can be formed by performing heat treatment on the oxide semiconductor stack 403 including a plurality of oxide semiconductor layers. The heat treatment is performed at a temperature that allows elements in the oxide semiconductor layers to be stacked to diffuse through heat, and under conditions that the oxide semiconductor layers to be stacked do not form a mixed region with a uniform composition (composition ratio) in the entire oxide semiconductor stack area. Do it with

In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 only need to have different energy gaps, and the stacking order thereof is not limited.

Specifically, in the oxide semiconductor stack 403, one oxide semiconductor layer has an energy gap of 3 eV or more, and the other oxide semiconductor layer has an energy gap of less than 3 eV.

In the transistor 440a illustrated in FIG. 1A, the energy gap is larger in the second oxide semiconductor layer 102 than in the first oxide semiconductor layer 101. In this embodiment,
In the transistor 440a, an In-Sn-Zn-based oxide film (energy gap of 2.6 eV to 2.9 eV, typically 2.8 eV) is used as the first oxide semiconductor layer 101, and an In-Sn-Zn-based oxide film is used as the second oxide semiconductor layer 102. is an In-Ga-Zn-based oxide film (energy gap 3.0
eV to 3.4 eV, typically 3.2 eV).

On the other hand, in the transistor 440b illustrated in FIG. 1B, the second oxide semiconductor layer 101 is
The oxide semiconductor layer 102 is an example in which the energy gap is smaller. In this embodiment, In-Ga-Z is used as the first oxide semiconductor layer 101 in the transistor 440b.
An In-Sn-Zn-based oxide film (energy gap of 2.8 eV) is used as the n-based oxide film (energy gap of 3.2 eV) and the second oxide semiconductor layer 102.

In this way, in the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 may have a layer with a larger energy gap in contact with the gate insulating film 402, or a layer with a larger energy gap. may be a small layer.

FIG. 4A shows a transistor 480 in which the oxide semiconductor stack 403 has a three-layer structure of a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103. shows.

The transistor 480 includes a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101, and a second oxide semiconductor layer 10, which are provided in this order over a substrate 400 having an insulating surface.
oxide semiconductor stack 403 including the second and third oxide semiconductor layers 103 and the source electrode layer 40
5a and a drain electrode layer 405b. An insulating film 407 is formed over the transistor 480.

In the oxide semiconductor stack 403 of the transistor 480, the first oxide semiconductor layer 101,
The energy gaps of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are not all the same, and include energy gaps of at least two different values.

When the oxide semiconductor stack 403 has a stacked structure of three or more layers, all the oxide semiconductor layers may have a different energy gap, or a plurality of oxide semiconductor layers having approximately the same energy gap may be oxidized. It may also be used in the physical semiconductor stack 403.

Further, as another form of a semiconductor device, a transistor 410 is shown in FIG. The transistor 410 has a bottom gate structure called a channel protection type (also called a channel stop type), and is also called an inverted staggered transistor.

As shown in FIG. 9A, the transistor 410 includes a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101 having a different energy gap, and a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101 having a different energy gap, and a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101 having a different energy gap, and Oxide semiconductor stack 40 including second oxide semiconductor layer 102
3. It has an insulating film 427, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 409 is formed over the transistor 410.

The insulating film 427 is provided on the oxide semiconductor stack 403 overlapping with the gate electrode layer 401, and functions as a channel protective film.

The insulating film 427 may be formed using a material and method similar to that of the insulating film 407, and typically, a single layer or a stack of inorganic insulating films such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a hafnium oxide film, a gallium oxide film, a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum nitride oxide film, or an aluminum oxide film can be used.

The insulating film 427 in contact with the oxide semiconductor stack 403 (if the insulating film 427 has a stacked structure,
When the film in contact with the oxide semiconductor stack 403 contains a large amount of oxygen, it can suitably function as a source for supplying oxygen to the oxide semiconductor stack 403.

Note that the insulating film 409 can be formed using the same material and method as the insulating film 407.

Further, as another form of the semiconductor device, a transistor 4 having a bottom gate structure is shown in FIG. 10(A).
30 is shown.

As shown in FIG. 10A, the transistor 430 includes a gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, a drain electrode layer 405b, which are provided in this order over a substrate 400 having an insulating surface, and have different energy gaps. An oxide semiconductor stack 403 including a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102 is included. An insulating film 407 is formed over the transistor 430.

The transistor 430 has a structure in which an oxide semiconductor stack 403 including a first oxide semiconductor layer 101 and a second oxide semiconductor layer 102 with different energy gaps is provided over a source electrode layer 405a and a drain electrode layer 405b.

Oxide semiconductor stack 403 (first oxide semiconductor layer 101, second oxide semiconductor layer 102,
The oxide semiconductor used for the third oxide semiconductor layer 103) includes at least indium (
In) or zinc (Zn) is preferably included. In particular, it is preferable to contain In and Zn. Further, it is preferable to include gallium (Ga) in addition to these as a stabilizer for reducing variations in electrical characteristics of a transistor using the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. In addition, aluminum (A
It is preferable to have l). Moreover, it is preferable to have zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanoids such as lanthanum (La) and cerium (
Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium ( Tm), ytterbium (Yb), and lutetium (Lu).

For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, and Zn-Mg oxide. oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides that are ternary metal oxides, In-Al-Zn-based oxides , In-Sn-Zn
oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In -Ce-Zn based oxide, In-Pr-Zn based oxide, In-Nd-Zn based oxide, In-Sm-Zn based oxide, In-Eu-Zn based oxide, In-Gd-Zn based oxide oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide,
In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide which is a quaternary metal oxide, In-Hf -Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn
-Hf-Zn based oxide and In-Hf-Al-Zn based oxide can be used.

Note that, for example, an In-Ga-Zn-based oxide herein means an oxide containing In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter. Also, In and G
Metal elements other than a and Zn may also be contained.

In addition, as an oxide semiconductor, InMO ₃ (ZnO) _m (m>0 and m is not an integer)
You may also use materials described in . Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co. In addition, as an oxide semiconductor, In ₂ SnO ₅
A material expressed as (ZnO) _n (n>0, and n is an integer) may be used.

For example, In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:G
An In--Ga--Zn based oxide having an atomic ratio of a:Zn=2:2:1 (=2/5:2/5:1/5) or an oxide having a composition close to that can be used. Or In:Sn:Zn=1:
1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/
6:1/2) or In-Sn-Zn oxide with an atomic ratio of In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) or a composition close to that. It is better to use oxides.

However, the material is not limited to these, and a material with an appropriate composition may be used depending on the required semiconductor characteristics (mobility, threshold value, variation, etc.). Further, in order to obtain the required semiconductor characteristics, it is preferable to set the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc. to appropriate values.

For example, high mobility can be obtained relatively easily with In--Sn--Zn based oxides. However, even with In--Ga--Zn based oxides, the mobility can be increased by lowering the defect density in the bulk.

Note that, for example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+
c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+C
=1) is close to the oxide composition by r, which means that a, b, and c are (a-A) ² + (b-B
) ² + (c−C) ² ≦r ² is satisfied. For example, r may be set to 0.05. The same applies to other oxides.

The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. Further, the structure may be amorphous and include a crystalline portion, or may be non-amorphous.

Oxide semiconductors in an amorphous state can have a flat surface relatively easily, so
When a transistor is manufactured using this, interface scattering can be reduced, and relatively high mobility can be obtained relatively easily.

In addition, in an oxide semiconductor having crystallinity, defects in the bulk can be further reduced, and if the surface flatness is improved, mobility higher than that of an amorphous oxide semiconductor can be obtained.
In order to improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface, and specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably is preferably formed on the surface with a thickness of 0.1 nm or less.

Note that Ra is a three-dimensional extension of the arithmetic mean roughness defined in JIS B0601:2001 (ISO4287:1997) so that it can be applied to curved surfaces. It can be expressed as a value that is the average of absolute values, and is defined by the following formula.

Here, the designated surface is the surface to be measured for roughness, and the coordinates ((x ₁ , y ₁ , f(x ₁ ,
y ₁ )), (x ₁ , y ₂ , f(x ₁ , y ₂ )), (x ₂ , y ₁ , f(x ₂ , y ₁ )), (
Let the area of the rectangle represented by the four points x _{2 ,} y _{2 , f (x 2} , y ₂ )) be S ₀ and the average height of the designated surface Z Set to ₀ . Ra can be measured with an atomic force microscope (AFM).

Oxide semiconductor stack 403 (first oxide semiconductor layer 101, second oxide semiconductor layer 102,
As the third oxide semiconductor layer 103), an oxide semiconductor layer containing crystal and having crystallinity (crystalline oxide semiconductor layer) can be used. The crystalline state of the crystalline oxide semiconductor layer may be a state in which the directions of crystal axes are disordered or a state in which the crystal axes have a certain orientation.

For example, as the crystalline oxide semiconductor layer, an oxide semiconductor layer including a crystal having a c-axis substantially perpendicular to the surface can be used.

An oxide semiconductor layer containing a crystal having a c-axis approximately perpendicular to the surface does not have a single crystal structure,
It has a structure that is not an amorphous structure, and is a crystalline oxide semiconductor with c-axis orientation (C Axis
Aligned Crystalline Oxide Semiconductor;
It is also called CAAC-OS) membrane.

The CAAC-OS film is neither completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure in which an amorphous phase includes a crystalline portion and an amorphous portion. Note that the crystal part is often sized to fit within a cube with one side of less than 100 nm. In addition, a transmission electron microscope (TEM)
In an image observed using a microscope (n Microscope), the boundary between the amorphous portion and the crystalline portion included in the CAAC-OS film is not clear. Further, grain boundaries (also referred to as grain boundaries) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility caused by grain boundaries is suppressed.

The crystal parts included in the CAAC-OS film have a c-axis aligned in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or a normal vector to the surface, and have a triangular shape when viewed from the direction perpendicular to the a-b plane. It has a hexagonal atomic arrangement, and metal atoms are arranged in a layer or metal atoms and oxygen atoms are arranged in a layer when viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, when simply described as vertical, 8
The range of 5° or more and 95° or less is also included. Also, when simply stating parallel, -5
The range of 5 degrees or more is also included.

Note that in the CAAC-OS film, the distribution of crystal parts does not have to be uniform. For example, CAA
In the process of forming a C-OS film, when crystals are grown from the surface side of the oxide semiconductor film, the proportion of crystal parts near the surface may be higher than near the surface on which the film is formed. Also, CA
By adding impurities to the AC-OS film, the crystalline portions may become amorphous in the impurity-added region.

The c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface. They may face different directions depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface. Note that the direction of the c-axis of the crystal part is parallel to the normal vector of the surface on which the CAAC-OS film is formed or the normal vector of the surface. The crystal portion is formed by forming a film or by performing a crystallization process such as heat treatment after forming a film.

A transistor using a CAAC-OS film can reduce fluctuations in electrical characteristics caused by irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

There are three methods for obtaining a crystalline oxide semiconductor layer with c-axis orientation. The first method is to form an oxide semiconductor layer at a film formation temperature of 200° C. or more and 500° C. or less, and align the c-axis approximately perpendicular to the surface. Second, after forming a thin film, the temperature is
This is a method of performing a heat treatment at 0° C. or lower to align the c-axis approximately perpendicular to the surface. The third method is to form a thin first layer, then perform heat treatment at 200°C or more and 700°C or less, form a second layer, and align the c-axis approximately perpendicular to the surface. .

First oxide semiconductor layer 101, second oxide semiconductor layer 102, third oxide semiconductor layer 10
The film thickness of No. 3 is 1 nm or more and 10 nm or less (preferably 5 nm or more and 30 nm or less), and a sputtering method, MBE (Molecular Beam Epitaxy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition) method, etc. is used as appropriate. be able to. Further, the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 are formed with the surfaces of the plurality of substrates set approximately perpendicular to the surface of the sputtering target. A film may be formed using a sputtering device that performs film formation.

In a transistor using an oxide semiconductor layer, the energy gap of the oxide semiconductor layer affects the electrical characteristics of the transistor. For example, in a transistor using an oxide semiconductor layer, when the energy gap of the oxide semiconductor layer is small, the on-characteristics (for example, on-state current and field effect mobility) are improved; If it is large, the off-state current can be reduced.

Oxide semiconductor stack 40 using multiple oxide semiconductor layers having different energy gaps
By using transistor 4, the electrical characteristics of transistor 440a, transistor 440b, and transistor 480 can be controlled more precisely, and desired electrical characteristics can be controlled by transistor 4.
40a, transistor 440b, and transistor 480.

For example, in the oxide semiconductor stack 403 of the transistor 480 illustrated in FIG.
The energy gap of the oxide semiconductor layer 102 is made smaller than the energy gap of the first oxide semiconductor layer 101 and the third oxide semiconductor layer 103. In this case, the first oxide semiconductor layer 101 and the third oxide semiconductor layer 103 can have almost the same energy gap.

FIG. 4(C) shows an energy band diagram in the film thickness direction (between E1 and E2) in FIG. 4(A). In the transistor 480, the first
oxide semiconductor layer 101, second oxide semiconductor layer 102, and third oxide semiconductor layer 10
It is preferable to select material No. 3. However, since a sufficient effect can be obtained if a buried channel is formed in the conduction band, it is not necessarily necessary to limit the energy band diagram to an energy band diagram having concavities in both the conduction band and the valence band as shown in FIG. 4(C). For example, a configuration may be adopted in which an energy band diagram having recesses only in the conduction band can be obtained.

For example, as the first oxide semiconductor layer 101 in the transistor 480, In-Ga-Z
An n-based oxide film (energy gap 3.2 eV), an In-Sn-Zn-based oxide film (energy gap 2.8 eV) as the second oxide semiconductor layer 102, and an In-Sn-Zn oxide film (energy gap 2.8 eV) as the third oxide semiconductor layer 103. - A Ga-Zn based oxide film (energy gap 3.2 eV) is used.

Further, as the oxide semiconductor stack 403 of three layers like the transistor 480,
The first oxide semiconductor layer 101 is an In-Ga-Zn-based oxide film, the second oxide semiconductor layer 102 is an In-Zn-based oxide film, and the third oxide semiconductor layer 103 is an In-Ga-Zn-based oxide film.
A stack of Zn-based oxide films, a Ga--Zn-based oxide film as the first oxide semiconductor layer 101, a second
The oxide semiconductor layer 102 is an In-Sn-Zn-based oxide film, the third oxide semiconductor layer 1
03 is a stack of Ga--Zn based oxide films, and the first oxide semiconductor layer 101 is a Ga--Zn layer.
oxide film, an In--Zn-based oxide film as the second oxide semiconductor layer 102, a stack of a Ga--Zn-based oxide film as the third oxide semiconductor layer 103, and the first oxide semiconductor layer 101. The second oxide semiconductor layer 102 is an In-Ga-Zn oxide film, the third oxide semiconductor layer 103 is an In-Ga-based oxide film, or the third oxide semiconductor layer 103 is an In-Ga-based oxide film. The first oxide semiconductor layer 101 is an In-Ga-Zn based oxide film, the second oxide semiconductor layer 102 is an indium oxide (In-based oxide) film, and the third oxide semiconductor layer 103 is an In-Ga-Zn based oxide film. -
A stack of Zn-based oxide films or the like can be used.

By forming a structure in which the second oxide semiconductor layer 102 with a small energy gap is sandwiched between the first oxide semiconductor layer 101 and the third oxide semiconductor layer 103 with a large energy gap, the off-state current ( This has the effect of reducing leakage current).

FIGS. 2A to 2E illustrate an example of a manufacturing method using a transistor 440a.

First, a conductive film is formed on a substrate 400 having an insulating surface, and then a gate electrode layer 401 is formed by a first photolithography process. Note that the resist mask may be formed by an inkjet method. When a resist mask is formed by an inkjet method, a photomask is not used, so manufacturing costs can be reduced.

Although there are no major restrictions on the substrate that can be used as the substrate 400 having an insulating surface, it is necessary that the substrate has at least enough heat resistance to withstand subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and alumino borosilicate glass, ceramic substrates,
A quartz substrate, a sapphire substrate, etc. can be used. In addition, single crystal semiconductor substrates such as silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can also be applied, and semiconductor elements are provided on these substrates. It may also be used as the substrate 400.

Further, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. To manufacture a flexible semiconductor device, the transistor 440a including the oxide semiconductor stack 403 may be directly fabricated on a flexible substrate, or the transistor 440a including the oxide semiconductor stack 403 may be fabricated on another manufacturing substrate. 440a may be produced and then peeled off and transferred to a flexible substrate. Note that in order to peel and transfer from the manufacturing substrate to a flexible substrate, a separation layer is preferably provided between the manufacturing substrate and the transistor 440a including an oxide semiconductor film.

An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. The base film has a function of preventing diffusion of impurity elements from the substrate 400, and has a stacked structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. can be formed. Further, the base film can be formed using aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, or a mixed material thereof. The base film may be formed by a plasma CVD method, a sputtering method, or the like.

Further, the material of the gate electrode layer 401 is prepared by plasma CVD method, sputtering method, etc.
It can be formed in a single layer or in a stacked manner using metal materials such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., or alloy materials containing these as main components. Further, as the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single layer structure or a laminated structure.

Further, the material of the gate electrode layer 401 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive materials such as zinc oxide and indium tin oxide added with silicon oxide can also be applied. Further, a laminated structure of the conductive material described above and the metal material described above may be used.

Further, the gate electrode layer 401 has a laminated structure, and one layer of the gate electrode layer 401 is In-Sn based, In-Sn
-Zn series, In-Al-Zn series, Sn-Ga-Zn series, Al-Ga-Zn series, Sn-Al
- Zn-based, In--Zn-based, Sn--Zn-based, Al--Zn-based, In-based, Sn-based, and Zn-based metal oxides may be used.

Further, as one layer of the gate electrode layer 401 in contact with the gate insulating film 402, a metal oxide containing nitrogen, specifically, an In-Ga-Zn-O film containing nitrogen or an In-Sn-O film containing nitrogen is used. , In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-
An O film, an In--O film containing nitrogen, or a metal nitride film (InN, SnN, etc.) can be used. These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or more, and when used as a gate electrode layer, they can increase the threshold voltage of the electrical characteristics of the transistor. Therefore, a so-called normally-off switching element can be realized.

For example, it is preferable that the gate electrode layer 401 has a stacked structure, and that one layer thereof is an oxynitride film containing indium, gallium, and zinc, which are materials with a particularly large work function. An oxynitride film containing indium, gallium, and zinc is obtained by forming the film in a mixed gas atmosphere of argon and nitrogen.

For example, as the gate electrode layer 401, from the substrate 400 side, a stacked structure of a copper film, a tungsten film, an oxynitride film containing indium, gallium, and zinc, a tungsten film, a tungsten nitride film, a copper film, and a titanium film are stacked. A laminated structure with a film, etc. can be used.

Next, a gate insulating film 402 is formed over the gate electrode layer 401 (see FIG. 2A). The gate insulating film 402 is preferably formed in consideration of the size of the transistor to be manufactured and the step coverage of the gate insulating film 402.

The thickness of the gate insulating film 402 is 1 nm or more and 20 nm or less, and is formed by sputtering, MBE, etc.
method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. Further, the gate insulating film 402 may be formed using a sputtering apparatus that performs film formation in a state where the surfaces of a plurality of substrates are set approximately perpendicular to the surface of a sputtering target.

The gate insulating film 402 can be formed using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film.

In addition, as materials for the gate insulating film 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y x > 0, y > 0)), hafnium silicate added with _nitrogen ( _HfSiO >0)), hafnium aluminate (HfAl _x O _y
(x>0, y>0)), gate leakage current can be reduced by using a high-k material such as lanthanum oxide.

Although the gate insulating film 402 may be a single layer or a stacked layer, an oxide insulating film is preferable as the film in contact with the oxide semiconductor stack 403. In this embodiment, a silicon oxide film is used as the gate insulating film 402.

Further, when the gate insulating film 402 is a stacked layer, for example, a silicon oxide film, an In-Hf-Zn-based oxide film, and an oxide semiconductor stack 403 may be stacked in this order on the gate electrode layer 401, or A silicon oxide film is formed on the layer 401 with an atomic ratio of In:Zr:Zn=1:1:1.
An n-Zr-Zn based oxide film and an oxide semiconductor stack 403 may be stacked in this order, or a silicon oxide film and an In layer with an atomic ratio of In:Gd:Zn=1:1:1 may be stacked on the gate electrode layer 401. -Gd-
The Zn-based oxide film and the oxide semiconductor stack 403 may be stacked in this order.

Next, a first oxide semiconductor film 191 and a second oxide semiconductor film 1 are formed over the gate insulating film 402.
A stacked layer 493 of oxide semiconductor films made of 92 layers is formed (see FIG. 2B).

Since the gate insulating film 402 is in contact with the oxide semiconductor film stack 493 (oxide semiconductor stack 403), it is preferable that at least an amount of oxygen exceeding the stoichiometric ratio exists in the film (in the bulk). For example, when using a silicon oxide film as the gate insulating film 402, SiO
_2+α (however, α>0). By using such a gate insulating film 402, oxygen can be supplied to the oxide semiconductor film stack 493 (oxide semiconductor stack 403), and the characteristics can be improved. By supplying oxygen to the oxide semiconductor film stack 493 (oxide semiconductor stack 403), oxygen vacancies in the film can be compensated for.

For example, by providing the gate insulating film 402 containing a large amount (excessively) of oxygen, which serves as an oxygen supply source, in contact with the oxide semiconductor film stack 493 (oxide semiconductor stack 403), the oxide is removed from the gate insulating film 402. Oxygen can be supplied to the semiconductor film stack 493 (oxide semiconductor stack 403). By performing heat treatment with the oxide semiconductor film stack 493 (oxide semiconductor stack 403) and the gate insulating film 402 at least partially in contact with each other, the oxide semiconductor film stack 493 (oxide semiconductor stack 403) is heated. Oxygen may be supplied.

Layered layer 493 of oxide semiconductor films (first oxide semiconductor film 191 and second oxide semiconductor film 1
92), the oxide semiconductor film stack 493 (first oxide semiconductor film 191
In order to prevent the oxide semiconductor film stack 493 (first oxide semiconductor film 191 and second oxide semiconductor film 192) from containing hydrogen or water as much as possible, 192), the gate insulating film 40 is deposited in the preheating chamber of the sputtering device.
It is preferable to preheat the substrate on which 2 is formed to remove and exhaust impurities such as hydrogen and water adsorbed on the substrate and the gate insulating film 402. Note that the evacuation means provided in the preheating chamber is preferably a cryopump.

Planarization treatment may be performed on a region of the gate insulating film 402 in which the stacked layer 493 of oxide semiconductor films (the stacked oxide semiconductor layer 403) is formed in contact with the stacked layer 493 of the oxide semiconductor film. The planarization process is not particularly limited, but may include a polishing process (for example, chemical mechanical polishing).
1 Polishing (CMP) method), dry etching treatment, and plasma treatment can be used.

As the plasma treatment, for example, reverse sputtering can be performed in which argon gas is introduced to generate plasma. Reverse sputtering refers to RF sputtering on the substrate side under an argon atmosphere.
This is a method of applying voltage using a power source to form plasma near the substrate to modify the surface.
Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. By performing reverse sputtering, powdery substances (also referred to as particles or dust) attached to the surface of the gate insulating film 402 can be removed.

As the planarization treatment, polishing treatment, dry etching treatment, and plasma treatment may be performed multiple times, or they may be performed in combination. Further, when performing the steps in combination, the order of the steps is not particularly limited, and may be set as appropriate depending on the unevenness of the surface of the gate insulating film 402.

Note that the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed under conditions that contain a large amount of oxygen (for example, the films are formed by a sputtering method in an atmosphere containing 100% oxygen). ) to form a film containing a large amount of oxygen (preferably containing a region where the oxygen content is excessive relative to the stoichiometric composition ratio when the oxide semiconductor is in a crystalline state). .

Note that in this embodiment, the target for manufacturing the first oxide semiconductor film 191 by a sputtering method has, for example, a composition ratio of In:Sn:Zn in an atomic ratio of 1:2: An In--Sn--Zn--O film is formed using an oxide target having a ratio of 2, 2:1:3, 1:1:1, or 20:45:35.

Note that in this embodiment, the target for manufacturing the second oxide semiconductor film 192 by a sputtering method has a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :Zn, for example.
An In--Ga--Zn based oxide film is formed using an oxide target with a molar ratio of O=1:1:2. Moreover, the material and composition of this target are not limited, for example, In ₂ O ₃ :G
A metal oxide target with a ₂ O ₃ :ZnO=1:1:1 [molar ratio] may be used.

Further, the filling rate of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a metal oxide target with a high filling rate, the formed oxide semiconductor film can be dense.

The sputtering gas used to form the first oxide semiconductor film 191 and the second oxide semiconductor film 192 can be a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. preferable.

A substrate is held in a film forming chamber maintained at reduced pressure. Then, while removing residual moisture in the film forming chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and the target is used to form a substrate 400.
A stack 493 of oxide semiconductor films (a first oxide semiconductor film 191 and a second oxide semiconductor film 192) is formed thereover. In order to remove residual moisture in the film forming chamber, an adsorption type vacuum pump,
For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump with a cold trap added. For example, the film forming chamber evacuated using a cryopump is filled with hydrogen atoms, water (H
Since compounds containing hydrogen atoms (more preferably compounds containing carbon atoms) such as ₂ O) are exhausted, the oxide semiconductor film stack 493 (first oxide semiconductor film 1
91 and the second oxide semiconductor film 192) can be reduced.

In addition, a stack 493 of the gate insulating film 402 and the oxide semiconductor film (the first oxide semiconductor film 191
It is preferable to successively form the gate insulating film 402 and the stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192) without exposure to the air. When the gate insulating film 402 and the stack of oxide semiconductor films 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192) are formed in succession without exposure to the air, impurities such as hydrogen and water can be prevented from being adsorbed onto a surface of the gate insulating film 402.

The CAAC-OS film is formed by a sputtering method using, for example, a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target cleaves from the a-b plane, resulting in a
- It may be exfoliated as sputtered particles in the form of a flat plate or pellet having a plane parallel to the b plane. In this case, the planar sputtered particles reach the substrate while maintaining their crystalline state, thereby making it possible to form a CAAC-OS film.

Further, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being disrupted by the impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film forming chamber may be reduced. Further, the concentration of impurities in the film forming gas may be reduced. Specifically, a film forming gas having a dew point of -80°C or lower, preferably -100°C or lower is used.

Furthermore, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100° C. or more and 740° C. or less, preferably 200° C. or more and 500° C. or less. By increasing the substrate heating temperature during film formation, when flat sputtered particles reach the substrate, migration occurs on the substrate.
The flat side of the sputtered particles adheres to the substrate.

Further, it is preferable to reduce plasma damage during film formation by increasing the proportion of oxygen in the film formation gas and optimizing the electric power. The proportion of oxygen in the film forming gas is 30% by volume or more, preferably 100% by volume.

As an example of a sputtering target, an In-Ga-Zn-O compound target is shown below.

Polycrystalline In _- G is _obtained by mixing _InO
a-Zn-O compound target. Note that X, Y, and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO _X powder, GaO _Y powder, and ZnO _Z powder,
2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. Note that the type of powder and the molar ratio of the powders to be mixed may be changed as appropriate depending on the sputtering target to be produced.

Layered layer 493 of oxide semiconductor films (first oxide semiconductor film 191 and second oxide semiconductor film 1
92) is processed into an island-shaped oxide semiconductor stack 403 (first oxide semiconductor layer 101 and second oxide semiconductor layer 102) by a photolithography process (see FIG. 2C).

Further, a resist mask for forming the island-shaped oxide semiconductor stack 403 may be formed by an inkjet method. When a resist mask is formed by an inkjet method, a photomask is not used, so manufacturing costs can be reduced.

Note that the oxide semiconductor film may be etched by dry etching or wet etching, or both may be used. For example, as an etching solution used for wet etching the oxide semiconductor film, a solution containing phosphoric acid, acetic acid, and nitric acid can be used. Also, IT
O07N (manufactured by Kanto Kagaku Co., Ltd.) may be used.

In this embodiment, the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed by etching using the same mask; The layer 102 is an oxide semiconductor layer having the same shape with side edges that coincide with each other. In the oxide semiconductor stack 403, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102
The sides (ends) of are exposed.

Note that in one embodiment of the disclosed invention, the oxide semiconductor stack may be processed into an island shape as shown in this embodiment, or may remain in a film shape without being processed.

Further, when forming a contact hole in the gate insulating film 402, this step can be performed simultaneously when the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are processed.

Note that, as in the transistor 449 in FIG. 3C, heat treatment is performed on the oxide semiconductor stack 403 to form a mixed region 10 between the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102.
5 may be formed. The heat treatment is performed at a temperature at which the elements in the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 can be diffused by heat, and This may be performed under conditions that do not result in a mixed region with a uniform composition in the entire region of the oxide semiconductor stack 403.

The heat treatment can be performed under reduced pressure, under a nitrogen atmosphere, under an oxygen atmosphere, under the atmosphere (ultra-dry air), under a rare gas atmosphere, or the like. Further, the heat treatment may be performed multiple times under different conditions (temperature, atmosphere, time, etc.). For example, the heat treatment may be performed at a temperature of 650° C., heated in a nitrogen atmosphere for 1 hour, and then heated in an oxygen atmosphere for 1 hour.

The step of performing heat treatment for forming the mixed region 105 is not particularly limited as long as it is performed after the first oxide semiconductor film 191 and the second oxide semiconductor film 192 are formed. It may be applied to the oxide semiconductor film 191 and the second oxide semiconductor film 192, or it may be applied to the island-shaped first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 as in this embodiment. It's okay. Further, the heat treatment may also serve as another heat treatment (for example, heat treatment for dehydration or dehydrogenation, heat treatment for crystallization, etc.) performed during the manufacturing process of the transistor.

Further, the oxide semiconductor stack 403 (the oxide semiconductor film stack 493) may be subjected to heat treatment to remove excess hydrogen (including water and hydroxyl groups) (dehydration or dehydrogenation). The temperature of the heat treatment is 300° C. or higher and 700° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or under a nitrogen atmosphere. For example, the substrate is introduced into an electric furnace that is one of the heat treatment apparatuses, and the oxide semiconductor stack 403 (oxide semiconductor film stack 493) is heat treated at 450° C. for one hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and may be an apparatus that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, GRTA (Gas R
apid Thermal Anneal) device, LRTA (Lamp Rapid T
RTA (Rapid Thermal Anneal) equipment, etc.
al) equipment can be used. An LRTA device is a device that heats a workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. For hot gas,
A rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated during heat treatment is used.

For example, as the heat treatment, GRTA may be performed by placing the substrate in an inert gas heated to a high temperature of 650° C. to 700° C., heating it for several minutes, and then removing the substrate from the inert gas.

Note that in the heat treatment, it is preferable that water, hydrogen, etc. be not included in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon to be introduced into the heat treatment equipment is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably is 0.1
ppm or less).

In addition, after heating the oxide semiconductor stack 403 (oxide semiconductor film stack 493) by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS) is added to the same furnace.
The moisture content when measured using a dew point meter using a cavity ring-down laser spectroscopy method is 20 ppm or less (-55°C dew point equivalent), preferably 1 ppm or less, more preferably 10 ppm or less.
(ppb or less air) may be introduced. It is preferable that the oxygen gas or dinitrogen monoxide gas does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is set to 6N or higher, preferably 7N or higher (that is, the impurity concentration in the oxygen gas or dinitrogen monoxide gas is set to 1 ppm or lower, preferably 0.1 ppm or lower). ) is preferable. Through the action of oxygen gas or dinitrogen monoxide gas, oxidation can be achieved by supplying oxygen, which is the main component of the oxide semiconductor, which has been simultaneously reduced in the process of removing impurities through dehydration or dehydrogenation. The physical semiconductor stack 403 (the stack 493 of oxide semiconductor films) can be highly purified and made to be I-type (intrinsic).

Note that the heat treatment for dehydration or dehydrogenation is performed after the formation of the stacked oxide semiconductor film 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192), and then the formation of the insulating film 407. As long as it is before, it may be performed at any timing in the manufacturing process of the transistor 440a. For example, after the formation of the oxide semiconductor film stack 493 (the first oxide semiconductor film 191 and the second oxide semiconductor film 192), or after the formation of the island-shaped oxide semiconductor stack 403 (the first oxide semiconductor layer 10
This can be performed after the first and second oxide semiconductor layers 102) are formed.

Further, the heat treatment for dehydration or dehydrogenation may be performed multiple times, or may be combined with other heat treatments. For example, after the first oxide semiconductor film 191 is formed and after the second oxide semiconductor film 19
The heat treatment may be performed twice after the second formation.

Heat treatment for dehydration or dehydrogenation is applied to the oxide semiconductor film before it is processed into an island shape as the oxide semiconductor stack 403 (the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102). When the stacking layer 493 (first oxide semiconductor film 191 and second oxide semiconductor film 192) covers the gate insulating film 402, oxygen contained in the gate insulating film 402 is released by heat treatment. This is preferable because it can prevent this.

Next, over the gate insulating film 402 and the oxide semiconductor stack 403, a conductive film that will become a source electrode layer and a drain electrode layer (including wiring formed of the same layer) is formed. The conductive film is made of a material that can withstand subsequent heat treatment. As the conductive film used for the source electrode layer and the drain electrode layer, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-mentioned elements as a component. A material film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film), etc. can be used. In addition, a high melting point metal film such as Ti, Mo, W, etc. or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) may be formed on one or both of the lower and upper sides of the metal film such as Al and Cu. It is also possible to have a structure in which these are laminated. Further, the conductive film used for the source electrode layer and the drain electrode layer may be formed of a conductive metal oxide. Indium oxide (In ₂ O ₃ ) as a conductive metal oxide
, tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide tin oxide (In ₂ O ₃ -
SnO ₂ ), indium oxide, zinc oxide (In ₂ O ₃ --ZnO), or a metal oxide material containing silicon oxide can be used.

A resist mask is formed on the conductive film by a photolithography process, selectively etched to form a source electrode layer 405a and a drain electrode layer 405b, and then the resist mask is removed.

In the oxide semiconductor stack 403, the side surfaces (ends) of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are exposed, so that the source electrode layer 405a and the drain electrode layer 4
05b is formed so as to be in contact with part of the side surfaces of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102.

In addition, in order to reduce the number of photomasks and steps used in the photolithography process, the etching process may be performed using a resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has multiple intensities. good. A resist mask formed using a multi-tone mask has a shape with multiple film thicknesses, and the shape can be further modified by etching, so it can be used in multiple etching processes to process different patterns. . Therefore, resist masks corresponding to at least two or more different patterns can be formed using one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, making it possible to simplify the process.

Note that during etching of the conductive film, it is desirable to optimize the etching conditions so that the oxide semiconductor stack 403 is not etched and divided. However, it is difficult to obtain a condition in which only the conductive film is etched and the oxide semiconductor stack 403 is not etched at all. When etching the conductive film, only a part of the oxide semiconductor stack 403 is etched, resulting in a groove (concave part). In some cases, the oxide semiconductor stack 403 has the following.

In this embodiment, a Ti film is used as the conductive film, and the oxide semiconductor stack 403 is made of In-Ga.
- Since a Zn-based oxide semiconductor was used, ammonia peroxide (ammonia,
A mixture of water and hydrogen peroxide) is used.

Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 2D).
A plurality of oxide semiconductor layers having different energy gaps (first oxide semiconductor layer 101
By using the oxide semiconductor stack 403 including the second oxide semiconductor layer 102), the electrical characteristics of the transistors 440a and 440b can be controlled with higher accuracy, and desired electrical characteristics can be imparted to the transistors 440a and 440b. It becomes possible to grant.

Next, an insulating film 407 is formed in contact with part of the oxide semiconductor stack 403 (see FIG. 2E).

The insulating film 407 can be formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like. As the insulating film 407, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film can be used.

Further, as the insulating film 407, an aluminum oxide film, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride film (for example, an aluminum nitride film) can also be used.

The insulating film 407 may be a single layer or a laminated layer, and for example, a laminated layer of a silicon oxide film and an aluminum oxide film can be used.

An aluminum oxide film that can be used as the insulating film 407 provided over the oxide semiconductor stack 403 has a high blocking effect of preventing both impurities such as hydrogen and water from passing through the film, as well as oxygen.

Therefore, during and after the fabrication process, the aluminum oxide film is exposed to hydrogen and
It functions as a protective film that prevents impurities such as water from entering the oxide semiconductor stack 403 and prevents oxygen, which is a main component of the oxide semiconductor, from being released from the oxide semiconductor stack 403.

The insulating film 407 is preferably formed using an appropriate method such as a sputtering method that prevents impurities such as water and hydrogen from being mixed into the insulating film 407. Further, in the insulating film 407, if the insulating film in contact with the oxide semiconductor stack 403 is a film containing excess oxygen, the oxide semiconductor stack 403
This is preferable because it serves as a source of oxygen to 3.

In this embodiment, a silicon oxide film with a thickness of 100 nm is formed as the insulating film 407 using a sputtering method. The silicon oxide film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of rare gas and oxygen.

Further, when the insulating film 407 is formed into a stacked layer, for example, In--Hf
- A Zn-based oxide film and a silicon oxide film may be stacked in this order, or an In-Zr-Zn-based oxide film with an atomic ratio of In:Zr:Zn=1:1:1 may be stacked on the oxide semiconductor stack 403. , silicon oxide films may be stacked in order, or In:Gd:Zn=1:1:1 may be stacked on the oxide semiconductor stack 403.
An In--Gd--Zn-based oxide film and a silicon oxide film having an atomic ratio of 100% may be laminated in this order.

As in the case of forming the oxide semiconductor film, in order to remove residual moisture in the film formation chamber for the insulating film 407, it is preferable to use an adsorption-type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating film 407 formed in a film forming chamber evacuated using a cryopump can be reduced. Further, as an exhaust means for removing residual moisture in the film forming chamber of the insulating film 407, a turbo molecular pump with a cold trap added thereto may be used.

As the sputtering gas used to form the insulating film 407, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed.

Further, as shown in FIGS. 3A and 3B, a planarizing insulating film 416 may be formed as an interlayer insulating film over the transistors 440c and 440d in order to reduce surface unevenness caused by the transistors. As the planarization insulating film 416, an organic material such as polyimide, acrylic resin, benzocyclobutene resin, or the like can be used. In addition to the above organic materials, low dielectric constant materials (l
OW-K material), etc. can be used. Note that the planarization insulating film 416 may be formed by stacking a plurality of insulating films made of these materials.

Further, openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating film 407 and the planarizing insulating film 416, and the source electrode layer 405a and the drain electrode layer 405b are formed in the openings.
A wiring layer may be formed to be electrically connected to. Various circuits can be configured by connecting it to other transistors using a wiring layer.

The source electrode layer 405a and the drain electrode layer 405b may be partially over-etched and removed during the etching process when forming openings that reach the source electrode layer 405a and the drain electrode layer 405b. The source electrode layer and the drain electrode layer can have a laminated structure, and a conductive film that also functions as an etching stopper during opening formation can be provided as the source electrode layer and the drain electrode layer.

As shown in FIG. 3A, the transistor 440c is an example in which a source electrode layer and a drain electrode layer have a stacked structure, and the source electrode layer 404a and the source electrode layer 40 serve as the source electrode layer.
5a, a drain electrode layer 404b and a drain electrode layer 405b are laminated as drain electrode layers. Like the transistor 440c, openings reaching the source electrode layer 404a and drain electrode layer 404b are formed in the planarizing insulating film 416, the insulating film 407, the source electrode layer 405a, and the drain electrode layer 405b, and the source electrode layer 404a and the drain electrode layer 404b are formed in the opening. Drain electrode layer 404
A wiring layer 465a and a wiring layer 465b electrically connected to the wiring layer 465b may be formed.

In the transistor 440c, the source electrode layer 404a and the drain electrode layer 404b also function as an etching stopper when forming an opening. The source electrode layer 404a and the drain electrode layer 404b are made of a tungsten film, a tantalum nitride film, etc.
, a copper film, an aluminum film, or the like can be used as the drain electrode layer 405b.

Alternatively, as shown in a transistor 440d in FIG. 3B, the source electrode layer 405a and the drain electrode layer 405b may be provided only over the oxide semiconductor stack 403 and not in contact with the side surfaces of the oxide semiconductor stack 403. The structure shown by the transistor 440d can also be manufactured by performing an etching process using a resist mask formed by a multi-tone mask. With this structure, leakage current (parasitic channel) of the source electrode layer 405a and drain electrode layer 405b of the transistor 440d can be further reduced.

The wiring layer 465a and the wiring layer 465b can be formed using the same material and method as the gate electrode layer 401, the source electrode layer 405a, and the drain electrode layer 405b. For example, a stack of a tantalum nitride film and a copper film, a stack of a tantalum nitride film and a tungsten film, or the like can be used as the wiring layer 465a and the wiring layer 465b.

In the oxide semiconductor stack 403 that has been highly purified and has oxygen vacancies filled, impurities such as hydrogen and water have been sufficiently removed, and the hydrogen concentration in the oxide semiconductor stack 403 is 5×10 ¹⁹ atoms.
s/cm ³ or less, preferably 5×10 ¹⁸ atoms/cm ³ or less. Note that the hydrogen concentration in the oxide semiconductor stack 403 is determined by secondary ion mass spectrometry (SIMS).
y ion mass spectrometry).

In the transistor 440a, which is manufactured using this embodiment and includes a highly purified oxide semiconductor stack 403 containing excess oxygen to compensate for oxygen vacancies, the current value in the off state (off current value) is 100zA/μm (1zA (zeptoampere) is 1×10 ^-21 A) or less, preferably 10zA/μm or less, more preferably 1zA/μm at room temperature per μm.
It can be lowered to a level of 100 yA/μm or less, more preferably 100 yA/μm or less.

As described above, it is possible to provide semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption.

(Embodiment 2)
In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 7, 8, and 11. The same parts or parts and steps having similar functions as those in the above embodiment can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. Further, detailed explanations of the same parts will be omitted.

In this embodiment, an example of a structure in which an upper oxide semiconductor layer covers a side surface of a lower oxide semiconductor layer in an oxide semiconductor stack is shown.

The transistor 340 illustrated in FIGS. 7A to 7C is an example of an inverted staggered transistor having a bottom gate structure. FIG. 7(A) is a plan view, and the dashed-dot line X in FIG. 7(A)
The cross section taken along the line -Y corresponds to FIG. 7(B), and the cross section taken along the dashed line VW in FIG. 7(A) corresponds to FIG. 7(C).

As shown in FIG. 7B, which is a cross-sectional view in the channel length direction, the transistor 340 includes a gate electrode layer 401, a gate insulating film 402, and a gate insulating film 402, which are sequentially provided on a substrate 400 having an insulating surface.
First oxide semiconductor layer 101 and second oxide semiconductor layer 10 with different energy gaps
2, a source electrode layer 405a, and a drain electrode layer 405b. Note that an insulating film 407 is formed over the transistor 340.

The first oxide semiconductor layer 101 is formed in contact with the gate insulating film 402, and the second oxide semiconductor layer 102 is formed to cover the top and side surfaces of the first oxide semiconductor layer 101. 2
The peripheral portion of the oxide semiconductor layer 102 is in contact with the gate insulating film 402. 1st
The structure in which the oxide semiconductor layer 101 is not in contact with the source electrode layer 405a or the drain electrode layer 405b reduces the occurrence of leakage current (parasitic channel) in the source electrode layer 405a and the drain electrode layer 405b of the transistor 340. ing.

FIG. 7(C) is a cross-sectional view in the channel width direction, and similarly to FIG. 7(B), the end (side surface) of the first oxide semiconductor layer 101 is the end of the second oxide semiconductor layer 102. The structure is such that the first oxide semiconductor layer 101 is not in contact with the insulating film 407.

The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different energy gaps. In this embodiment, the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102
This is an example in which the compositions are different and the energy gap of the second oxide semiconductor layer 102 is larger than that of the first oxide semiconductor layer 101.

8A to 8C show a three-layer stacked structure of a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103 as an oxide semiconductor stack 403. A transistor 380a used is shown.

A transistor 380a illustrated in FIGS. 8A to 8C is an example of an inverted staggered transistor having a bottom gate structure. FIG. 8(A) is a plan view, and the cross section cut along the dashed-dotted line XY in FIG. 8(A) corresponds to FIG. 8(B), and the cross-section cut along the dashed-dotted line The cut cross section corresponds to FIG. 8(C).

As shown in FIG. 8B, which is a cross-sectional view in the channel length direction, the transistor 380a includes a gate electrode layer 401 and a gate insulating film 402, which are sequentially provided on a substrate 400 having an insulating surface.
, an oxide semiconductor stack 403 including a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103, a source electrode layer 405a, and a drain electrode layer 405.
It has b. An insulating film 407 is formed over the transistor 380a.

The first oxide semiconductor layer 101 is formed in contact with the gate insulating film 402, and the second oxide semiconductor layer 102 is stacked over the first oxide semiconductor layer 101. Third oxide semiconductor layer 1
03 is formed to cover the side surfaces of the first oxide semiconductor layer 101 and the top and side surfaces of the second oxide semiconductor layer 102, and the peripheral portion of the third oxide semiconductor layer 103 is formed by the gate insulating film 402.
The structure is in contact with the First oxide semiconductor layer 101 and second oxide semiconductor layer 102
By having a structure in which the transistor 380a is not in contact with the source electrode layer 405a or the drain electrode layer 405b, generation of leakage current (parasitic channel) in the source electrode layer 405a and the drain electrode layer 405b of the transistor 380a is reduced.

FIG. 8C is a cross-sectional view in the channel width direction, and similarly to FIG. 8B, the ends (side surfaces) of the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are oxide semiconductor layer 103 of
The structure is such that the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 are not in contact with the insulating film 407 .

The first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 have different energy gaps. This embodiment is an example in which the energy gap of the second oxide semiconductor layer 102 is smaller than that of the first oxide semiconductor layer 101.

Further, the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 have different energy gaps. In this embodiment, the energy gap of the third oxide semiconductor layer 103 is the second
This is an example in which the energy gap is larger than that of the oxide semiconductor layer 102.

Note that in this embodiment, the energy gap of the third oxide semiconductor layer 103 is
This is approximately the same as the energy gap of the first oxide semiconductor layer 101.

For example, as the first oxide semiconductor layer 101 in the transistor 380a, In-Ga-
A Zn-based oxide film (energy gap 3.2 eV), an In-Sn-Zn-based oxide film (energy gap 2.8 eV) as the second oxide semiconductor layer 102, and an In-Sn-based oxide film (energy gap 2.8 eV) as the third oxide semiconductor layer 103. - A Ga-Zn based oxide film (energy gap 3.2 eV) is used.

Further, as the three-layer oxide semiconductor stack 403 like the transistor 380a, the first
An In-Ga-Zn-based oxide film is used as the oxide semiconductor layer 101 of the second oxide semiconductor layer 10.
2 is an In-Zn based oxide film, and the third oxide semiconductor layer 103 is an In-Ga-Zn film.
a Ga-Zn-based oxide film as the first oxide semiconductor layer 101, an In-Sn-Zn-based oxide film as the second oxide semiconductor layer 102, and a third oxide semiconductor. layer 103
The first oxide semiconductor layer 101 is a Ga-Zn oxide film, the second oxide semiconductor layer 102 is an In-Zn oxide film, and the third oxide semiconductor layer 102 is an In-Zn oxide film. The semiconductor layer 103 is a stack of Ga--Zn oxide films, and the first oxide semiconductor layer 101 is In
-Ga-based oxide film, In--Ga--Zn-based oxide film as the second oxide semiconductor layer 102,
The third oxide semiconductor layer 103 is a stack of In-Ga-based oxide films, the first oxide semiconductor layer 101 is an In-Ga-Zn-based oxide film, and the second oxide semiconductor layer 102 is an oxide film. Indium (In-based oxide) film, In-Ga-Zn as the third oxide semiconductor layer 103
A stack of oxide films or the like can be used.

Furthermore, by covering the second oxide semiconductor layer 102 with the first oxide semiconductor layer 101 and the third oxide semiconductor layer 103, an increase in oxygen vacancies in the second oxide semiconductor layer 102 is suppressed. , the threshold voltage of the transistor 380a can be made close to zero. Furthermore, since the second oxide semiconductor layer 102 serves as a buried channel, the channel formation region can be moved away from the insulating film interface, thereby reducing interfacial scattering of carriers and achieving high field effect mobility. I can do it.

The transistor 380b illustrated in FIG. 11A uses the same mask when processing the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 into an island shape (or an island formed by processing). In this structure, a part of the gate insulating film 402 is etched and made thin using the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 as masks. transistor 3
In 80b, the gate insulating film 402 is thicker in a region overlapping with the island-shaped first oxide semiconductor layer 101 and second oxide semiconductor layer 102 than in other regions (regions that do not overlap). have. When processing the first oxide semiconductor layer 101 and the second oxide semiconductor layer 102 into island shapes, by etching up to part of the gate insulating film 402, residues of the first oxide semiconductor layer 101, etc. It is possible to remove etching residue and reduce the occurrence of leakage current.

Further, a transistor 380c illustrated in FIG. 11B has a structure in which an oxide semiconductor stack 403 is formed through three photolithography steps. The oxide semiconductor stack 403 included in the transistor 380c is formed by forming an island-shaped first oxide semiconductor layer 101 using a first mask after forming a first oxide semiconductor film, and forming an island-shaped first oxide semiconductor layer 101 using a first mask. After forming a second oxide semiconductor film over the first oxide semiconductor layer 101, an island-shaped second oxide semiconductor layer 102 is formed using a second mask, and the island-shaped first oxide semiconductor layer 102 is formed using a second mask. A third oxide semiconductor film is formed over the semiconductor layer 101 and the second oxide semiconductor layer 102, and then processed into an island-shaped third oxide semiconductor layer 103 using a third mask. ,It is formed.

Note that the transistor 380c has a structure in which the end surface of the first oxide semiconductor layer 101 protrudes from the side surface of the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 is formed on the side surface of the first oxide semiconductor layer 102. This is an example of a structure in which it is in contact with a part of the upper surface of the layer 101.

Further, as another form of a semiconductor device, FIG. 9B shows a channel protection type transistor 418 having a bottom gate structure.

As shown in FIG. 9B, which is a cross-sectional view in the channel length direction, the transistor 418 includes a gate electrode layer 401, a gate insulating film 402, and a gate insulating film 402, which are provided in this order over a substrate 400 having an insulating surface.
An oxide semiconductor stack 403 including a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103, an insulating film 427 functioning as a channel protection film, a source electrode layer 405a, It has a drain electrode layer 405b. An insulating film 409 is formed over the transistor 418.

The first oxide semiconductor layer 101 is formed in contact with the gate insulating film 402, and the second oxide semiconductor layer 102 is stacked over the first oxide semiconductor layer 101. Third oxide semiconductor layer 1
03 is formed to cover the side surfaces of the first oxide semiconductor layer 101 and the top and side surfaces of the second oxide semiconductor layer 102, and the peripheral portion of the third oxide semiconductor layer 103 is formed by the gate insulating film 402.
The structure is in contact with the First oxide semiconductor layer 101 and second oxide semiconductor layer 102
By having a structure in which the transistor 418 is not in contact with the source electrode layer 405a or the drain electrode layer 405b, generation of leakage current (parasitic channel) in the source electrode layer 405a and the drain electrode layer 405b of the transistor 418 is reduced.

Further, as another form of the semiconductor device, a bottom gate structure transistor 4 is shown in FIG. 10(B).
38 is shown.

As shown in FIG. 10B, the transistor 438 includes a gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, a drain electrode layer 405b, and a first oxide layer that are provided in this order over the substrate 400 having an insulating surface. The oxide semiconductor stack 403 includes an oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103. transistor 438
An insulating film 407 is formed thereon.

The transistor 438 includes an oxide semiconductor stack 403 including the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 over the source electrode layer 405a and the drain electrode layer 405b. It is a structure provided. At least one of the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 has a different energy gap.

In the transistor 438, the first oxide semiconductor layer 101 is formed in contact with the source electrode layer 405a and the drain electrode layer 405b, and the second oxide semiconductor layer 102 is stacked over the first oxide semiconductor layer 101. be done. The third oxide semiconductor layer 103 is formed to cover the side surfaces of the first oxide semiconductor layer 101 and the top and side surfaces of the second oxide semiconductor layer 102,
The periphery of the third oxide semiconductor layer 103 includes the source electrode layer 405a and the drain electrode layer 40.
5b.

In this way, the shapes of the stacked oxide semiconductor layers may be different for each oxide semiconductor layer, and various shapes and structures can be selected for the stacked oxide semiconductor layers.

As described above, it is possible to provide semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 3)
In this embodiment, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. The same parts or parts and steps having similar functions as those in the above embodiment can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. Further, detailed explanations of the same parts will be omitted.

In this embodiment, in the method for manufacturing a semiconductor device according to the disclosed invention, oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions) is added to an oxide semiconductor stack that has been subjected to dehydration or dehydrogenation treatment. An example of supplying oxygen into the film by introducing oxygen (including

Due to the dehydration or dehydrogenation treatment, oxygen, which is the main component of the oxide semiconductor, may be simultaneously desorbed and reduced. In the oxide semiconductor stack, oxygen vacancies exist at locations where oxygen is desorbed, and the oxygen vacancies generate donor levels that cause changes in the electrical characteristics of the transistor.

Therefore, it is preferable to supply oxygen to the oxide semiconductor stack that has been subjected to dehydration or dehydrogenation treatment. By supplying oxygen to the oxide semiconductor stack, oxygen vacancies in the film can be compensated for. By using the oxide semiconductor stack in a transistor, variations in the threshold voltage Vth of the transistor due to oxygen vacancies and a shift ΔVth in the threshold voltage can be reduced. Furthermore, the threshold voltage can be shifted positively to make the transistor normally off.

5A corresponds to FIG. 2C, in which a gate electrode layer 401, a gate insulating film 402, and a first oxide semiconductor layer 1 having a different energy gap are formed over a substrate 400 having an insulating surface.
An oxide semiconductor stack 403 including oxide semiconductor layer 01 and second oxide semiconductor layer 102 is formed.

Next, oxygen 431 (containing at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the oxide semiconductor stack 403 to form the first oxide semiconductor layer 101 and the second oxide semiconductor layer. Oxygen-excess regions 111 and 112 are formed in the oxide semiconductor stack 403 including the oxide semiconductor layer 102, and oxygen is supplied thereto (see FIG. 5B).

Note that the oxygen-excess regions 111 and 112 are regions in which at least part of the oxide semiconductor contains an excess amount of oxygen relative to the stoichiometric composition ratio when the oxide semiconductor is in a crystalline state. The oxygen 431 supplied to the oxygen-excess regions 111 and 112 causes the first oxide semiconductor layer 101 to
In addition, oxygen vacancies present in the oxide semiconductor stack 403 including the second oxide semiconductor layer 102 can be compensated for.

A source electrode layer 405a and a drain electrode layer 405b are formed over the oxide semiconductor stack 403 including the gate insulating film 402 and the oxygen-excess regions 111 and 112, and a transistor 443a is manufactured (see FIG. 5C).

Note that the step of introducing oxygen 431 can also be performed after forming the source electrode layer 405a and the drain electrode layer 405b. FIG. 5D shows an example in which oxygen is introduced into the oxide semiconductor stack 403 including the oxide semiconductor layer 101 and the second oxide semiconductor layer 102 after the source electrode layer 405a and the drain electrode layer 405b are formed. A transistor 443b is shown.

As shown in FIG. 5(D), oxygen 431 is present in the source electrode layer 405a and the drain electrode layer 405b.
serves as a mask and is selectively introduced into the channel formation region of the oxide semiconductor stack 403 including the oxide semiconductor layer 101 and the second oxide semiconductor layer 102. In the oxide semiconductor stack 403 of the transistor 443b, a region that does not overlap with the source electrode layer 405a or the drain electrode layer 405b has a higher oxygen concentration than a region that overlaps with the source electrode layer 405a or the drain electrode layer 405b.

Further, as another form of a semiconductor device, FIG. 4B shows a transistor 483 having a bottom gate structure in which oxygen is introduced into the oxide semiconductor stack 403. FIG. 4A shows a transistor 480 in which the oxide semiconductor stack 403 has a three-layer structure of a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer 103. shows.

The transistor 483 includes a first oxide semiconductor layer 101 including a gate electrode layer 401, a gate insulating film 402, and an oxygen-excess region 111, which are provided in this order over a substrate 400 having an insulating surface.
, an oxide semiconductor stack 403 including a second oxide semiconductor layer 102 including an oxygen-excess region 112 and a third oxide semiconductor layer 103 including an oxygen-excess region 113, a source electrode layer 405a,
It has a drain electrode layer 405b. An insulating film 407 is formed over the transistor 483.

In the oxide semiconductor stack 403 of the transistor 483, the first oxide semiconductor layer 101,
The energy gaps of the second oxide semiconductor layer 102 and the third oxide semiconductor layer 103 are not all the same, and include energy gaps of at least two different values.

The transistor 483 is an example in which oxygen is introduced throughout the oxide semiconductor stack 403, and the first
An oxygen-excess region 111, an oxygen-excess region 112, or an oxygen-excess region 113 is provided throughout the oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103, respectively. .

Further, as another form of a semiconductor device, FIG. 9C shows a channel protection transistor 413 having a bottom gate structure in which oxygen is introduced into the oxide semiconductor stack 403.

The transistor 413 includes a first oxide semiconductor layer 101 including a gate electrode layer 401, a gate insulating film 402, and an oxygen-excess region 111, which are provided in this order over a substrate 400 having an insulating surface.
An oxide semiconductor stack 403 including a second oxide semiconductor layer 102 including an oxygen-excess region 112 and a third oxide semiconductor layer 103 including an oxygen-excess region 113, an insulating film 427 functioning as a channel protective film, and a source electrode. It has a layer 405a and a drain electrode layer 405b. An insulating film 409 is formed over the transistor 413.

At least one of the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 has a different energy gap from the other oxide semiconductor layers. In the transistor 413, the energy gap of the second oxide semiconductor layer 102 is smaller than that of the first oxide semiconductor layer 101 and the third oxide semiconductor layer 103.

The transistor 413 is an example in which oxygen is introduced throughout the oxide semiconductor stack 403, and the first
An oxygen-excess region 111, an oxygen-excess region 112, or an oxygen-excess region 113 is provided throughout the oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103, respectively. .

Further, in the transistor 413, the first oxide semiconductor layer 101 is formed by the gate insulating film 40.
2, and the second oxide semiconductor layer 102 is stacked over the first oxide semiconductor layer 101. The third oxide semiconductor layer 103 is formed to cover the side surface of the first oxide semiconductor layer 101 and the top surface and side surface of the second oxide semiconductor layer 102.
The peripheral portion of 03 has a structure in which it is in contact with the gate insulating film 402. First oxide semiconductor layer 1
01 and the second oxide semiconductor layer 102 as the source electrode layer 405a or the drain electrode layer 40
5b, the occurrence of leakage current (parasitic channel) in the source electrode layer 405a and drain electrode layer 405b of the transistor 413 is reduced.

Further, as another form of a semiconductor device, FIG. 10C shows a bottom-gate transistor 433 in which oxygen is introduced into the oxide semiconductor stack 403.

As shown in FIG. 10C, the transistor 433 includes a gate electrode layer 401, a gate insulating film 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxygen-excess region 111, which are provided in this order over the substrate 400 having an insulating surface. an oxide semiconductor stack 403 including a first oxide semiconductor layer 101 including an oxygen-excess region 112, a second oxide semiconductor layer 102 including an oxygen-excess region 112, and a third oxide semiconductor layer 103 including an oxygen-excess region 113. . On the transistor 433,
An insulating film 407 is formed.

In the transistor 433, an oxide semiconductor stack 403 including a first oxide semiconductor layer 101, a second oxide semiconductor layer 102, and a third oxide semiconductor layer is provided over a source electrode layer 405a and a drain electrode layer 405b. It is a structure that can be used. At least one of the first oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103 has a different energy gap from the other oxide semiconductor layers, and the transistor 433 has a different energy gap from the other oxide semiconductor layers. Oxide semiconductor layer 1
02 energy gap between the first oxide semiconductor layer 101 and the third oxide semiconductor layer 10
This is an example of a value smaller than 3.

The transistor 433 is an example in which oxygen is introduced throughout the oxide semiconductor stack 403, and the first
An oxygen-excess region 111, an oxygen-excess region 112, or an oxygen-excess region 113 is provided throughout the oxide semiconductor layer 101, the second oxide semiconductor layer 102, and the third oxide semiconductor layer 103, respectively. .

In the transistor 433, oxygen may be introduced directly into the exposed oxide semiconductor stack 403, or may be introduced through the insulating film 407.

Note that in the transistor 340 and the transistor 380a described in Embodiment 2, in which the upper oxide semiconductor layer covers the side surfaces of the lower oxide semiconductor layer, the oxide semiconductor stack 40
7(D) and FIG. 8(D) show an example in which oxygen is introduced into No. 3 to provide an oxygen-excess region.

In the transistor 343 in FIG. 7D, a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101 having a different energy gap, and a second oxide semiconductor layer are sequentially provided over a substrate 400 having an insulating surface. An oxide semiconductor stack 403 including a semiconductor layer 102, a source electrode layer 405a, and a drain electrode layer 405b are included. An insulating film 407 is formed over the transistor 343. In the transistor 343, the oxide semiconductor stack 403 includes the first oxide semiconductor layer 101 including the oxygen-excess region 111 and the second oxide semiconductor layer 102 including the oxygen-excess region 112.

In the transistor 383 in FIG. 8D, a gate electrode layer 401, a gate insulating film 402, a first oxide semiconductor layer 101 having a different energy gap, and a second oxide semiconductor layer are provided in this order over a substrate 400 having an insulating surface. The oxide semiconductor stack 403 includes an oxide semiconductor layer 102, a third oxide semiconductor layer 103, a source electrode layer 405a, and a drain electrode layer 405b. An insulating film 407 is formed over the transistor 383. In the transistor 383, the oxide semiconductor stack 403 includes the first oxide semiconductor layer 10 including the oxygen-excess region 111.
1, a second oxide semiconductor layer 102 including an oxygen-excess region 112, and a third oxide semiconductor layer 103 including an oxygen-excess region 113.

Note that in an oxide semiconductor stack in which an oxide semiconductor layer with a larger energy gap than a lower oxide semiconductor layer is stacked as an upper layer, as shown in the transistor 343 and the transistor 383, the upper oxide semiconductor layer is stacked over the lower oxide semiconductor layer. By forming a structure in which the side surfaces of the layer are covered, generation of leakage current (parasitic channel) in the source electrode layer and drain electrode layer of the transistor can be reduced.

By introducing oxygen into the oxide semiconductor stack 403 that has been subjected to dehydration or dehydrogenation treatment and supplying oxygen into the film, the oxide semiconductor stack 403 is made highly purified and I-type (intrinsic). be able to. The transistors 443a, 443b, transistor 413, transistor 433, transistor 343, and transistor 383, which include the highly purified I-type (intrinsic) oxide semiconductor stack 403, have suppressed variations in electrical characteristics and are electrically stable. It is.

As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, etc. can be used.

In the step of introducing oxygen, when introducing oxygen into the oxide semiconductor stack 403, the oxide semiconductor stack 40
3, or may be introduced directly into the oxide semiconductor stack 40 by passing through another film such as the insulating film 407.
3 may be introduced. When oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used; however, when oxygen is introduced directly into the exposed oxide semiconductor stack 403 Alternatively, plasma treatment or the like can also be used.

The introduction of oxygen into the oxide semiconductor stack 403 is not particularly limited as long as it is performed after dehydration or dehydrogenation treatment. Further, oxygen may be introduced multiple times into the oxide semiconductor stack 403 that has been subjected to the dehydration or dehydrogenation treatment.

For example, in Embodiment 1, when oxygen is introduced into the oxide semiconductor stack 403, the source electrode layer 405 is introduced into the exposed oxide semiconductor film stack 493 or the oxide semiconductor stack 403.
a. It can be performed after forming the drain electrode layer 405b, after forming the gate insulating film 402, after forming the gate electrode layer 401, and after forming the insulating film 407.

Further, in the oxygen-excess regions 111 and 112 in the oxide semiconductor stack 403, the oxygen concentration introduced in the oxygen introduction step is set to 1×10 ¹⁸ atoms/cm ³ or more and 5×10 ²¹ at
It is preferable to set it to oms/ ^cm3 or less.

Note that oxygen is one of the main component materials in the oxide semiconductor. Therefore, it is difficult to accurately estimate the oxygen concentration in the oxide semiconductor stack 403 using a method such as SIMS. In other words, it can be said that it is difficult to determine whether oxygen was intentionally added to the oxide semiconductor stack 403.

By the way, it is known that oxygen has isotopes such as ¹⁷ O and ¹⁸ O, and the abundance ratio of these in nature is about 0.037% and 0.204% of the total oxygen atoms, respectively. In other words, when these isotopes are intentionally added to the oxide semiconductor stack 403, the concentrations of these isotopes can be estimated by a method such as SIMS, and by measuring these concentrations, the oxide semiconductor stack 403 It may be possible to estimate the oxygen concentration in the stack 403 more accurately. Therefore, by measuring these concentrations, it may be determined whether oxygen has been intentionally added to the oxide semiconductor stack 403.

Further, heat treatment is preferably performed after introducing oxygen into the oxide semiconductor film.

When oxygen is directly introduced into the oxide semiconductor stack 403 as in the transistors 443a and 443b of this embodiment, the gate insulating film 4 in contact with the oxide semiconductor stack 403
02. The insulating film 407 does not necessarily need to be a film containing a large amount of oxygen. A blocking effect is provided for impurities such as oxygen, hydrogen, and water so that the introduced oxygen does not desorb from the oxide semiconductor stack 403 again and impurities such as hydrogen and water do not enter the oxide semiconductor stack 403 again. It is preferable to provide a film with high (blocking effect) as the insulating film 407. For example, it is preferable to use an aluminum oxide film, which has a high blocking effect against both impurities such as hydrogen and water, and oxygen.

Of course, the gate insulating film 402 and the insulating film 407 in contact with the oxide semiconductor film may be films containing a large amount of oxygen, oxygen may be directly introduced into the oxide semiconductor stack 403, and a plurality of oxygen supply methods may be performed.

Further, in this embodiment, introduction of oxygen into the oxide semiconductor stack 403 will be described as an example; however, oxygen may also be introduced into the gate insulating film 402, the insulating film 407, and the like that are in contact with the oxide semiconductor stack 403. Oxygen can be supplied to the oxide semiconductor stack 403 by introducing oxygen into the gate insulating film 402 and the insulating film 407 that are in contact with the oxide semiconductor stack 403 to make the oxygen excessive.

As described above, a semiconductor device using an oxide semiconductor stack having stable electrical characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 4)
In this embodiment mode, another embodiment of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. The same parts or parts and steps having similar functions as those in the above embodiment can be performed in the same manner as in the above embodiment, and repeated explanations will be omitted. Further, detailed explanations of the same parts will be omitted.

This embodiment is an example in which a low resistance region is formed in an oxide semiconductor stack in a method for manufacturing a semiconductor device according to the disclosed invention. The low resistance region can be formed by introducing an impurity (also referred to as a dopant) that changes the conductivity into the oxide semiconductor stack.

In this embodiment, an example of a channel protection type transistor 420 having a bottom gate structure is shown. FIGS. 6A to 6C illustrate an example of a method for manufacturing the transistor 420.

First, a gate electrode layer 401 is formed on a substrate 400 having an insulating surface.
1, a gate insulating film 402 is formed on top of the gate insulating film 402.

A first oxide semiconductor layer 101 having a different energy gap is formed on the gate insulating film 402.
Then, an oxide semiconductor stack 403 including the second oxide semiconductor layer 102 is formed.

Note that oxygen may be introduced into the oxide semiconductor stack 403 as described in Embodiment 2, so that the oxide semiconductor stack 403 may include an oxygen-excess region. Further, the oxide semiconductor stack 403 may have a three-layer structure, and the upper oxide semiconductor layer may cover the side surface of the lower oxide semiconductor layer.

An insulating film 427 functioning as a channel protective film is formed over the oxide semiconductor stack 403 that overlaps with the gate electrode layer 401 (see FIG. 6A).

Next, using the insulating film 427 as a mask, a dopant 421 is selectively introduced into the oxide semiconductor stack 403 to form low resistance regions 121a, 121b, 122a, and 122b (FIG. 6).
See B).

In this embodiment, the insulating film 427 that functions as a channel protective film is used as a mask in the step of introducing the dopant 421, but a resist mask is formed separately and the dopant 421 is
may be introduced selectively. Further, in the case of the transistor 440a, the transistor 430, etc. in which a channel protective film is not provided, a resist mask may be formed separately and a dopant may be selectively introduced.

Depending on the conditions for introducing the dopant 421, if the dopant 421 is introduced only into the first oxide semiconductor layer 101 or only into the second oxide semiconductor layer 102 to form a low resistance region, the first oxide semiconductor layer There may be a dopant concentration distribution in the oxide semiconductor layer 101 and the second oxide semiconductor layer 102.

The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor stack 403. Dopants 421 include Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), and argon (Ar).
), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (C
1), titanium (Ti), and zinc (Zn).

The dopant 421 is introduced into the oxide semiconductor stack 403 by an injection method. dopant 4
As a method for introducing 21, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, etc. can be used. In that case, dopant 421
It is preferable to use a single ion of , or an ion of fluoride or chloride.

The step of introducing the dopant 421 may be controlled by appropriately setting implantation conditions such as accelerating voltage and dose amount, and the thickness of the insulating film 427 serving as a mask. In this embodiment, the dopant 42
Using boron as No. 1, boron ions are implanted by an ion implantation method. Note that the dose amount of the dopant 421 may be 1×10 ¹³ ions/cm ² or more and 5×10 ¹⁶ ions/cm ² or less.

The concentration of the dopant 421 in the low resistance region is 5×10 ¹⁸ atoms/cm ³ or more 1
It is preferable that it is not more than ×10 ²² atoms/cm ³ .

The dopant 421 may be introduced while the substrate 400 is being heated.

Note that the process of introducing the dopant 421 into the oxide semiconductor stack 403 may be performed multiple times, and multiple types of dopants may be used.

Furthermore, after the dopant 421 introduction treatment, heat treatment may be performed. The heating conditions are preferably 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower for 1 hour in an oxygen atmosphere. Further, the heat treatment may be performed in a nitrogen atmosphere, under reduced pressure, or in the atmosphere (ultra-dry air).

When the oxide semiconductor stack 403 is a crystalline oxide semiconductor film, part of the film may become amorphous due to the introduction of the dopant 421. In this case, by performing heat treatment after introducing the dopant 421, the crystallinity of the oxide semiconductor stack 403 can be recovered.

Therefore, in the oxide semiconductor stack 403, the first oxide semiconductor layer 101 in which the low resistance regions 121a and 121b are provided with the channel formation region 121c sandwiched therebetween, and the channel formation region 12
A second oxide semiconductor layer 102 is formed in which low resistance regions 122a and 122b are provided with 2c sandwiched therebetween.

Next, the source electrode layer 405 is in contact with the low resistance regions 121a, 121b, 122a, and 122b.
a. Form a drain electrode layer 405b.

Through the above steps, the transistor 420 of this embodiment is manufactured (see FIG. 6C).

A first oxide semiconductor layer 101 in which low resistance regions 121a and 121b are provided with a channel formation region 121c in between, and a second oxide semiconductor layer 101 in which low resistance regions 122a and 122b are provided in the channel length direction with a channel formation region 122c in between. By including the oxide semiconductor stack 403 including the oxide semiconductor layer 102, the transistor 420 has high on-characteristics (for example, on-state current and field-effect mobility), and is capable of high-speed operation and high-speed response.

In the transistor 420, the low resistance regions 121a, 121b, 122a, and 122b can function as a source region or a drain region. Low resistance regions 121a, 12
1b, 122a, 122b, the low resistance regions 121a, 121b, 12
The electric field applied to the channel forming regions 121c and 122c formed between 2a and 122b can be relaxed. Further, by electrically connecting the oxide semiconductor stack 403, the source electrode layer 405a, and the drain electrode layer 405b in the low resistance regions 121a, 121b, 122a, and 122b, the oxide semiconductor stack 403, the source electrode layer 405a, and the drain Contact resistance with the electrode layer 405b can be reduced. Therefore, the electrical characteristics of the transistor can be improved.

This embodiment can be implemented in combination with other embodiments as appropriate.

(Embodiment 5)
A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor shown as an example in any of Embodiments 1 to 4. Further, part or all of a drive circuit including a transistor can be integrally formed over the same substrate as a pixel portion, so that a system on panel can be formed.

In FIG. 12A, a sealant 4005 is provided to surround a pixel portion 4002 provided over a first substrate 4001, and is sealed by a second substrate 4006. Figure 1
In 2(A), a scanning film formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is formed in a region different from the region surrounded by the sealant 4005 on the first substrate 4001. A line drive circuit 4004 and a signal line drive circuit 4003 are mounted. In addition, various signals and potentials applied to a separately formed signal line drive circuit 4003, scanning line drive circuit 4004, or pixel portion 4002 are transferred to an FPC (Flexible printed circuit).
it) 4018a, 4018b.

In FIGS. 12B and 12C, a sealing material 4005 is provided to surround a pixel portion 4002 provided over a first substrate 4001 and a scanning line driver circuit 4004. Further, a second substrate 4006 is provided over the pixel portion 4002 and the scanning line driver circuit 4004.
Therefore, the pixel portion 4002 and the scanning line driver circuit 4004 are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006. Figure 12 (B
) In (C), a signal formed with a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is placed in a region different from the region surrounded by the sealant 4005 on the first substrate 4001. A line drive circuit 4003 is mounted. In FIGS. 12B and 12C, various signals and potentials are supplied to a separately formed signal line driver circuit 4003, a scanning line driver circuit 4004, or a pixel portion 4002 from an FPC 4018.

Further, although FIGS. 12B and 12C show an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001, the structure is not limited to this. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line drive circuit or a part of the scan line drive circuit may be separately formed and mounted.

Note that the method of connecting the separately formed drive circuit is not particularly limited, and COG (Ch
ip on glass) method, wire bonding method, or TAB (Tape A
Automated Bonding method, etc. can be used. FIG. 12(A) is
This is an example in which a signal line driver circuit 4003 and a scanning line driver circuit 4004 are implemented using the COG method, and FIG. 12B is an example in which the signal line driver circuit 4003 is implemented using the COG method.
2(C) is an example in which the signal line driver circuit 4003 is mounted using the TAB method.

Further, the display device includes a panel in which a display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, connectors such as modules with FPC, TAB tape or TCP attached, modules with a printed wiring board provided at the end of TAB tape or TCP, or ICs (integrated circuits) directly mounted on display elements using the COG method. All modules are also included in the display device.

Further, the pixel portion and the scanning line driver circuit provided over the first substrate include a plurality of transistors, and the transistors exemplified in any of Embodiments 1 to 4 can be used.

Display elements provided in display devices include liquid crystal elements (also referred to as liquid crystal display elements) and light emitting elements (
(also referred to as a light emitting display element) can be used. Light emitting elements include elements whose brightness is controlled by current or voltage, and specifically include inorganic EL (Electro
Luminescence), organic EL, etc. Furthermore, display media whose contrast changes due to electrical action, such as electronic ink, can also be used.

One form of a semiconductor device will be described with reference to FIGS. 12 and 13. Figure 13 is different from Figure 12 (
This corresponds to the cross-sectional view taken along MN in B).

As shown in FIG. 13, the semiconductor device has a connection terminal electrode 4015 and a terminal electrode 4016. It is connected to the.

The connection terminal electrode 4015 is formed from the same conductive film as the first electrode layer 4030, and is
016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the transistors 4010 and 4011.

Furthermore, the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 are
It has a plurality of transistors, and in FIG. 13, transistor 4 included in the pixel portion 4002
010 and a transistor 4011 included in the scanning line driver circuit 4004 are illustrated.
In FIG. 13A, an insulating film 4020 is provided over the transistors 4010 and 4011,
In FIG. 13B, an insulating film 4021 is further provided. Note that the insulating film 4023 is an insulating film that functions as a base film.

As the transistors 4010 and 4011, the transistors described in any of Embodiments 1 to 4 can be used. In this embodiment, an example is shown in which a transistor having the same structure as the transistor 440a described in Embodiment 1 is used.

The transistor 4010 and the transistor 4011 are transistors each having an oxide semiconductor stack including at least two oxide semiconductor layers with different energy gaps. By using an oxide semiconductor stack including a plurality of oxide semiconductor layers having different energy gaps, the electrical characteristics of the transistor can be controlled with more precision, and desired electrical characteristics can be imparted to the transistors 4010 and 4011. becomes possible.

Therefore, the semiconductor device of this embodiment shown in FIGS. 12 and 13 has high functionality, high reliability,
Alternatively, semiconductor devices suitable for various purposes such as low power consumption can be provided.

A transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be used.

FIG. 13A shows an example of a liquid crystal display device using a liquid crystal element as a display element. Figure 13(A)
, a liquid crystal element 4013 which is a display element has a first electrode layer 4030 and a second electrode layer 4.
031 and a liquid crystal layer 4008. Note that insulating films 4032 and 4033 functioning as alignment films are provided to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are connected to the liquid crystal layer 4.
The structure is such that they are laminated via 008.

Further, 4035 is a columnar spacer obtained by selectively etching the insulating film,
It is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical spacer may be used.

When using a liquid crystal element as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

Further, a liquid crystal composition that exhibits a blue phase without using an alignment film may be used for the liquid crystal layer 4008. The blue phase is one of the liquid crystal phases, and is a phase that appears just before the cholesteric phase transitions to the isotropic phase when the cholesteric liquid crystal is heated. A blue phase can be developed using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. In addition, in order to widen the temperature range in which a blue phase appears, a liquid crystal layer is formed by adding polymerizable monomers, polymerization initiators, etc. to a liquid crystal composition that shows a blue phase, and performing polymer stabilization treatment. You can also do it. A liquid crystal composition that exhibits a blue phase has a short response speed, is optically isotropic, requires no alignment treatment, and has low viewing angle dependence. Furthermore, since there is no need to provide an alignment film, there is no need for a rubbing process, so it is possible to prevent electrostatic damage caused by the rubbing process, and reduce defects and damage to the liquid crystal display device during the manufacturing process. . Therefore, it becomes possible to improve the productivity of the liquid crystal display device. In a transistor using an oxide semiconductor film, the electrical characteristics of the transistor may vary significantly due to the influence of static electricity, and there is a possibility that the transistor may deviate from a design range. Therefore, it is more effective to use a liquid crystal composition that exhibits a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor film.

Further, the specific resistance of the liquid crystal material is 1×10 ⁹ Ω·cm or more, preferably 1×10 ¹¹
It is at least Ω·cm, more preferably at least 1×10 ¹² Ω·cm. Note that the value of specific resistance in this specification is a value measured at 20°C.

The size of the storage capacitor provided in the liquid crystal display device is set so as to be able to hold charge for a predetermined period of time, taking into account leakage current of transistors arranged in the pixel portion. The size of the storage capacitor may be set in consideration of the off-state current of the transistor and the like. By using a transistor including an oxide semiconductor film disclosed in this specification, a storage capacitor having a capacitance of 1/3 or less, preferably 1/5 or less of the liquid crystal capacitance in each pixel is provided. That's enough.

A transistor using an oxide semiconductor film disclosed in this specification has a current value (
(off-state current value) can be controlled low. Therefore, the holding time of electrical signals such as image signals can be increased, and the writing interval can also be set longer in the power-on state. Therefore, the frequency of refresh operations can be reduced, which has the effect of suppressing power consumption.

Further, the transistor including the oxide semiconductor film disclosed in this specification can control field-effect mobility to a high degree, and therefore can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a drive circuit portion can be formed on the same substrate.
That is, since there is no need to use a semiconductor device formed from a silicon wafer or the like as a separate drive circuit, the number of components of the semiconductor device can be reduced. Furthermore, by using transistors that can be driven at high speed in the pixel portion, it is possible to provide high-quality images. Therefore, it is possible to achieve high reliability as a semiconductor device.

The liquid crystal display device has TN (Twisted Nematic) mode, IPS (In-P
lane-Switching) mode, FFS (Fringe Field Switching) mode,
ching) mode, ASM (Axially Symmetrically aligned)
Micro-cell) mode, OCB (Optical Compensated B)
FLC (Ferroelectric Liqui) mode,
d Crystal) mode, AFLC (AntiFerroelectric Liq)
uid Crystal) mode, etc. can be used.

Further, it may be a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device employing a vertical alignment (VA) mode. There are several vertical alignment modes, but
For example, MVA (Multi-Domain Vertical Alignment)
mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can be used. Further, it can also be applied to a VA type liquid crystal display device. What is a VA type liquid crystal display device?
This is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. A VA type liquid crystal display device is a type in which liquid crystal molecules are oriented perpendicularly to the panel surface when no voltage is applied. Furthermore, a method called multi-domain design or multi-domain design, in which a pixel is divided into several regions (sub-pixels) and molecules are tilted in different directions, can be used.

Further, in the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, an antireflection member, and the like are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as a light source.

Further, as a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Furthermore, the color elements controlled by pixels during color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white)
, or one or more colors such as yellow, cyan, magenta, etc. are added to RGB. In addition,
The size of the display area may be different for each color element dot. However, the disclosed invention is not limited to color display devices, but can also be applied to monochrome display devices.

Furthermore, a light emitting element that utilizes electroluminescence can be used as a display element included in the display device. Light-emitting elements that utilize electroluminescence are distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound, and the former is generally an organic compound.
The latter is called an inorganic EL element.

In an organic EL element, by applying a voltage to a light emitting element, electrons and holes are respectively injected from a pair of electrodes into a layer containing a luminescent organic compound, and a current flows. When these carriers (electrons and holes) recombine, the luminescent organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to this mechanism, such a light emitting element is called a current excitation type light emitting element.

Inorganic EL devices are classified into dispersed type inorganic EL devices and thin film type inorganic EL devices depending on their device configurations. A dispersion type inorganic EL device has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. Thin-film inorganic EL devices sandwich a light-emitting layer between dielectric layers,
Furthermore, it has a structure in which it is sandwiched between electrodes, and the luminescence mechanism is localized luminescence that utilizes the inner-shell electronic transition of metal ions. Note that an explanation will be given here using an organic EL element as a light emitting element.

The light-emitting element may have at least one of a pair of electrodes that is translucent in order to extract light emission. Then, a transistor and a light emitting element are formed on a substrate, and there is a top emission method in which light emission is extracted from the surface opposite to the substrate, a bottom emission method in which light emission is extracted from the surface on the substrate side, and a surface emission method such as the substrate side and the surface opposite to the substrate. There is a light emitting element with a double-sided emission structure that extracts light from the surface, and any light emitting element with any emission structure can be applied.

FIG. 13B shows an example of a light-emitting device using a light-emitting element as a display element. A light emitting element 4513 that is a display element is electrically connected to a transistor 4010 provided in the pixel portion 4002. Note that the structure of the light emitting element 4513 includes a first electrode layer 4030, an electroluminescent layer 4511,
Although the second electrode layer 4031 has a stacked structure, it is not limited to the illustrated structure. Light emitting element 451
The configuration of the light emitting element 4513 can be changed as appropriate depending on the direction of light extracted from the light emitting element 4513.

The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the sidewall of the opening becomes an inclined surface with a continuous curvature.

The electroluminescent layer 4511 may be composed of a single layer or may be composed of a plurality of stacked layers.

The second electrode layer 4 is formed to prevent oxygen, hydrogen, water, carbon dioxide, etc. from entering the light emitting element 4513.
A protective film may be formed on the partition wall 4510 and the partition wall 4510. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed. In addition, the first substrate 4001
A filler 451 is placed in the space sealed by the second substrate 4006 and the sealant 4005.
4 is provided and sealed. In order to avoid exposure to the outside air, it is preferable to package (seal) with a protective film (laminated film, ultraviolet curable resin film, etc.) or cover material that has high airtightness and less outgassing.

As the filler 4514, in addition to inert gases such as nitrogen and argon, ultraviolet curing resins or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( polyvinyl butyral) or EVA
(ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

In addition, if necessary, a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate),
Optical films such as a retardation plate (λ/4 plate, λ/2 plate) and a color filter may be provided as appropriate. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, it is possible to perform anti-glare treatment that can diffuse reflected light using surface irregularities and reduce reflections.

Furthermore, it is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper, also called an electrophoretic display, has the advantages of being as easy to read as paper, consuming less power than other display devices, and being thin and lightweight. ing.

The electrophoretic display device may have various forms, but it is one in which a plurality of microcapsules containing first particles with a positive charge and second particles with a negative charge are dispersed in a solvent or a solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions, and only the color of the particles gathered on one side is displayed. Note that the first particles or the second particles contain a dye and do not move in the absence of an electric field. Further, the color of the first particles and the color of the second particles are different (including colorless).

In this way, an electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect, in which a substance with a high dielectric constant moves to a high electric field region.

The above microcapsules dispersed in a solvent are called electronic ink, and this electronic ink can be printed on the surface of glass, plastic, cloth, paper, etc. Furthermore, color display is also possible by using color filters or particles containing pigments.

Note that the first particles and the second particles in the microcapsules are made of a conductor material, an insulator material,
A material selected from semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, electrochromic materials, and magnetophoretic materials, or a composite material thereof may be used.

Furthermore, a display device using a twist ball display method can also be applied as the electronic paper. In the twist ball display method, spherical particles painted in white and black are arranged between a first electrode layer and a second electrode layer, which are the electrode layers used in the display element. This is a method of displaying by controlling the orientation of spherical particles by creating a potential difference between two electrode layers.

Note that in FIGS. 12 and 13, the first substrate 4001 and the second substrate 4006 are as follows.
In addition to the glass substrate, a flexible substrate can also be used, such as a translucent plastic substrate. As a plastic, FRP (Fiberglass
Ass-Reinforced Plastics) board, PVF (polyvinyl fluoride) film, polyester film, or acrylic resin film can be used. Further, if translucency is not required, a metal substrate (metal film) such as aluminum or stainless steel may be used. For example, a sheet having a structure in which aluminum foil is sandwiched between PVF films or polyester films can also be used.

In this embodiment, an aluminum oxide film is used as the insulating film 4020.

The aluminum oxide film provided as the insulating film 4020 over the oxide semiconductor film has a high blocking effect of not allowing both impurities such as hydrogen and water to pass through the film, as well as oxygen.

Therefore, during and after the fabrication process, the aluminum oxide film is exposed to hydrogen and
It functions as a protective film that prevents impurities such as water from entering the oxide semiconductor film and preventing oxygen, which is the main component of the oxide semiconductor, from being released from the oxide semiconductor film.

Further, for the insulating film 4021 that functions as a planarizing insulating film, a heat-resistant organic material such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. can be used.
Note that the insulating film may be formed by stacking a plurality of insulating films made of these materials.

The method for forming the insulating film 4021 is not particularly limited, and may be sputtering, S
OG method, spin coating, dip, spray coating, droplet discharge method (inkjet method, etc.),
Printing methods (screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used.

A display device performs display by transmitting light from a light source or a display element. Therefore, thin films such as a substrate, an insulating film, and a conductive film provided in a pixel portion through which light passes are all transparent to light in the visible wavelength range.

In the first electrode layer and second electrode layer (also referred to as pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display element, the direction of the light to be extracted, the location where the electrode layer is provided, Translucency and reflectivity may be selected depending on the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium A light-transmitting conductive material such as tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, and graphene can be used.

Further, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N
b) Metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), etc. ,
It can be formed using one or more of their alloys, or metal nitrides thereof.

Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole and thiophene or a derivative thereof.

Furthermore, since transistors are easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. Preferably, the protection circuit is configured using a nonlinear element.

As described above, by using the transistor described in any of Embodiments 1 to 4, semiconductor devices having various functions can be provided.

(Embodiment 6)
A semiconductor device having an image sensor function that reads information on a target can be manufactured using the transistor described as an example in any of Embodiments 1 to 4.

FIG. 14A shows an example of a semiconductor device having an image sensor function. FIG. 14(A) is an equivalent circuit of the photosensor, and FIG. 14(B) is a cross-sectional view showing a part of the photosensor.

The photodiode 602 has one electrode electrically connected to the photodiode reset signal line 658 and the other electrode electrically connected to the gate of the transistor 640. transistor 640
One of the source and drain is electrically connected to the photosensor reference signal line 672, and the other source and drain is electrically connected to one of the source and drain of the transistor 656. The transistor 656 has its gate electrically connected to the gate signal line 659 and the other of its source and drain to the photosensor output signal line 671.

Note that in the circuit diagrams in this specification, the symbol for a transistor using an oxide semiconductor film is written as "OS" so that it can be clearly identified as a transistor using an oxide semiconductor film. In FIG. 14A, the transistor 640 and the transistor 656 are the same as those in Embodiment 1.
The transistors shown in 4 to 4 can be applied, and are transistors using an oxide semiconductor film.
In this embodiment, an example is shown in which a transistor having the same structure as the transistor 440a described in Embodiment 1 is used.

FIG. 14B shows a photodiode 602 and a transistor 640 in a photosensor.
2, a photodiode 602 and a transistor 640 functioning as a sensor are provided on a substrate 601 (TFT substrate) having an insulating surface. A substrate 613 is provided on the photodiode 602 and the transistor 640 using an adhesive layer 608.

An insulating film 631, an insulating film 632, an interlayer insulating film 633, and an interlayer insulating film 634 are provided over the transistor 640. The photodiode 602 is provided on the interlayer insulating film 633,
Between the electrode layer 641 formed on the interlayer insulating film 633 and the electrode layer 642 provided on the interlayer insulating film 634, a first semiconductor film 606a and a second semiconductor film 60 are arranged in order from the interlayer insulating film 633 side.
6b and a third semiconductor film 606c are stacked.

The electrode layer 641 is electrically connected to a conductive layer 643 formed on the interlayer insulating film 634, and the electrode layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641. The conductive layer 645 is
It is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a semiconductor film having a p-type conductivity type is used as the first semiconductor film 606a, a high-resistance semiconductor film (I-type semiconductor film) is used as the second semiconductor film 606b, and an n-type conductivity type is used as the third semiconductor film 606c. This example illustrates a pin-type photodiode in which semiconductor films having the same structure are stacked.

The first semiconductor film 606a is a p-type semiconductor film, and can be formed of an amorphous silicon film containing an impurity element that imparts p-type conductivity. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing a Group 13 impurity element (for example, boron (B)). Silane (SiH ₄ ) may be used as the semiconductor material gas. Or S
_i2H6 , _SiH2Cl2 , _SiHCl3 , _SiCl4 , _{SiF4 , etc.} may be used. Further, after forming an amorphous silicon film that does not contain an impurity element, an impurity element may be introduced into the amorphous silicon film using a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing the impurity element by ion implantation or the like and then performing heating or the like. In this case, methods for forming the amorphous silicon film include LPCVD method, vapor phase growth method,
Alternatively, a sputtering method or the like may be used. The thickness of the first semiconductor film 606a is 10 nm or more5
It is preferable to form the layer to have a thickness of 0 nm or less.

The second semiconductor film 606b is an I-type semiconductor film (intrinsic semiconductor film) and is formed from an amorphous silicon film. To form the second semiconductor film 606b, an amorphous silicon film is formed by plasma CVD using a semiconductor material gas. Silane (SiH ₄ ) may be used as the semiconductor material gas. Or Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , S
iCl ₄ , SiF _{4 ,} etc. may also be used. The second semiconductor film 606b is formed using the LPCVD method.
It may be performed by a vapor phase growth method, a sputtering method, or the like. The thickness of the second semiconductor film 606b is 2
It is preferable to form the layer to have a thickness of 00 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film, and is formed of an amorphous silicon film containing an impurity element that imparts n-type conductivity. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor material gas containing a Group 15 impurity element (for example, phosphorus (P)). Silane (SiH ₄ ) may be used as the semiconductor material gas. Or _{Si2H6 ,}
SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ or the like may also be used. Further, after forming an amorphous silicon film that does not contain an impurity element, an impurity element may be introduced into the amorphous silicon film using a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing the impurity element by ion implantation or the like and then performing heating or the like. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The third semiconductor film 606c is preferably formed to have a thickness of 20 nm or more and 200 nm or less.

Further, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (semi-amorphous semiconductor). It may be formed using a SAS)) semiconductor.

Microcrystalline semiconductors belong to a metastable state intermediate between amorphous and single crystal, considering Gibbs free energy. That is, it is a semiconductor having a third state that is stable in terms of free energy, has short-range order, and has lattice strain. Columnar or acicular crystals grow in the normal direction to the substrate surface. Microcrystalline silicon, which is a typical example of microcrystalline semiconductors, has a Raman spectrum shifted to a lower wave number than 520 cm ⁻¹ , which is the wavelength of single crystal silicon.
That is, 520 cm ^-1 indicating single crystal silicon and 480 cm -1 indicating amorphous silicon ^.
There is a peak in the Raman spectrum of microcrystalline silicon between 1 and ¹ . Further, in order to terminate dangling bonds, at least 1 atomic % or more of hydrogen or halogen is contained. Furthermore, by incorporating a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, a good microcrystalline semiconductor film with increased stability can be obtained.

This microcrystalline semiconductor film can be formed by a high-frequency plasma CVD method with a frequency of several tens of MHz to several hundred MHz, or a microwave plasma CVD device with a frequency of 1 GHz or more. Typically, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , S
It can be formed by diluting a silicon-containing compound such as _iF4 with hydrogen. Further, in addition to a compound containing silicon (for example, silicon hydride) and hydrogen, a microcrystalline semiconductor film can be formed by diluting it with one or more rare gas elements selected from helium, argon, krypton, and neon. . In these cases, the flow rate ratio of hydrogen to the silicon-containing compound (for example, silicon hydride) is set to 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and more preferably 100 times. Furthermore, carbide gases such as CH ₄ and C ₂ H ₆ , GeH
₄ , germanizing gas such as _GeF4 , _F2, etc. may be mixed.

Furthermore, since the mobility of holes generated by the photoelectric effect is smaller than the mobility of electrons, a pin-type photodiode exhibits better characteristics when the light-receiving surface is on the p-type semiconductor film side. Here, p
The photodiode 602 is viewed from the surface of the substrate 601 on which the in-type photodiode is formed.
Here is an example of converting the light received by the device into an electrical signal. Furthermore, since light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film side serving as the light-receiving surface becomes disturbance light, it is preferable to use a conductive film having a light-shielding property as the electrode layer. Further, the n-type semiconductor film side can also be used as a light-receiving surface.

As the insulating film 632, interlayer insulating film 633, and interlayer insulating film 634, an insulating material is used, and depending on the material, sputtering method, plasma CVD method, SOG method, spin coating, dipping, spray coating, or droplet discharge is used. It can be formed using a method (inkjet method, etc.), a printing method (screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc.

In this embodiment, an aluminum oxide film is used as the insulating film 631. The insulating film 631 can be formed by a sputtering method or a plasma CVD method.

The aluminum oxide film provided as the insulating film 631 over the oxide semiconductor film has a high blocking effect of not allowing both impurities such as hydrogen and water to pass through the film, as well as oxygen.

Therefore, during and after the fabrication process, the aluminum oxide film is exposed to hydrogen and
It functions as a protective film that prevents impurities such as water from entering the oxide semiconductor film and preventing oxygen, which is the main component of the oxide semiconductor, from being released from the oxide semiconductor film.

As the insulating film 632, inorganic insulating materials include a silicon oxide layer, a silicon oxynitride layer,
A single layer or a stack of nitride insulating films such as an aluminum oxide layer, an oxide insulating film such as an aluminum oxynitride layer, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer can be used. can.

The interlayer insulating films 633 and 634 are preferably insulating films that function as a flattening insulating film to reduce surface unevenness. As the interlayer insulating films 633 and 634, heat-resistant organic insulating materials such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic insulating materials, low dielectric constant materials (low-
A single layer or a laminated layer of siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. can be used.

By detecting the light incident on the photodiode 602, information on the object to be detected can be read. Note that a light source such as a backlight can be used when reading information on the object to be detected.

As described above, by using an oxide semiconductor stack including a plurality of oxide semiconductor layers having different energy gaps as a semiconductor layer, it is possible to control the electrical characteristics of a transistor with higher precision, and to adjust the desired electrical characteristics to a transistor. It becomes possible to grant Therefore, by using the transistor, it is possible to provide semiconductor devices that meet various purposes, such as high functionality, high reliability, and low power consumption.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 7)
The transistor shown as an example in any of Embodiments 1 to 4 can be suitably used in a semiconductor device having an integrated circuit in which a plurality of transistors are stacked. In this embodiment, an example of a storage medium (memory element) is shown as an example of a semiconductor device.

The embodiment mode includes a transistor 140 that is a first transistor manufactured over a single crystal semiconductor substrate, and a transistor 162 that is a second transistor manufactured using a semiconductor film above the transistor 140 with an insulating film interposed therebetween. Fabricate a semiconductor device. The transistor described as an example in any of Embodiments 1 to 3 can be suitably used for the transistor 162. In this embodiment, an example is shown in which a transistor having a structure similar to the transistor 440a described in Embodiment 1 is used as the transistor 162.

The semiconductor materials and structures of the stacked transistor 140 and transistor 162 may be the same or different. This embodiment is an example in which transistors having materials and structures suitable for the circuit of a storage medium (memory element) are used.

FIG. 15 shows an example of the configuration of a semiconductor device. FIG. 15A shows a cross section of the semiconductor device, and FIG. 15B shows a plane view of the semiconductor device. Here, FIG. 15(A)
This corresponds to the cross sections along C1-C2 and D1-D2 in (B). Further, FIG. 15C shows an example of a circuit diagram when the above semiconductor device is used as a memory element. The semiconductor device illustrated in FIGS. 15A and 15B includes a transistor 140 using a first semiconductor material in a lower portion, and a transistor 162 using a second semiconductor material in an upper portion. In this embodiment, the first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. As a semiconductor material other than an oxide semiconductor, for example, a compound semiconductor material such as silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide can be used, and it is preferable to use a single crystal semiconductor. Other organic semiconductor materials may also be used. A transistor using such a semiconductor material can easily operate at high speed. On the other hand, transistors using oxide semiconductors can retain charge for a long time due to their characteristics.

The semiconductor device in FIG. 15 will be explained using FIGS. 15(A) to 15(C).

The transistor 140 includes a channel formation region 116 provided in a substrate 185 containing a semiconductor material (for example, silicon, etc.), an impurity region 120 provided to sandwich the channel formation region 116, and a metal compound region in contact with the impurity region 120. 124 and channel forming region 1
16, and a gate electrode 110 provided on the gate insulating film 108.

As the substrate 185 containing a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied. Note that "SOI substrate" generally refers to a substrate having a structure in which a silicon semiconductor film is provided on an insulating surface, but in this specification etc., "SOI substrate" refers to a substrate having a structure in which a silicon semiconductor film is provided on an insulating surface. Also includes the substrate of the structure. In other words, the semiconductor film included in the "SOI substrate" is not limited to a silicon semiconductor film. Furthermore, SOI substrates include those having a structure in which a semiconductor film is provided on an insulating substrate such as a glass substrate with an insulating film interposed therebetween.

The method for manufacturing SOI substrates is to implant oxygen ions into a mirror-polished wafer and then heat it to a high temperature to form an oxide layer at a certain depth from the surface and eliminate defects that occur in the surface layer. For example, a method in which a semiconductor substrate is cleaved using the growth of microvoids formed by hydrogen ion irradiation through heat treatment, a method in which a single crystal semiconductor film is formed on an insulating surface by crystal growth, etc. can be used.

For example, ions are added from one surface of a single crystal semiconductor substrate to form a weakened layer at a certain depth from one surface of the single crystal semiconductor substrate, and a weakened layer is formed on one surface of the single crystal semiconductor substrate or an element. An insulating film is formed on either side of the substrate. With a single crystal semiconductor substrate and an element substrate stacked on top of each other with an insulating film in between, heat treatment is performed to create cracks in the weakened layer and separate the single crystal semiconductor substrate at the weakened layer. A single crystal semiconductor film is formed as a film on an element substrate. An SOI substrate produced using the above method can also be suitably used.

An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 140. Note that in order to achieve high integration, it is preferable that the transistor 140 have a structure in which the transistor 140 does not have a sidewall insulating layer serving as a sidewall, as shown in FIG. On the other hand, if the characteristics of the transistor 140 are important, a sidewall insulating layer serving as a sidewall may be provided on the side surface of the gate electrode 110, and an impurity region 120 including regions with different impurity concentrations may be provided.

The transistor 140 using a single crystal semiconductor substrate can operate at high speed. Therefore, by using the transistor as a read transistor, information can be read at high speed. Two layers of insulating films are formed to cover the transistor 140. As a process before forming the transistor 162 and the capacitor 164, the two layers of the insulating film are subjected to CMP processing to form the planarized insulating film 128 and the insulating film 130, and at the same time expose the upper surface of the gate electrode 110.

The insulating film 128 and the insulating film 130 are typically made of silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, silicon nitride oxide film, aluminum nitride oxide film, etc. An inorganic insulating film can be used. The insulating film 128 and the insulating film 130 can be formed using a plasma CVD method, a sputtering method, or the like.

Further, organic materials such as polyimide, acrylic resin, benzocyclobutene resin, etc. can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) and the like can be used. When using an organic material, the insulating film 128 and the insulating film 130 may be formed by a wet method such as a spin coating method or a printing method.

Note that in the insulating film 130, a silicon oxide film is used as a film in contact with the semiconductor film.

In this embodiment, a silicon oxynitride film with a thickness of 50 nm is formed as the insulating film 128 by a sputtering method, and a silicon oxide film with a thickness of 550 nm is formed as the insulating film 130 with a sputtering method.

A gate electrode layer 148 is formed on the insulating film 130 which has been sufficiently planarized by CMP processing. The gate electrode layer 148 can be formed by forming a conductive layer and then selectively etching the conductive layer.

A gate insulating film 146 is formed on the gate electrode layer 148.

As the gate insulating film 146, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, a nitride oxide film are formed using a plasma CVD method or a sputtering method. An aluminum film, a hafnium oxide film, or a gallium oxide film can be formed.

Oxide semiconductor films having different energy gaps are stacked over the gate insulating film 146. In this embodiment, the gate insulating film 146 is formed by a sputtering method as a stack of oxide semiconductor films.
An In--Sn--Zn-based oxide layer and an In--Ga--Zn based oxide layer are sequentially laminated thereon.

Next, the oxide semiconductor film stack is selectively etched to form an island-shaped oxide semiconductor stack 144.

A source or drain electrode 142a and a source or drain electrode 142b are formed on the oxide semiconductor stack 144.

The conductive layer that can be used for the gate electrode layer 148, the source or drain electrode 142a, and the source or drain electrode 142b can be formed using a PVD method such as a sputtering method.
It can be formed using a CVD method such as a method or a plasma CVD method. Further, as a material for the conductive layer, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements, or the like can be used. Any one of Mn, Mg, Zr, Be, Nd, and Sc, or a combination of two or more of these may be used.

The conductive layer may have a single layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film. Examples of the structure include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked. Note that when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, the source electrode or drain electrode 142a having a tapered shape and the source electrode or drain electrode 142 have a tapered shape.
It has the advantage of being easy to process into b.

Next, an insulating film 150 is formed over the gate electrode layer 148, the gate insulating film 146, and the oxide semiconductor stack 144. In this embodiment, an aluminum oxide film is formed as the insulating film 150.

The aluminum oxide film provided as the insulating film 150 on the oxide semiconductor stack 144 has a blocking effect (blocking effect) that prevents both impurities such as hydrogen and water, and oxygen from passing through the film.
is high.

Therefore, during and after the fabrication process, the aluminum oxide film is exposed to hydrogen and
It functions as a protective film that prevents impurities such as water from entering the oxide semiconductor stack 144 and prevents oxygen, which is a main component of the oxide semiconductor, from being released from the oxide semiconductor stack 144.

Further, a separate insulating film may be formed by stacking on the insulating film 150.

As the insulating film, silicon oxide film,
A silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a gallium oxide film can be used.

An electrode layer 153 is formed on the insulating film 150 in a region overlapping with the source or drain electrode 142a.

Next, an insulating film 152 is formed over the transistor 162 and the electrode layer 153. Insulating film 15
2 can be formed using a sputtering method, a CVD method, or the like. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, or aluminum oxide. Furthermore, organic materials such as polyimide, acrylic, and benzocyclobutene resins can be used, and wet methods such as coating methods, printing methods, and inkjet methods can be used for the organic materials.

Next, openings reaching the source electrode or drain electrode 142b are formed in the gate insulating film 146, the insulating film 150, and the insulating film 152. The opening is formed by selective etching using a mask or the like.

Thereafter, a wiring 156 in contact with the source or drain electrode 142b is formed in the opening. Note that FIG. 15 does not show a connection location between the source electrode or drain electrode 142b and the wiring 156.

The wiring 156 can be formed using a PVD method such as a sputtering method, or a carbon dioxide method such as a plasma CVD method.
It is formed by forming a conductive layer using a VD method and then etching the conductive layer. Further, as a material for the conductive layer, an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements, or the like can be used. Mn, Mg, Z
Any one of r, Be, Nd, and Sc, or a combination of these materials may be used. The details are the same as those of the source electrode or drain electrode 142a.

Through the above steps, the transistor 162 and the capacitor 164 are formed. In this embodiment,
The transistor 162 is a transistor including an oxide semiconductor stack 144 including at least two oxide semiconductor layers with different energy gaps. By using the oxide semiconductor stack 144 including a plurality of oxide semiconductor layers having different energy gaps as semiconductor layers, the electrical characteristics of the transistor 162 can be controlled with more precision, and desired electrical characteristics can be imparted to the transistor 162. It becomes possible to grant. Further, in this embodiment, the oxide semiconductor stack 144 is highly purified to be an oxide semiconductor stack containing excess oxygen to compensate for oxygen vacancies. Therefore, the transistor 162 has a reduced off-state current, suppresses variations in electrical characteristics, and is electrically stable. The capacitive element 164 includes a source or drain electrode 142a, an insulating film 150, and an electrode layer 153.

If a capacitance is not required, a configuration in which the capacitive element 164 is not provided is also possible.

FIG. 15C shows an example of a circuit diagram when the above semiconductor device is used as a memory element. In FIG. 15C, one of the source electrode and the drain electrode of the transistor 162, one of the electrodes of the capacitor 164, and the gate electrode of the transistor 140 are electrically connected. Further, a first line (also called a source line) and the source electrode of the transistor 140 are electrically connected, and a second line (also called a bit line) and a drain electrode of the transistor 140 are electrically connected. are electrically connected. Also,
The third wiring (3rd Line: also referred to as a first signal line) and the other of the source electrode or drain electrode of the transistor 162 are electrically connected, and the fourth wiring (4th Line)
: also referred to as a second signal line) and the gate electrode of the transistor 162 are electrically connected. Then, a fifth line (also called a word line) and a capacitive element 16
The other electrode of No. 4 is electrically connected.

The transistor 162 using an oxide semiconductor has an extremely small off-state current, so by turning off the transistor 162, one of the source electrode or the drain electrode of the transistor 162 and the capacitor 164 are connected. one of the electrodes and the transistor 140
It is possible to maintain the potential of a node electrically connected to the gate electrode (hereinafter referred to as node FG) for an extremely long time. By having the capacitive element 164, it becomes easy to hold the charge applied to the node FG, and it becomes easy to read out the held information.

When storing information in the semiconductor device (writing), first, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Here, it is assumed that either of charges giving two different potential levels (hereinafter referred to as a low level charge or a high level charge) is provided. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off, so that the node FG becomes a floating state, so that a predetermined charge is held in the node FG. The state remains as it is. As described above, by accumulating and holding a predetermined amount of charge in the node FG, information can be stored in the memory cell.

Since the off-state current of transistor 162 is controlled to be extremely small, the charge supplied to node FG is retained for a long time. Therefore, refresh operations are not required or the frequency of refresh operations can be made extremely low, and power consumption can be sufficiently reduced. Furthermore, even when there is no power supply, it is possible to retain stored contents for a long period of time.

When reading out stored information (reading), when a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (read potential) is applied to the fifth wiring, the data is held at the node FG. Depending on the amount of charge applied, transistor 140 assumes different states. Generally, transistor 1
40 is an n-channel type, the apparent threshold value V th_H of the transistor 140 when a high level charge is held at the node FG is the apparent threshold value V _{th_H} of the transistor 140 when a low level charge is held at the node FG. This is because it becomes lower than the threshold value V _{th_L} . Here, the apparent threshold value refers to the potential of the fifth wiring necessary to turn on the transistor 140. Therefore, the potential of the fifth wiring is V _th
By setting the potential V ₀ between _{_H} and V _{th_L} , the charge held in the node FG can be determined. For example, when a high-level charge is applied during writing, the transistor 140 becomes "on" when the potential of the fifth wiring becomes V ₀ (>V _{th_H} ). When a low level charge is applied, the potential of the fifth wiring becomes V ₀ (<V _{th
_L} ), the transistor 140 remains in the "off state". Therefore, the potential of the fifth wiring is controlled to read out the on state or off state of the transistor 140 (second
The stored information can be read out by reading out the potential of the wiring.

Furthermore, when rewriting the stored information, a new potential is supplied to the node FG that has held a predetermined amount of charge due to the above writing, thereby causing the node FG to hold the charge related to the new information. Specifically, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring (potential related to new information) is supplied to the node FG, and a predetermined amount of charge is accumulated in the node FG. Thereafter, by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned off, the transistor 162 is turned off, so that the node FG retains charges related to new information. That is, by performing the same operation as the first write (second write) with a predetermined amount of charge held in the node FG by the first write, it is possible to overwrite the stored information. It is.

The transistor 162 described in this embodiment is a transistor that has an oxide semiconductor stack including at least two oxide semiconductor layers with different energy gaps, and whose off-state current is controlled to be sufficiently low. By using such a transistor, a semiconductor device that can retain memory contents for an extremely long period of time can be obtained.

As described above, by using an oxide semiconductor stack including a plurality of oxide semiconductor layers having different energy gaps, the electrical characteristics of a transistor can be controlled with more precision, and desired electrical characteristics can be imparted to the transistor. becomes possible. Therefore, it is possible to provide semiconductor devices suitable for various purposes such as high functionality, high reliability, and low power consumption.

As described above, the structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

(Embodiment 8)
The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also called televisions or television receivers), computer monitors, cameras such as digital cameras and digital video cameras, digital photo frames, and mobile phones (mobile phones, mobile phones, etc.). (also referred to as devices), portable game machines, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. An example of an electronic device including the semiconductor device described in the above embodiment will be described. By including the semiconductor device described in the above embodiments, it is possible to provide electronic equipment that is provided with qualities suitable for various purposes, such as high functionality, high reliability, and low power consumption.

FIG. 16(A) shows a table 9000 having a display section. Table 9000 is
A display portion 9003 is incorporated into the housing 9001. A semiconductor device manufactured using one embodiment of the present invention can be used for the display portion 9003, and images can be displayed using the display portion 9003. Note that a configuration in which the housing 9001 is supported by four legs 9002 is shown. The housing 9001 also includes a power cord 9005 for power supply.

The display section 9003 has a touch input function, and by touching a display button 9004 displayed on the display section 9003 of the table 9000 with your finger, you can operate the screen, input information, and perform other operations. It may also be a control device that controls other home appliances through screen operations by enabling communication with or control of home appliances. For example, if the semiconductor device having the image sensor function described in Embodiment Mode 6 is used, the display portion 9003 can have a touch input function.

Furthermore, the screen of the display portion 9003 can be stood perpendicular to the floor by means of a hinge provided in the housing 9001, allowing the device to be used as a television device. In a small room, installing a large-screen television device will reduce free space, but if the table has a built-in display unit, the space in the room can be used effectively.

FIG. 16(B) shows a television device 9100. A television device 9100 includes a display portion 9103 built into a housing 9101. A semiconductor device manufactured using one embodiment of the present invention can be used for the display portion 9103, and images can be displayed using the display portion 9103. Note that a configuration in which the housing 9101 is supported by a stand 9105 is shown here.

The television device 9100 can be operated using an operation switch included in the housing 9101 or a separate remote controller 9110. Using operation keys 9109 provided on the remote control device 9110, the channel and volume can be controlled, and the video displayed on the display section 9103 can be controlled. Further, the remote control device 9110 may be provided with a display section 9107 that displays information output from the remote control device 9110.

A television device 9100 shown in FIG. 16(B) includes a receiver, a modem, and the like. The television device 9100 can receive general television broadcasts using a receiver, and can also receive one-way (sender to receiver) or two-way communication by connecting to a wired or wireless communication network via a modem. (between sender and receiver, or between receivers, etc.)
It is also possible to perform information communication.

By applying the semiconductor device described in any of Embodiments 1 to 7 to the display portion 9103, a television device with higher performance and higher reliability can be obtained.

FIG. 16C shows a computer, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like. A computer displays a semiconductor device manufactured using one embodiment of the present invention in its display portion 9203.
It is produced by using it.

By applying the semiconductor device described in any of Embodiments 1 to 7 to the display portion 9203, a computer with higher performance and higher reliability can be obtained.

FIG. 16(D) shows an example of a mobile phone. The mobile phone 9500 has a housing 9501
In addition to a display portion 9502 built into the , the device is equipped with operation buttons 9503, external connection ports 9504, speakers 9505, microphones 9506, operation buttons 9507, and the like. Embodiment 1
By applying the semiconductor device shown in any one of 7 to 7 to the display portion 9502, a mobile phone with higher performance and higher reliability can be obtained.

In the mobile phone 9500 shown in FIG. 16D, operations such as inputting information, making a call, or composing an email can be performed by touching the display portion 9502 with a finger or the like.

The screen of the display section 9502 mainly has three modes. The first is a display mode that mainly displays images, and the second is an input mode that mainly inputs information such as characters. The third mode is a mixture of two modes: display mode and input mode.

For example, when making a phone call or composing an e-mail, the display unit 9502 may be set to an input mode mainly for inputting characters, and the user may input the characters displayed on the screen. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display section 9502.

Furthermore, by providing a detection device having a sensor for detecting inclination such as a gyro or an acceleration sensor inside the mobile phone 9500, the orientation of the mobile phone 9500 (vertical or horizontal) can be determined and the screen of the display unit 9502 can be displayed. The display can be changed automatically.

Further, switching of the screen mode is performed by touching the display portion 9502 or operating an operation button 9503 on the housing 9501. Further, it is also possible to switch depending on the type of image displayed on the display section 9502. For example, if the image signal to be displayed on the display section is video data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

In addition, in the input mode, a signal detected by the optical sensor of the display section 9502 is detected, and if there is no input by touch operation on the display section 9502 for a certain period of time, the screen mode is switched from the input mode to the display mode. May be controlled.

Further, the display portion 9502 can also function as an image sensor. For example, by touching the display portion 9502 with a palm or fingers and capturing an image of a palm print, fingerprint, or the like, personal authentication can be performed. Furthermore, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used in the display section, it is also possible to image finger veins, palm veins, and the like.

As described above, the structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

In this example, a second oxide semiconductor layer smaller than the energy gap of the first oxide semiconductor layer is formed over the first oxide semiconductor layer, and a second oxide semiconductor layer is further formed over the second oxide semiconductor layer. Samples (sample 1A, sample 1B, sample 2A, and sample 2B) in which the oxide semiconductor layer No. 3 was formed were prepared, and the cross-sectional structures of sample 1A, sample 1B, sample 2A, and sample 2B were observed. In addition, the ionization potentials of Sample 1A and Sample 2A were measured, and energy band diagrams were calculated based on the results. In this specification, the value of the ionization potential is the sum of the band gap and the electron affinity, and the value of the band gap is the value obtained by measuring a single film of the material with an ellipsometry.

As sample 1A, an In-Ga-Zn-based oxide film with a thickness of 5 nm was formed as a first oxide semiconductor layer 1001 on a quartz substrate serving as a substrate 1000, and an In-Ga-Zn-based oxide film with a thickness of 5 nm was formed as a second oxide semiconductor layer 1002.
An In--Sn--Zn-based oxide film with a thickness of 5 nm and an In--Ga--Zn-based oxide film with a thickness of 5 nm were stacked as the third oxide semiconductor layer 1003. Each film was formed using a sputtering method at a substrate temperature of 300° C. and in an oxygen atmosphere (oxygen 100%). The target is an oxide target with In:Ga:Zn=1:1:1 [atomic ratio].
- Deposit a Zn-based oxide film. In addition, the In-Sn-Zn based oxide film is In:Sn:Zn
An oxide target with an atomic ratio of =2:1:3 is used.

Sample 1B was obtained by subjecting an oxide semiconductor stack formed in the same manner as sample 1A to heat treatment to produce an oxide semiconductor stack having a mixed region. The heat treatment was performed at a temperature of 650° C. in a nitrogen atmosphere for 1 hour, and then at a temperature of 650° C. in an oxygen atmosphere for 1 hour.

As sample 2A, an In-Ga-Zn-based oxide film with a thickness of 5 nm was formed as a first oxide semiconductor layer 1001 on a quartz substrate serving as a substrate 1000, and an In-Ga-Zn-based oxide film with a thickness of 5 nm was formed as a second oxide semiconductor layer 1002.
nm thick In-Zn-based oxide film, and a 5 nm thick In-Zn-based oxide film as the third oxide semiconductor layer 1003.
Ga—Zn-based oxide films were deposited in layers. Each film was formed using a sputtering method at a substrate temperature of 300° C. and in an oxygen atmosphere (oxygen 100%). The target is I
Using an oxide target with n:Ga:Zn=1:1:1 [atomic ratio], In-Ga-Zn
A system oxide film is formed. Further, for the In--Zn-based oxide film, an oxide target with In:Zn=2:1 [atomic ratio] is used.

Sample 2B was obtained by subjecting an oxide semiconductor stack formed in the same manner as sample 2A to heat treatment to produce an oxide semiconductor stack having a mixed region. The heat treatment was performed at a temperature of 650° C. in a nitrogen atmosphere for 1 hour, and then at a temperature of 650° C. in an oxygen atmosphere for 1 hour.

The end faces of Sample 1A, Sample 1B, Sample 2A, and Sample 2B were cut out, and an acceleration voltage of 3
00 kV, and the cross sections of Sample 1A, Sample 1B, Sample 2A, and Sample 2B were observed. Figure 1
Sample 1A in Figure 7(B), Sample 1B in Figure 17(C), Sample 2A in Figure 18(B), Figure 18(C)
shows a TEM image of sample 2B. Note that schematic diagrams of sample 1A and sample 2A are shown in FIG. 17(A) and FIG. 18(A). In FIGS. 17A and 18A, the interface between stacked oxide semiconductor layers is illustrated by a dotted line, but the interface is schematically illustrated.

The TEM images of Sample 1A and Sample 1B shown in FIG. , a 5-nm-thick In-Sn-Zn-based oxide film as the second oxide semiconductor layer 1002, and a 5-nm-thick second In-Ga-Zn-based oxide film as the third oxide semiconductor layer 1003. This is an oxide semiconductor stack formed by stacking films. In the TEM image of sample 1A in FIG. 17(B), an interface can be seen between the stacked oxide semiconductor layers. On the other hand, sample 1B was subjected to heat treatment after forming the oxide semiconductor stack.
As shown in FIG. 17C, in the TEM image of FIG. 17C, no clear interface can be seen between the laminated oxide semiconductor layers, resulting in a mixed region.

The TEM images of Sample 2A and Sample 2B shown in FIG. , the second oxide semiconductor layer 1002 is an In-Zn-based oxide film with a thickness of 5 nm, and the third oxide semiconductor layer 1003 is a second In-Ga-Zn-based oxide film with a thickness of 5 nm. This is a stacked oxide semiconductor stack. In the TEM image of sample 2A in FIG. 18(B), an interface can be seen between the stacked oxide semiconductor layers. On the other hand, the TE of sample 2B was subjected to heat treatment after forming the oxide semiconductor stack.
In the M image, as shown in FIG. 18C, no clear interface can be seen between the laminated oxide semiconductor layers, which is a mixed region.

In addition, as shown in FIGS. 17(B)(C) and 18(B)(C), sample 1A, sample 1B,
Sample 2A and Sample 2B are the first In-Ga-Z which is the first oxide semiconductor layer 1001.
An n-based oxide film, an In-Sn-Zn-based oxide film serving as the second oxide semiconductor layer 1002, and an I
n-Zn-based oxide film and second In-Ga-Z which is the third oxide semiconductor layer 1003
The n-based oxide film contains crystals and is a crystalline oxide semiconductor with c-axis orientation (CAAC-
It can be confirmed that it is an OS) film. Further, the first I, which is the first oxide semiconductor layer 1001,
The n-Ga-Zn-based oxide film also includes an amorphous structure.

Note that in the oxide semiconductor stack, the crystal state of each oxide semiconductor layer is not particularly limited; all the oxide semiconductor layers may have a crystal structure, or all the oxide semiconductor layers may have an amorphous structure. An oxide semiconductor layer having a crystalline structure and an oxide semiconductor layer having an amorphous structure may coexist.

In addition, sample 1A was obtained by laminating films under the same film forming conditions using a single crystal silicon substrate as the substrate.
and ultraviolet photoelectron spectroscopy (UPS: Ult) while sputtering from the surface of sample 2A.
19 and 21 show the results of measuring the ionization potential using Raviolet Photoelectron Spectroscopy).

In FIGS. 19 and 21, the horizontal axis represents sputtering time from the sample surface, and the vertical axis represents ionization potential. Note that the In-Ga-Zn-based oxide film and the In-Sn
- The boundaries of the samples are displayed on the assumption that the sputtering rate of the Zn-based oxide film and the sputtering rates of the In--Ga--Zn-based oxide film and the In--Zn-based oxide film are equal.

From FIG. 19, it can be seen that the ionization potential decreases in the In--Sn--Zn-based oxide film sandwiched between the In--Ga--Zn-based oxide films. Note that the ionization potential represents the energy difference from the vacuum level to the valence band.

The conduction band energy was calculated by subtracting the band gap measured by ellipsometry from the ionization potential value, and the band structure of this laminated film was created. However, the band gaps of the In-Ga-Zn-based oxide film and the In-Sn-Zn-based oxide film are 3.2 eV and 2.8 eV, respectively.
It was set as eV. The result is shown in FIG. It can be seen from FIG. 20 that a buried channel is formed as shown in the energy band diagram shown in FIG. 4(C).

It can be seen from FIG. 21 that the ionization potential decreases in the In--Zn-based oxide film sandwiched between the In--Ga--Zn-based oxide films. Note that the ionization potential represents the energy difference from the vacuum level to the valence band.

The conduction band energy was calculated by subtracting the band gap measured by ellipsometry from the ionization potential value, and the band structure of this laminated film was created. However, the band gaps of the In--Ga--Zn-based oxide film and the In--Zn-based oxide film were set to 3.2 eV and 2.6 eV, respectively. The result is shown in FIG. It can be seen from FIG. 22 that a buried channel is formed as shown in the energy band diagram shown in FIG. 4(C).

In this example, the first oxide semiconductor layer and the third oxide semiconductor layer are made of In-Ga-
A Zn-based oxide film is used as the second oxide semiconductor layer, which has a smaller ionization potential than the first oxide semiconductor layer and the third oxide semiconductor layer, and has a small energy gap. It was confirmed that a stack using a -Zn-based oxide film or an In-Zn-based oxide film can be represented by the energy band diagram shown in FIG. 20, FIG. 22, or FIG. 4(C). The combination of materials for the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer is not particularly limited, and the energy levels shown in FIG. 20, FIG. 22, or FIG. The practitioner may select and combine materials as appropriate in consideration of the energy gap of the materials used so as to form a band diagram.

In this example, a transistor (example transistor) having an oxide semiconductor stack formed of a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, which is illustrated as transistors 440a, 440b, and 430 in Embodiment 1, 1 to 4, and comparative example transistors 1 to 4)
We calculated the characteristics of

The calculations in this example were performed using the simulation software TCAD (Technol) manufactured by Synopsys.
ogy Computer-Aided Design).

As Example Transistor 1, Example Transistor 2, Comparative Example Transistor 1, and Comparative Example Transistor 2, gates with a thickness of 100 nm were provided on the gate electrode layer as shown in transistors 440a and 440b in Embodiment 1. An oxide semiconductor stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially stacked on an insulating film, and a source electrode layer and a drain electrode layer provided on the oxide semiconductor stack. A transistor with a bottom gate structure (channel etch type) was used.

As Example Transistor 3, Example Transistor 4, Comparative Example Transistor 3, and Comparative Example Transistor 4, a gate insulating film with a thickness of 100 nm provided on the gate electrode layer as shown in transistor 430 in Embodiment 1 was used. a source electrode layer and a drain electrode layer; and an oxide semiconductor stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially stacked on the source electrode layer and the drain electrode layer. A transistor with a bottom gate structure was used.

In Example Transistors 1 to 4 and Comparative Example Transistors 1 to 4, calculations were made assuming that the channel length (L) and channel width (W) were both 10 μm, and the drain voltage (Vd) was 1V.

Further, the structure of the oxide semiconductor stack included in Example Transistors 1 to 4 includes a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps, and the first oxide semiconductor layer is Example transistor 1 and example transistor 3 each have an In-Sn-Zn-based oxide film with a film thickness of 5 nm, an In-Ga-Zn-based oxide film with a film thickness of 5 nm as the second oxide semiconductor layer, and the first Example transistor 2 and example having an In-Ga-Zn-based oxide film with a film thickness of 5 nm as the oxide semiconductor layer, and an In-Sn-Zn-based oxide film with a film thickness of 5 nm as the second oxide semiconductor layer. It was set as transistor 4.

On the other hand, the configuration of the oxide semiconductor stack included in Comparative Example Transistors 1 to 4, which are comparative examples, is as follows:
a first oxide semiconductor layer and a second oxide semiconductor layer having the same energy gap;
The second oxide semiconductor layer has an In-Ga-Zn oxide film with a thickness of 5 nm, and the second oxide semiconductor layer has an In-Ga-Zn oxide film with a thickness of 5 nm. Comparative Example Transistor 1 and Comparative Example Transistor 3 (consisting of a single layer of an In-Ga-Zn-based oxide film), and a 5-nm-thick In-Sn-Zn-based oxide film as the first oxide semiconductor layer; Comparative Example Transistor 2 and Comparative Example Transistor 4 each had an In-Sn-Zn-based oxide film with a film thickness of 5 nm as the oxide semiconductor layer of Comparative Example Transistor 2 (that is, the oxide semiconductor layer was a single layer of an ITGO film).

In-Ga- contained in Example transistors 1 to 4 and Comparative example transistors 1 to 4
The Zn-based oxide film has a band gap of 3.15 eV and a carrier lifetime of 1 nsec.
, the bulk mobility is 10 cm ² /Vs, the electron affinity is 4.6 eV, and In-Sn
-Zn-based oxide film has a band gap of 2.8 eV and a carrier lifetime of 1 nsec.
, the bulk mobility was calculated as 35 cm ² /Vs, and the electron affinity was calculated as 4.6 eV.

The off-state current values of Example Transistor 1, Example Transistor 2, Comparative Example Transistor 1, and Comparative Example Transistor 2 obtained by calculation are shown in FIGS. 23A and 23B. Off-state current values of Comparative Example Transistor 3 and Comparative Example Transistor 4 are shown in FIGS. 25A and 25B, respectively. Note that FIGS. 23(B) and 25(B) show cases where the drain current is 1.0×10 −35 A to 1.0×10 ⁻³⁵ A in FIG. 23(A) or FIG. 25(A).
This is a graph showing an enlarged range of 0×10 ⁻²⁵ A. Figure 23(A)(B) and Figure 25
In (A) and (B), the vertical axis shows the drain current (A), and the horizontal axis shows the gate voltage (V).

Further, the field effect mobilities of Example Transistor 1, Example Transistor 2, Comparative Example Transistor 1, and Comparative Example Transistor 2 obtained by calculation are shown in FIG. FIG. 26 shows the field effect mobilities of transistor No. 3 and comparative example transistor 4, respectively. In FIGS. 24 and 26, the vertical axis represents field effect mobility (cm ² /Vs), and the horizontal axis represents gate voltage (V).

Examples transistor 1, example transistor 2, comparative example transistor 1, and comparative example transistor 2, which are transistors with the same structure, have different off-state current values as shown in FIGS. 23(A) and 23(B), and as shown in FIG. 24. The field effect mobilities also showed different values.

Similarly, example transistor 3, example transistor 4, which are transistors with the same structure,
Comparative Example Transistor 3 and Comparative Example Transistor 4 had different off-state current values as shown in FIGS. 25A and 25B, and different field effect mobilities as shown in FIG. 26.

In particular, in this example, the field effect mobilities shown in FIGS. 24 and 26 significantly differed depending on the oxide semiconductor material used in the oxide semiconductor stack and the stack order.

From the above results, the electrical characteristics (field effect mobility and off-current characteristics in this example) of the transistor can be varied by stacking oxide semiconductor layers with different bandgaps even though they have the same structure. It has been shown that it can be changed.

Therefore, by using an oxide semiconductor stack, the electrical characteristics of the transistor can be controlled with more precision, and desired electrical characteristics can be imparted to the transistor.

101 Oxide semiconductor layer 102 Oxide semiconductor layer 103 Oxide semiconductor layer 105 Mixed region 106 Element isolation insulating layer 108 Gate insulating film 110 Gate electrode 111 Oxygen excess region 112 Oxygen excess region 113 Oxygen excess region 116 Channel formation region 120 Impurity region 121a Low resistance region 121b Low resistance region 121c Channel formation region 122a Low resistance region 122b Low resistance region 122c Channel formation region 124 Metal compound region 128 Insulating film 130 Insulating film 140 Transistor 142a Drain electrode 142b Drain electrode 144 Oxide semiconductor stack 146 Gate insulating film 148 Gate electrode layer 150 Insulating film 152 Insulating film 153 Electrode layer 156 Wiring 162 Transistor 164 Capacitor 185 Substrate 191 Oxide semiconductor film 192 Oxide semiconductor film 340 Transistor 343 Transistor 380a Transistor 380b Transistor 380c Transistor 383 Transistor 400 Substrate 401 Gate electrode layer 402 Gate insulating film 403 Oxide semiconductor stack 404a Source electrode layer 404b Drain electrode layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating film 409 Insulating film 410 Transistor 413 Transistor 416 Planarizing insulating film 418 Transistor 420 Transistor 421 Dopant 427 Insulating film 430 Transistor 431 Oxygen 433 Transistor 438 Transistor 440a Transistor 440b Transistor 440c Transistor 440d Transistor 443a Transistor 443b Transistor 449 Transistor 465a Wiring layer 465b Wiring layer 480 Transistor 483 Transistor 493 Laminated layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 60 8 Adhesive layer 613 Substrate 631 Insulating film 632 Insulating film 633 Interlayer insulating film 634 Interlayer insulating film 640 Transistor 641 Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photo Sensor reference signal line 1000 Substrate 1001 Oxide semiconductor layer 1002 Oxide semiconductor layer 1003 Oxide semiconductor layer 4001 Substrate 4002 Pixel portion 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal Element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 Anisotropic conductive film 4020 Insulating film 4021 Insulating film 4023 Insulating film 4030 Electrode layer 4031 Electrode layer 4032 Insulating film 4033 Insulating film 4510 Partition 4511 Electroluminescent layer 4513 Light emitting element 4514 Filling material 9000 Table 9001 Housing 9002 Legs 9003 Display section 9004 Display button 9005 Power cord 9100 Television device 9101 Housing 9103 Display portion 9105 Stand 9107 Display portion 9109 Operation keys 9110 Remote control unit 9201 Main unit 9202 Housing 9203 Display portion 9204 Keyboard 9205 External connection port 9206 Pointing device 9500 Mobile phone 9501 box Body 9502 Display section 9503 Operation button 9504 External connection port 9505 Speaker 9506 Microphone 9507 Operation button

Claims (4)

a first insulating film having a region functioning as a gate insulating layer of a transistor;
a first oxide semiconductor layer having a region in contact with the first insulating film;
a second oxide semiconductor layer having a region in contact with the first oxide semiconductor layer and overlapping with the first insulating film via the first oxide semiconductor layer;
A semiconductor device comprising: an oxide insulating film having a region in contact with the second oxide semiconductor layer,
The first oxide semiconductor layer includes In, Sn, and Zn,
The second oxide semiconductor layer includes In, Ga, and Zn,
In the semiconductor device, the atomic ratio of In to Sn in the first oxide semiconductor layer is larger than the atomic ratio of In to Ga in the second oxide semiconductor layer. a first insulating film having a region functioning as a gate insulating layer of a transistor;
a first oxide semiconductor layer having a region in contact with the first insulating film;
a second oxide semiconductor layer having a region in contact with the first oxide semiconductor layer and overlapping with the first insulating film via the first oxide semiconductor layer;
A semiconductor device comprising: an oxide insulating film having a region in contact with the second oxide semiconductor layer,
The first oxide semiconductor layer includes In, Sn, and Zn,
The second oxide semiconductor layer includes In, Ga, and Zn,
The atomic ratio of In to Sn in the first oxide semiconductor layer is greater than the atomic ratio of In to Ga in the second oxide semiconductor layer,
A semiconductor device, wherein the atomic ratio of Zn to In in the first oxide semiconductor layer is different from the atomic ratio of Zn to In in the second oxide semiconductor layer. In claim 1 or 2,
In the semiconductor device, the second oxide semiconductor layer has a crystal part oriented along the c-axis. In any one of claims 1 to 3,
A semiconductor device, wherein the first oxide semiconductor layer has crystallinity different from that of the second oxide semiconductor layer.

Images