JP4981283B2 - Thin film transistor using amorphous oxide layer - Google Patents

Thin film transistor using amorphous oxide layer Download PDF

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JP4981283B2
JP4981283B2 JP2005258270A JP2005258270A JP4981283B2 JP 4981283 B2 JP4981283 B2 JP 4981283B2 JP 2005258270 A JP2005258270 A JP 2005258270A JP 2005258270 A JP2005258270 A JP 2005258270A JP 4981283 B2 JP4981283 B2 JP 4981283B2
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JP2007073701A5 (en
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政史 佐野
勝美 安部
享 林
久人 薮田
文徳 遠藤
日出也 雲見
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キヤノン株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Description

  The present invention relates to a thin film transistor using an amorphous oxide insulating layer as a gate insulating film or having an amorphous oxide resistance layer.

  In recent years, development of a thin film transistor (TFT) using a transparent conductive oxide polycrystalline thin film containing ZnO as a main component in a channel layer has been actively performed (Patent Document 1).

  Since the thin film can be formed at a low temperature and is transparent to visible light, it is said that a flexible transparent TFT can be formed on a substrate such as a plastic plate or a film.

Non-Patent Document 1 discloses a technique in which a transparent amorphous oxide semiconductor film (a-IGZO) made of indium, gallium, zinc, and oxygen is used for a TFT channel layer. Furthermore, it is shown that it is possible to form a flexible and transparent TFT exhibiting good field effect mobility 6-9 cm 2 V −1 s −1 on a substrate such as a polyethylene terephthalate (PET) film at room temperature. Yes.
JP 2002-76356 A K. Nomura et.al, Nature, Vol. 432 (2004-11) (English), p.488-492

  In a conductive transparent oxide containing ZnO as a main component, oxygen defects are likely to occur, a large number of carrier electrons are generated, and it is difficult to reduce the electrical conductivity. For this reason, even when no gate voltage is applied, a large current flows between the source terminal and the drain terminal, and it is difficult to realize a normally-off operation of the TFT. It is also difficult to increase the on / off ratio of the transistor. The main cause is generation of defects at the interface between the conductive transparent oxide channel layer and the gate insulating film. In addition, examples of the gate insulating film that can be formed at room temperature include amorphous SiNx, SiOx, etc. in plasma CVD, but suitable materials for an amorphous insulating film that can be formed by a sputtering method that can be formed in a large area at a relatively low cost. Is not found.

  Further, when a transparent amorphous oxide semiconductor film (a-IGZO) made of indium, gallium, zinc, and oxygen as described in Non-Patent Document 1 is used for the channel layer of the TFT, there are the following problems. That is, there has been a demand for improvement in stability and reliability such as generation of hysteresis and change with time in the electrical characteristics of the TFT. The main cause is the generation of defects at the interface between the a-IGZO channel layer and the gate insulating film, as in the case of the conductive transparent oxide mainly composed of ZnO.

When a high dielectric constant insulating film such as Al 2 O 3 , Y 2 O 3 , HfO 2 or the like is formed at a low temperature of 300 ° C. or lower and further at room temperature, the high dielectric constant insulating film becomes a polycrystal and its crystal orientation and It is difficult to make the polycrystalline grain size uniform and improve the stability and reliability. In addition, the polycrystalline structure has a portion where the grain size changes in the film thickness direction in the initial stage, and tends to be non-uniform. The surface of the insulating film has a surface morphology corresponding to the grain size, and there is a problem that the interface between the channel layer and the gate insulating film or the interface between the gate insulating film and the gate electrode metal is not flat.

  Therefore, an object of the present invention is to provide a thin film transistor using an amorphous insulating layer having a good interface or a high resistance layer.

  As a result of intensive research and development on the growth conditions of the In—Ga—Zn—O film and related films, the present inventors have obtained the knowledge that the above problems can be solved by using an amorphous oxide film. .

Specifically, In—M—Zn (M is at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge) is the main constituent element, and the resistance value is 10 11 Ω · An amorphous oxide film having a thickness of cm or more is used as the gate insulating film. Alternatively, the resistor layer is used between the gate insulating film and the semiconductor layer.

In the present invention, the resistance layer is a layer mainly having a function as a carrier transport layer.
By using such a specific amorphous oxide film, it is possible to stably produce a thin film TFT having good interface characteristics.

  The present invention will be specifically described below.

The present invention is a thin film transistor having at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The gate insulating film includes an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge; The resistance value is 10 11 Ω · cm or more,
The semiconductor layer has an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge;
The composition ratio of at least one of Ga, Al, Fe, Sn, and Mg contained in the gate insulating film is higher than the composition ratio of at least one of Ga, Al, Fe, Sn, and Mg contained in the semiconductor layer. big,
The thin film transistor is characterized in that a resistance value of the semiconductor layer is less than 10 10 Ω · cm, and a band gap of the semiconductor layer is smaller than a band gap of the gate insulating film .

Further, the present invention, the semiconductor layer has a In, and Zn, and O, Ga, Al, Fe, Sn, Mg, Ca, Si, and including an amorphous oxide and at least one of Ge ,
Wherein the resistance value of the semiconductor layer is Ri der less than 10 10 Ω · cm, a thin film transistor according to (1) the band gap of the semiconductor layer being less than the band gap of the gate insulating film.

The present invention is a thin film transistor having at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
Having a resistance layer between the semiconductor layer and the gate insulating film;
The resistance layer includes an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge,
The semiconductor layer has an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge;
The semiconductor layer has a resistance value of less than 10 10 Ω · cm,
A thin film transistor characterized in that the resistance value of the resistance layer is 10 11 Ω · cm or more, the film thickness is 1 nm or more and 200 nm or less, and the band gap of the resistance layer is smaller than the band gap of the gate insulating film. is there.

  In the thin film transistor according to (3), the semiconductor layer mainly has a function as a carrier generation layer, and the resistance layer mainly has a function as a carrier transport layer. is there.

Further, the present invention, the semiconductor layer has a In, and Zn, and O, Ga, Al, Fe, Sn, Mg, Ca, Si, and at least one of Ge, the amorphous oxide containing ,
The thin film transistor according to (3) above, wherein the semiconductor layer has a resistance value of less than 10 10 Ω · cm.

  ADVANTAGE OF THE INVENTION According to this invention, the amorphous oxide insulating film used suitably for the gate insulating film of TFT can be provided. In addition, a thin film transistor using an amorphous insulating layer or a high resistance layer having a favorable interface can be provided.

(1) First, a thin film transistor having at least a substrate, a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the gate insulating film includes In, Zn, and O In addition, a thin film transistor having an amorphous oxide insulating film that includes at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge and has a resistance value of 10 11 Ω · cm or more will be described.

A gate insulating film used for a thin film transistor is required to have a high relative dielectric constant, high insulating properties, and smoothness. This is because, as is well known, when used as a gate insulating layer, it acts as a capacitor, and its electric capacity is proportional to the relative dielectric constant and inversely proportional to the film thickness. That is, the higher the resistance value, the better. However, in practice, the resistance value is preferably 10 11 Ω · cm or more.

  In the thin film transistor (TFT), if there is a defect at the interface between the gate insulating film and the channel layer thin film, the electron mobility is lowered and the transistor characteristics are hysteresis. For example, if the gate insulating film has a polycrystalline structure, its surface property tends to be rough, and the relative area between the gate insulating film and the channel layer interface becomes larger than a flat surface with an amorphous structure. As a result, if the defect generation mechanism at the interface is the same, the number of defects increases according to the relative area.

In—M—Zn—O (M is at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge) formed at room temperature by sputtering is the main constituent element, and its resistance value is 10 An oxide gate insulating film of 11 Ω · cm or more has an amorphous structure. And the surface property becomes very flat. The gate insulating film inherits the surface flatness of the base, and the insulating layer in the inverted staggered structure shown in FIG. 1 maintains the flatness of the substrate. In addition, the insulating layer maintains its flatness even on the channel layer formed flat in the staggered structure shown in FIG. That is, the interface between the gate insulating film and the channel layer (semiconductor layer) can keep the relative area to a minimum and suppress the number of defects at the interface. In addition, because of the amorphous structure, there are no grain boundaries in the polycrystalline structure. In general, defects are likely to be generated at grain boundaries, and carrier traps are likely to occur. In addition, although the grain boundary in the gate insulating film tends to be a source of gate leakage current, it can be suppressed by using an amorphous insulating layer. Due to these effects, it is possible to suppress the problem of a decrease in electron mobility and hysteresis in transistor characteristics.

(About amorphous structure)
An amorphous oxide film whose composition in the crystalline state is represented by InGaO 3 (ZnO) m (m is a natural number less than 6) is stable in an amorphous state up to a high temperature of 800 ° C. or higher when the value of m is less than 6. To be kept. However, as the value of m increases, that is, the ratio of ZnO to InGaO 3 increases, and as it approaches the ZnO composition, it becomes easier to crystallize.

  Therefore, the value of m is preferably less than 6 for the amorphous oxide insulating film. The same applies to the amorphous oxide semiconductor layer.

A gate insulating film formed at a low temperature of 300 ° C. or lower has an amorphous structure and exhibits a relatively high relative dielectric constant as an oxide. For example, an insulating film having a composition ratio of indium, gallium, and zinc of 1: 1: 1 can be formed at room temperature by sputtering in an argon gas atmosphere containing oxygen gas. The relative dielectric constant was 8 or more. Therefore, the design film thickness of the insulating layer can be designed thicker than that of SiO 2 or the like. In this case, it is possible to design the film thickness to be twice or more as compared with the relative dielectric constant 3.9 of general SiO 2 , and it is possible to increase the substantial withstand voltage when constructing the TFT, and the reliability. Can be increased. In general, many high dielectric constant materials have an oxide having a crystal structure, and the relative dielectric constant often depends on the crystal orientation. Since the gate insulating film according to the present invention has an amorphous structure and a high relative dielectric constant, the dielectric constant does not change due to nonuniformity due to crystallinity, and a uniform and stable high dielectric constant insulating film is provided even at low temperature formation. It becomes possible to do.

  The relative dielectric constant of the amorphous oxide insulating layer is preferably 4 or more. More preferably, it is 8 or more. This is because the design upper limit value of the film thickness can be relaxed with respect to the relative dielectric constant of about 7 for existing amorphous SiNx and about 4 for the dielectric constant of SiOx.

Here, room temperature refers to a temperature of about 0 ° C. to 40 ° C. Amorphous refers to a compound in which only a halo pattern is observed in an X-ray diffraction spectrum and does not show a specific diffraction line.
(When laminating an amorphous oxide insulating layer and an amorphous oxide semiconductor)
Amorphous oxidation with In-M-Zn-O (M is at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge) as a main constituent element in the configuration of FIG. 1 or FIG. When using a thing, it is preferable to set it as the following structures. That is, it is preferable to increase the band gap by increasing the composition ratio of at least one of Ga, Al, Fe, Sn, and Mg represented by M of the amorphous oxide insulating layer as compared with the semiconductor layer. For example, an amorphous oxide semiconductor film having a 1: 1: 1 composition ratio of indium, gallium, and zinc has a band gap of about 3 eV, so that the band gap of the amorphous oxide insulating film can be increased by sufficiently increasing the Ga composition ratio. It can be about 5 eV.

Further, since the semiconductor layer constitutes a TFT channel layer, its resistance value is preferably less than 10 10 Ω · cm. If the resistance value exceeds this value, it will be difficult to function as a TFT. More preferably, it is 10 3 Ω · cm or more and less than 10 9 Ω · cm. By using a resistance value in this range as the amorphous oxide semiconductor layer, a high value of field effect mobility exceeding 1 cm 2 / (V · sec) can be obtained, and the on / off ratio can be made more than 10 3 .

  By using the amorphous oxide insulating film, a flexible TFT having a staggered (top gate) structure in which a gate insulating film and a gate terminal are sequentially formed on the semiconductor channel layer shown in FIG. 1 can be formed. Further, a flexible TFT having an inverted stagger (bottom gate) structure in which a gate insulating film and a semiconductor channel layer are sequentially formed on the gate terminal shown in FIG. 2 can be formed.

  Note that a glass substrate, a plastic substrate, a plastic film, or the like can be used as a substrate over which the TFT using the insulating film is formed.

(2) Next, a thin film transistor having at least a substrate, a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, and between the semiconductor layer and the gate insulating film A resistive layer, the resistive layer including In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge;
A thin film transistor having an amorphous oxide having a resistance value of 10 11 Ω · cm or more and a film thickness of 1 nm to 200 nm and a resistance layer having a band gap smaller than that of the gate insulating film will be described.

(Suppression of gate leakage current)
By adopting a structure in which the amorphous oxide resistance layer shown in FIG. 3 is provided between the gate insulating film and the semiconductor layer, leakage current can be suppressed. That is, in the structure of FIG. 2, it is possible to prevent the gate leakage current from being increased due to carrier injection from the gate electrode to the semiconductor layer (when there is no significant difference between the band gap of the semiconductor layer and the band gap of the gate insulating film). I can do it.

  At this time, the interface between the amorphous oxide resistance layer and the semiconductor layer can constitute the above-described flat interface. In this case, the thickness of the amorphous oxide resistance layer is preferably 1 nm or more and 200 nm or less, although it depends on the characteristic value of the gate insulating film. If the thickness was less than 1 nm, the effect of inserting the high resistance layer was not observed. Moreover, when the film thickness exceeds 200 nm, it is necessary to increase the gate voltage applied to the gate electrode, which is not practical. When an amorphous oxide resistance layer having a film thickness of 1 nm or more and 200 nm or less is used, gate leakage current in the TFT can be suppressed.

(Suppression of defect generation at the semiconductor layer and insulating film interface)
In the structure shown in FIG. 3, when the semiconductor layer 2 includes at least the composition of an amorphous oxide film that is the resistance layer 7, generation of defects mainly related to oxygen vacancies at the interface is suppressed. It can be considered that the probability of defect generation due to the difference in bonding state is reduced as much as the same components are included in the joining of completely different materials. In addition, since the semiconductor layer and the resistance layer are both oxides and there are few oxygen vacancies in the resistance layer, the increase in carrier density related to oxygen vacancies at the interface between the semiconductor layer and the resistance layer is suppressed, and the increase in off current in the TFT is suppressed. it can. Further, by making the band gap of the resistance layer wider than that of the semiconductor layer, a resistance value of 10 11 Ω · cm or more can be easily realized.

By suppressing the gate leakage current and suppressing the generation of defects at the interface between the semiconductor layer and the insulating film, a highly reliable and normally-off TFT can be realized.
(Functional separation effect: semiconductor layer is carrier generation layer, resistance layer is carrier transport layer)
The following functions can be obtained by using the structure of FIG. 3 and selecting the combination so that the semiconductor layer and the resistive layer have substantially the same band gap or the resistive layer has the same or smaller band gap than the semiconductor layer. . That is, the resistance layer can function mainly as a carrier transport layer. The channel layer can function mainly as a carrier generation layer.

  Here, “mainly” means that the resistance layer has a slight carrier generation function and the semiconductor layer has a slight carrier transport function. That is, it represents the dominant function of the carrier transport function and the carrier generation function.

  In the above description, the “semiconductor layer” and the “resistive layer” are separated from each other for the sake of convenience. However, these two stacked layers have the function of the channel layer. .

  In addition, each of the above layers does not necessarily have to be separated into a single layer. For example, in one channel layer, charge generation is achieved by controlling the composition of the semiconductor material continuously or stepwise in the layer thickness direction. It can have a function and a charge transport function.

Non-Patent Document 1 discloses a configuration in which a transparent amorphous oxide semiconductor film (a-IGZO) made of indium, gallium, zinc, and oxygen is used for a channel layer of a TFT. And it is shown that it is possible to form a flexible and transparent TFT exhibiting good field effect mobility 6-9 cm 2 V -1 s -1 on a substrate such as a polyethylene terephthalate (PET) film at room temperature. ing. By laminating a resistance layer, which is an insulating film having the same composition, on this amorphous oxide semiconductor film, an ideal interface between the semiconductor and the resistance layer can be obtained. Further, by injecting carriers into a resistance layer which is considered to have few oxygen vacancies, that is, a defect density related to oxygen, it can function as a carrier transport layer and can obtain good field effect mobility. In addition, since the carrier transport layer can be an amorphous oxide film with a low stoichiometric ratio (stoichiometry) with little oxygen vacancies, it is chemically stable and has excellent uniformity, stability and reliability. Supply becomes possible.

For this purpose, for example, an amorphous oxide semiconductor layer having a 1: 1: 1 composition ratio of indium, gallium, and zinc and an amorphous oxide resistance layer having the same metal composition as this semiconductor layer is shown in FIG. Create a TFT. With such a configuration, a normally-off operation can be realized with certainty, and the on / off ratio of the transistor can be more than 10 5 . At that time, the field effect mobility is 10 cm 2 V −1 s −1 or more, and it has a suppressing effect on the occurrence of hysteresis in the transistor characteristics.

  Due to these effects, the present invention can provide a thin film transistor using an amorphous resistance layer having a good interface. Further, by using an amorphous oxide semiconductor and a resistance layer, it is possible to realize functional separation using the semiconductor layer as a carrier generation layer and the resistance layer as a carrier transport layer, and a stable and uniform thin film transistor can be supplied.

  The above is an example in which an amorphous oxide including In—Ga—Zn—O is used as a semiconductor layer (channel layer). As described below, In—Ga—Zn—O is used. It is not limited to the amorphous oxide comprised including.

  As the semiconductor layer, an amorphous oxide including at least one element of Sn, In, and Zn can be used.

Furthermore, when Sn is selected as at least a part of the constituent elements of the amorphous oxide, Sn is replaced by Sn 1-x M4 x (0 <x <1, M4 is Si, a group 4 element having an atomic number smaller than Sn, It can also be substituted with Ge or Zr.

When In is selected as at least a part of the constituent elements of the amorphous oxide, In is replaced with In 1-y M3 y (0 <y <1, M3 is Lu, or a Group 3 element having an atomic number smaller than In. Selected from B, Al, Ga, or Y).

In addition, when Zn is selected as at least a part of the constituent elements of the amorphous oxide, Zn is changed to Zn 1-z M2 z (0 <z <1, M2 is Mg of a group 2 element having an atomic number smaller than Zn or Can be substituted.

  Specifically, amorphous materials that can be applied to the present invention are Sn-In-Zn oxide, In-Zn-Ga-Mg oxide, In oxide, In-Sn oxide, In-Ga oxide, In-Zn oxide. Materials, Zn-Ga oxide, Sn-In-Zn oxide, and the like. Of course, the composition ratio of the constituent materials is not necessarily 1: 1. In addition, although Zn and Sn may be difficult to form an amorphous material by themselves, an amorphous phase is easily formed by including In. For example, in the case of the In—Zn system, it is preferable that the atomic ratio excluding oxygen is a composition containing In of about 20 atomic% or more. In the case of the Sn—In system, it is preferable that the ratio of the number of atoms excluding oxygen is such that In is included at about 80 atomic% or more. In the case of the Sn—In—Zn system, it is preferable that the ratio of the number of atoms excluding oxygen is such that In is contained at about 15 atomic% or more.

  Amorphous can be confirmed by the fact that a clear diffraction peak is not detected (that is, a halo pattern is observed) when X-ray diffraction is performed on a thin film to be measured at a low incident angle of about 0.5 degrees. . Note that in the present invention, in the case where the above material is used for a channel layer of a field effect transistor, it does not exclude that the channel layer includes a constituent material in a microcrystalline state.

  In this example, an amorphous In—Ga—Zn—O insulating film was formed by sputtering.

  An amorphous In-Ga-Zn-O insulating film was deposited on a glass substrate (Corning 1737) by a high-frequency sputtering method using a mixed gas of oxygen and argon as an atmosphere. The substrate temperature is 25 ° C. With respect to the obtained film, X-rays were incident on the film surface at an incident angle of 0.5 degree and (thin film method) was subjected to X-ray diffraction. As a result, a clear diffraction peak was not detected, and it was confirmed that all the produced In—Zn—Ga—O films were amorphous films.

  Furthermore, as a result of measuring the X-ray reflectivity and analyzing the pattern, it was found that the mean square roughness (Rrms) of the thin film was about 0.5 nm and the film thickness was about 150 nm. As a result of X-ray fluorescence (XRF) analysis, the metal composition ratio of the thin film was In: Ga: Zn = 0.98: 3.02: 1.00. From the analysis of the optical absorption spectrum, the forbidden band energy width of the fabricated amorphous thin film was found to be about 4 eV.

In addition, a Pt electrode was deposited to 100 nm on a glass substrate (Corning 1737), and an amorphous In—Ga—Zn—O insulating film was deposited to 150 nm on the lower electrode. Furthermore, IV characteristics and CV characteristics were evaluated with a structure in which a Pt electrode having a diameter of 0.5 mm was deposited as a top electrode by a 50 nm mask. As a result of measurement between the upper and lower terminals, the resistance value of the amorphous In—Ga—Zn—O insulating film was 5 × 10 11 Ω · cm, and the relative dielectric constant was 12.

Even when a polyethylene terephthalate (PET) film having a thickness of 200 μm was used instead of the glass substrate, the obtained amorphous oxide insulating film showed similar characteristics.
(Preparation of MISFET element)
The inverted staggered (bottom gate) type MISFET element shown in FIG. 1 was produced. First, Cr was vapor-deposited on the glass substrate 1, and the gate terminal 4 was formed by the photolithography method and the lift-off method. An amorphous In—Ga—Zn—O insulating film used as the gate insulating film 3 was formed to 150 nm thereon by sputtering. Further thereon, an amorphous silicon film having a thickness of 300 nm used as the semiconductor layer 2 was formed at a substrate temperature of 250 ° C. by plasma CVD. A Cr / Al laminated film was deposited by 300 nm, and a drain terminal 5 and a source terminal 6 were formed by photolithography and lift-off methods.

As a result of evaluating the IV characteristics of this MISFET element, the field effect mobility was 0.3 cm 2 / Vs, and the on / off ratio was more than 10 5 .

  As described above, it has been found that an oxide insulating film having an amorphous structure suitable for TFT can be manufactured at room temperature by a sputtering method suitable for large-area film formation.

  In this example, a MISFET element having a stacked structure of an amorphous In—Ga—Zn—O insulating film and an amorphous In—Ga—Zn—O semiconductor layer was produced.

  A staggered (top gate) type MISFET element shown in FIG. 2 was produced. First, an In: Ga: Zn = 0.98: 1.02: 1.00 amorphous In-Ga-Zn-O film having a metal composition ratio of 30 nm used as a channel layer (semiconductor layer) 2 is formed on a glass substrate 1 by sputtering. did. Further thereon, a gold film having a thickness of 30 nm was laminated, and a drain terminal 5 and a source terminal 6 were formed by a photolithography method and a lift-off method. Finally, an amorphous In—Ga—Zn—O insulating film having a metal composition ratio of In: Ga: Zn = 0.98: 3.02: 1.00 used as the gate insulating film 3 was formed to a thickness of 150 nm by sputtering. Further, a gold film was formed thereon, and a gate terminal 4 was formed by a photolithography method and a lift-off method.

As a result of evaluating the IV characteristics of this MISFET element, the field effect mobility was 3 cm 2 / Vs, and the on / off ratio was more than 10 3 .

  From the above, it was found that a TFT using an amorphous In-Ga-Zn-O film as a semiconductor layer and an insulating layer can be manufactured.

  In this example, a MISFET element having a laminated structure of a gate insulating film / amorphous In—Ga—Zn—O resistance layer / amorphous In—Ga—Zn—O semiconductor layer was produced.

  A staggered (top gate) MISFET element shown in FIG. 3 was produced. First, an In: Ga: Zn = 0.98: 1.02: 1.00 amorphous In-Ga-Zn-O film having a metal composition ratio of 30 nm used as the channel layer 2 was formed on the glass substrate 1 by sputtering. Further thereon, a gold film having a thickness of 30 nm was laminated, and a drain terminal 5 and a source terminal 6 were formed by a photolithography method and a lift-off method. An amorphous In—Ga—Zn—O insulating thin film having a metal composition ratio of In: Ga: Zn = 0.98: 3.02: 1.00 used as the high resistance layer 7 was formed to 150 nm thereon by sputtering. Finally, an amorphous SiNx insulating thin film having a thickness of 100 nm was formed as the gate insulating film 3 by the CVD method. Further, a gold film was formed thereon, and a gate terminal 4 was formed by a photolithography method and a lift-off method.

As a result of evaluating the IV characteristics of this MISFET element, the field effect mobility was 5 cm 2 / Vs and the on / off ratio was more than 10 4 .

  From the above, it was found that a TFT using an amorphous In-Ga-Zn-O film as a high resistance layer can be manufactured. It was also confirmed that the high resistance layer has an effect of reducing the off current and the gate leakage current.

  In this example, a MISFET element of gate insulating film / amorphous In—Ga—Zn—O resistance layer (carrier transport layer) / amorphous In—Ga—Zn—O semiconductor layer (carrier generation layer) was produced.

  A staggered (top gate) MISFET element shown in FIG. 3 was produced.

  The resistive layer 7 has the same configuration as that of Example 3 except that an amorphous In—Ga—Zn—O insulating thin film having a metal composition ratio of In: Ga: Zn = 0.98: 1.02: 1.00 was formed to a thickness of 100 nm by sputtering.

FIG. 4 shows the current-voltage characteristics of the TFT element measured at room temperature. As the drain voltage V DS increases, the drain current I DS increases, indicating that the channel is n-type conductive. I DS shows the behavior of a typical semiconductor transistor that saturates (pinch off) at about V DS = 6 V. When the gain characteristic was examined, the threshold value of the gate voltage V GS when V DS = 6 V was applied was about 0.35 V. When V G = 6 V, a current of I DS = 2.0 × 10 −4 A flowed. This corresponds to the fact that carriers can be induced in the insulator In-Ga-Zn-O amorphous oxide film by the gate bias.

The on / off ratio of the transistor was about 5 × 10 6 . Further, when the field effect mobility was calculated from the output characteristics, a field effect mobility of about 11.8 cm 2 (Vs) −1 was obtained in the saturation region.
(Comparative Example 1)
A staggered (top gate) type MISFET element having the same configuration as that of Example 4 was prepared except that the resistance layer 7 was not provided.

As a result of evaluating the IV characteristics of this MISFET element, the field effect mobility was 5 cm 2 / Vs, and the on / off ratio was more than 10 4 .

  Since the transistor off current of the MISFET element of Example 4 was about two orders of magnitude smaller than the transistor off current of the MISFET element of Comparative Example 1, the resistance layer of Example 4 is an insulator when the gate voltage is negatively applied. Function as. On the other hand, when the gate voltage is applied positively, carrier injection from the semiconductor layer occurs and functions as a channel. In addition, since the field effect mobility is about twice as large, it can be seen that the resistance layer functions as a good carrier transport layer.

  The thin film transistor (TFT) according to the present invention can be applied as a switching element of an LCD or an organic EL display. In addition, it is possible to form all TFT processes at low temperatures on flexible materials such as plastic films, and it can be widely applied to flexible displays, IC cards and ID tags.

FIG. 4 is a structural diagram of an inverted staggered TFT using an amorphous oxide as a gate insulating film. FIG. 3 is a structural diagram of a staggered TFT using an amorphous oxide as a gate insulating film. FIG. 5 is a structural diagram of a staggered TFT in which an amorphous oxide resistance layer is provided between a gate insulating film and a semiconductor layer. 6 is a graph showing current-voltage characteristics of a top gate type MISFET element fabricated in Example 4;

Explanation of symbols

1 Substrate 2 Semiconductor layer 3 Gate insulating film 4 Gate electrode (gate terminal)
5 Drain electrode (drain terminal)
6 Source electrode (source terminal)
7 Resistance layer

Claims (4)

  1. A thin film transistor having at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate;
    The gate insulating film includes an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge; der resistance value of 10 11 Ω · cm or more is,
    The semiconductor layer has an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge;
    The composition ratio of at least one of Ga, Al, Fe, Sn, and Mg contained in the gate insulating film is higher than the composition ratio of at least one of Ga, Al, Fe, Sn, and Mg contained in the semiconductor layer. big,
    A thin film transistor , wherein a resistance value of the semiconductor layer is less than 10 10 Ω · cm, and a band gap of the semiconductor layer is smaller than a band gap of the gate insulating film .
  2. A thin film transistor having at least a semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate;
    Having a resistance layer between the semiconductor layer and the gate insulating film;
    The resistance layer includes an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge,
    The semiconductor layer has an amorphous oxide containing In, Zn, O, and at least one of Ga, Al, Fe, Sn, Mg, Ca, Si, and Ge;
    The semiconductor layer has a resistance value of less than 10 10 Ω · cm,
    A thin film transistor, wherein a resistance value of the resistance layer is 10 11 Ω · cm or more, a film thickness is 1 nm or more and 200 nm or less, and a band gap of the resistance layer is smaller than a band gap of the gate insulating film.
  3. 3. The semiconductor layer according to claim 2 , wherein the semiconductor layer is an oxide semiconductor containing at least one composition other than oxygen in the resistance layer, and the band gap of the semiconductor layer is smaller than the band gap of the resistance layer. The thin film transistor described.
  4. 3. The thin film transistor according to claim 2 , wherein the semiconductor layer mainly has a function as a carrier generation layer, and the resistance layer mainly has a function as a carrier transport layer.
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