JP6326379B2 - 超伝導集積回路の製作のためのシステムおよび方法 - Google Patents
超伝導集積回路の製作のためのシステムおよび方法 Download PDFInfo
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- JP6326379B2 JP6326379B2 JP2014561117A JP2014561117A JP6326379B2 JP 6326379 B2 JP6326379 B2 JP 6326379B2 JP 2014561117 A JP2014561117 A JP 2014561117A JP 2014561117 A JP2014561117 A JP 2014561117A JP 6326379 B2 JP6326379 B2 JP 6326379B2
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- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76891—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by using superconducting materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Description
量子コンピュータの設計および動作のためのいくつかの一般的な手法がある。そのような手法の1つは、量子計算の「回路」または「ゲート」モデルである。この手法では、量子ビットは、アルゴリズムのコンパイル済み表現である論理ゲートの順序に作用される。多くの研究は、回路モデル量子コンピュータの基本要素を形成するため、十分なコヒーレンスでの量子ビットの開発に焦点を置いている。
量子計算は、超伝導量子プロセッサなどの量子プロセッサを使用して実行することができる。超伝導量子プロセッサは、例えば、2つ以上の超伝導量子ビットなどの多くの量子ビットおよび関連局所バイアス素子を含む超伝導集積回路を備え得る。本システムおよび方法に従って製作することができる例示的な超伝導量子プロセッサのシステムおよび方法のさらなる詳細については、その各々の全体が参照により本明細書に組み込まれる、米国特許第7,135,701号明細書、米国特許第7,418,283号明細書、米国特許第7,533,068号明細書、米国特許第7,619,437号明細書、米国特許第7,639,035号明細書、米国特許第7,898,282号明細書、米国特許第8,008,942号明細書、米国特許第8,190,548号明細書、米国特許第8,195,596号明細書、米国特許第8,283,943号明細書および米国特許出願公開第2011−0022820号明細書に記載されている。
超伝導量子ビットは、超伝導集積回路に含めることができるある種の超伝導量子素子である。超伝導量子ビットは、情報の符号化に使用される物理的特性に応じていくつかのカテゴリに分類することができる。例えば、超伝導量子ビットは、電荷、磁束および位相素子に分類することができる。電荷素子は、素子の電荷状態の情報を格納し、操作する。磁束素子は、素子の何らかの部分を通り抜ける磁束に関連する変数の情報を格納し、操作する。位相素子は、位相素子の2つの領域間の超伝導位相差に関連する変数の情報を格納し、操作する。最近では、電荷、磁束および位相自由度のうちの2つ以上を使用するハイブリッド素子が開発されている。
コンピュータプロセッサは、超伝導プロセッサの形態を取り得、超伝導プロセッサは、従来の意味での量子プロセッサではなくともよい。例えば、超伝導プロセッサのいくつかの実施形態は、量子トンネル現象、重ね合わせおよび絡み合いなどの量子効果に焦点を置くものでなくともよく、むしろ、例えば、古典的なコンピュータプロセッサの動作を管理する原理などの異なる原理を重視することによって動作することができる。しかし、依然として、そのような「古典的な」超伝導プロセッサの実装には、ある利点が存在し得る。古典的な超伝導プロセッサの自然な物理的特性により、古典的な超伝導プロセッサは、非超伝導プロセッサより高いスイッチング速度および短い計算時間が可能であり得、したがって、古典的な超伝導プロセッサに関するある問題を解く方がより実用的であり得る。本システムおよび方法は、超伝導量子プロセッサと古典的な超伝導プロセッサの両方の製作における使用に特によく適している。
従来、超伝導集積回路の製作は、最先端の半導体製作施設で実行されるものではなかった。これは、超伝導集積回路で使用される材料のいくつかが半導体施設を汚染する恐れがあるという事実に基づき得る。例えば、金は、超伝導回路で抵抗器として使用することができるが、金は、半導体施設でのCMOSウエハの生成に使用される製作ツールを汚染する恐れがある。結果的に、金を含む超伝導集積回路は、通常、CMOSウエハを加工処理するツールでは加工処理されない。
エッチングは、フォトレジストまたは他のマスキング技法によって描出される所望のパターンに従って、例えば、基板、誘電体層、酸化物層、電気絶縁層および/または金属層などの層を取り除く。2つの例示的なエッチング技法は、化学ウェットエッチングおよび化学ドライエッチングである。
Claims (2)
- 三層ジョセフソン接合を形成する方法であって、
ベース電極層、絶縁層および対電極層を含む超伝導三層を堆積させる工程と、
前記超伝導三層を覆ってフォトレジストマスクパターンを堆積させる工程と、
少なくとも1つのジョセフソン接合を形成するために前記超伝導三層にパターンをエッチングする工程であって、前記ベース電極層の少なくとも2つの部分を露出させるため、前記対電極層の少なくとも2つの部分を取り除く工程、および、前記絶縁層の少なくとも2つの部分を取り除く工程を含む、工程とを含み、
前記ジョセフソン接合の対電極と前記ジョセフソン接合の絶縁層は、同じ広がりを持ち、
前記超伝導三層を堆積させる工程は、
チャンバ内でニオブのベース層を堆積させる工程と、
前記チャンバ内で前記ニオブのベース層の少なくとも一部分を覆って酸化アルミニウム層を堆積させる工程と、
前記ニオブのベース層および前記酸化アルミニウム層を熱化するため、不活性ガスで前記チャンバを満たす工程と、
前記チャンバから前記不活性ガスをポンピングで送り出す工程と、
前記不活性ガスをポンピングで送り出す工程の後に、前記チャンバ内で前記酸化アルミニウム層の少なくとも一部分を覆ってニオブの最上層を堆積させる工程とを含む、
方法。 - 不活性ガスで前記チャンバを満たす工程は、アルゴンで前記チャンバを満たす工程を含む、請求項1に記載の方法。
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US9768371B2 (en) | 2017-09-19 |
JP2024105311A (ja) | 2024-08-06 |
JP7212002B2 (ja) | 2023-01-24 |
WO2013180780A2 (en) | 2013-12-05 |
JP7478268B2 (ja) | 2024-05-02 |
US20150119252A1 (en) | 2015-04-30 |
US20180033944A1 (en) | 2018-02-01 |
JP2018129535A (ja) | 2018-08-16 |
US20200274050A1 (en) | 2020-08-27 |
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