JP6196092B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6196092B2
JP6196092B2 JP2013158233A JP2013158233A JP6196092B2 JP 6196092 B2 JP6196092 B2 JP 6196092B2 JP 2013158233 A JP2013158233 A JP 2013158233A JP 2013158233 A JP2013158233 A JP 2013158233A JP 6196092 B2 JP6196092 B2 JP 6196092B2
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Japan
Prior art keywords
wire
bonding
terminal
view
semiconductor chip
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JP2013158233A
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Japanese (ja)
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JP2015029022A (ja
JP2015029022A5 (enExample
Inventor
洋輔 今関
洋輔 今関
壮司 黒田
壮司 黒田
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2013158233A priority Critical patent/JP6196092B2/ja
Priority to US14/329,833 priority patent/US9281289B2/en
Priority to CN201410352981.6A priority patent/CN104347549B/zh
Priority to CN201810790404.3A priority patent/CN109037184B/zh
Priority to KR1020140094613A priority patent/KR20150014867A/ko
Priority to TW103125751A priority patent/TWI631680B/zh
Publication of JP2015029022A publication Critical patent/JP2015029022A/ja
Priority to HK15107383.3A priority patent/HK1206869B/zh
Priority to US15/041,858 priority patent/US10170402B2/en
Publication of JP2015029022A5 publication Critical patent/JP2015029022A5/ja
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Publication of JP6196092B2 publication Critical patent/JP6196092B2/ja
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    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
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    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2013158233A 2013-07-30 2013-07-30 半導体装置 Active JP6196092B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2013158233A JP6196092B2 (ja) 2013-07-30 2013-07-30 半導体装置
US14/329,833 US9281289B2 (en) 2013-07-30 2014-07-11 Semiconductor device and method of manufacturing the same
CN201810790404.3A CN109037184B (zh) 2013-07-30 2014-07-23 半导体器件
CN201410352981.6A CN104347549B (zh) 2013-07-30 2014-07-23 半导体器件及其制造方法
KR1020140094613A KR20150014867A (ko) 2013-07-30 2014-07-25 반도체 장치 및 그 제조 방법
TW103125751A TWI631680B (zh) 2013-07-30 2014-07-28 半導體裝置
HK15107383.3A HK1206869B (zh) 2013-07-30 2015-08-01 半导体器件及其制造方法
US15/041,858 US10170402B2 (en) 2013-07-30 2016-02-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013158233A JP6196092B2 (ja) 2013-07-30 2013-07-30 半導体装置

Publications (3)

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JP2015029022A JP2015029022A (ja) 2015-02-12
JP2015029022A5 JP2015029022A5 (enExample) 2016-04-07
JP6196092B2 true JP6196092B2 (ja) 2017-09-13

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US (2) US9281289B2 (enExample)
JP (1) JP6196092B2 (enExample)
KR (1) KR20150014867A (enExample)
CN (2) CN104347549B (enExample)
TW (1) TWI631680B (enExample)

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Publication number Priority date Publication date Assignee Title
JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法
JP6991014B2 (ja) 2017-08-29 2022-01-12 キオクシア株式会社 半導体装置
TWI739379B (zh) * 2019-04-24 2021-09-11 日商新川股份有限公司 半導體裝置、半導體裝置的製造方法、以及打線接合裝置
CN110265378B (zh) * 2019-06-19 2020-10-23 福建福顺半导体制造有限公司 一种电子元件
KR102736238B1 (ko) * 2020-01-10 2024-12-02 에스케이하이닉스 주식회사 본딩 와이어 분지 구조를 포함한 반도체 패키지
KR102864755B1 (ko) 2020-07-10 2025-09-24 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US12142595B2 (en) * 2020-12-23 2024-11-12 Skyworks Solutions, Inc. Apparatus and methods for tool mark free stitch bonding
US12021063B2 (en) 2021-01-28 2024-06-25 Qualcomm Incorporated Circular bond finger pad
CN114864420B (zh) * 2022-04-19 2025-01-28 江西万年芯微电子有限公司 一种提升薄芯片良率的贴片方式
KR20230173269A (ko) 2022-06-16 2023-12-27 삼성전자주식회사 반도체 패키지

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JP2015029022A (ja) 2015-02-12
CN104347549B (zh) 2018-08-10
KR20150014867A (ko) 2015-02-09
US20150035172A1 (en) 2015-02-05
TWI631680B (zh) 2018-08-01
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CN104347549A (zh) 2015-02-11
TW201505145A (zh) 2015-02-01
HK1206869A1 (zh) 2016-01-15

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