KR20150014867A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

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Publication number
KR20150014867A
KR20150014867A KR1020140094613A KR20140094613A KR20150014867A KR 20150014867 A KR20150014867 A KR 20150014867A KR 1020140094613 A KR1020140094613 A KR 1020140094613A KR 20140094613 A KR20140094613 A KR 20140094613A KR 20150014867 A KR20150014867 A KR 20150014867A
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South Korea
Prior art keywords
bonding
terminals
wire
semiconductor chip
wires
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KR1020140094613A
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English (en)
Korean (ko)
Inventor
요스께 이마제끼
소시 구로다
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르네사스 일렉트로닉스 가부시키가이샤
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Publication of KR20150014867A publication Critical patent/KR20150014867A/ko
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
    • H10W70/635Through-vias
    • HELECTRICITY
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69Insulating materials thereof
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
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    • H10W72/07521Aligning
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    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
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    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07531Techniques
    • H10W72/07532Compression bonding, e.g. thermocompression bonding
    • H10W72/07533Ultrasonic bonding, e.g. thermosonic bonding
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    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07553Controlling the environment, e.g. atmosphere composition or temperature changes in shapes
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/353Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
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    • H10W72/531Shapes of wire connectors
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    • H10W72/531Shapes of wire connectors
    • H10W72/537Multiple bond wires having different shapes
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/541Dispositions of bond wires
    • H10W72/5434Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
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    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
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    • H10W72/00Interconnections or connectors in packages
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    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
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    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
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    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/59Bond pads specially adapted therefor
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    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
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    • H10W72/944Dispositions of multiple bond pads
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    • H10W72/951Materials of bond pads
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W90/28Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
KR1020140094613A 2013-07-30 2014-07-25 반도체 장치 및 그 제조 방법 Withdrawn KR20150014867A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2013-158233 2013-07-30
JP2013158233A JP6196092B2 (ja) 2013-07-30 2013-07-30 半導体装置

Publications (1)

Publication Number Publication Date
KR20150014867A true KR20150014867A (ko) 2015-02-09

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KR1020140094613A Withdrawn KR20150014867A (ko) 2013-07-30 2014-07-25 반도체 장치 및 그 제조 방법

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US (2) US9281289B2 (enExample)
JP (1) JP6196092B2 (enExample)
KR (1) KR20150014867A (enExample)
CN (2) CN104347549B (enExample)
TW (1) TWI631680B (enExample)

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JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法
JP6991014B2 (ja) 2017-08-29 2022-01-12 キオクシア株式会社 半導体装置
TWI739379B (zh) * 2019-04-24 2021-09-11 日商新川股份有限公司 半導體裝置、半導體裝置的製造方法、以及打線接合裝置
CN110265378B (zh) * 2019-06-19 2020-10-23 福建福顺半导体制造有限公司 一种电子元件
KR102736238B1 (ko) * 2020-01-10 2024-12-02 에스케이하이닉스 주식회사 본딩 와이어 분지 구조를 포함한 반도체 패키지
KR102864755B1 (ko) 2020-07-10 2025-09-24 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US12142595B2 (en) * 2020-12-23 2024-11-12 Skyworks Solutions, Inc. Apparatus and methods for tool mark free stitch bonding
US12021063B2 (en) 2021-01-28 2024-06-25 Qualcomm Incorporated Circular bond finger pad
CN114864420B (zh) * 2022-04-19 2025-01-28 江西万年芯微电子有限公司 一种提升薄芯片良率的贴片方式
KR20230173269A (ko) 2022-06-16 2023-12-27 삼성전자주식회사 반도체 패키지

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JPS61105851A (ja) 1984-10-30 1986-05-23 Toshiba Corp ワイヤボンデイング方法
JPH06103697B2 (ja) * 1988-06-25 1994-12-14 日本電気株式会社 コンパクトicのワイヤボンディング構造体
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP2001156107A (ja) * 1999-11-30 2001-06-08 Rohm Co Ltd Icチップ、およびこれの導体ワイヤ接続方法
JP4034932B2 (ja) * 2000-12-15 2008-01-16 株式会社沖データ 半導体装置、ledプリントヘッドおよびワイヤボンディング方法
JP2002237567A (ja) * 2001-02-09 2002-08-23 Nec Corp 半導体装置
WO2002103793A1 (en) * 2001-06-07 2002-12-27 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
JP4967524B2 (ja) * 2006-08-15 2012-07-04 ヤマハ株式会社 半導体装置及びワイヤーボンディング方法
JP2008171927A (ja) * 2007-01-10 2008-07-24 Renesas Technology Corp 半導体装置
JP2009043793A (ja) * 2007-08-07 2009-02-26 Panasonic Corp 半導体装置、およびその半導体装置の製造方法

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CN109037184A (zh) 2018-12-18
US20160163625A1 (en) 2016-06-09
US9281289B2 (en) 2016-03-08
CN109037184B (zh) 2022-05-03
JP2015029022A (ja) 2015-02-12
CN104347549B (zh) 2018-08-10
US20150035172A1 (en) 2015-02-05
TWI631680B (zh) 2018-08-01
US10170402B2 (en) 2019-01-01
CN104347549A (zh) 2015-02-11
JP6196092B2 (ja) 2017-09-13
TW201505145A (zh) 2015-02-01
HK1206869A1 (zh) 2016-01-15

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