TWI631680B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI631680B
TWI631680B TW103125751A TW103125751A TWI631680B TW I631680 B TWI631680 B TW I631680B TW 103125751 A TW103125751 A TW 103125751A TW 103125751 A TW103125751 A TW 103125751A TW I631680 B TWI631680 B TW I631680B
Authority
TW
Taiwan
Prior art keywords
lead
pin
solder
semiconductor wafer
view
Prior art date
Application number
TW103125751A
Other languages
English (en)
Other versions
TW201505145A (zh
Inventor
今關洋輔
黑田壯司
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW201505145A publication Critical patent/TW201505145A/zh
Application granted granted Critical
Publication of TWI631680B publication Critical patent/TWI631680B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/48479—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48499—Material of the auxiliary connecting means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4945—Wire connectors having connecting portions of different types on the semiconductor or solid-state body, e.g. regular and reverse stitches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85186—Translational movements connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10271—Silicon-germanium [SiGe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本發明公開了一種可提高半導體裝置可靠性之技術。所述半導體裝置包括具有形成於晶片搭載面上之複數個焊點(引腳)BF之佈線基板3、搭載於佈線基板3上之半導體晶片、以及分別具有球形部Bnd1及針腳部Bnd2之複數條引線BW。複數個焊點BF具有分別與引線BWa之針腳部Bnd2連接之焊點BF1、以及與引線BWb之球形部Bnd1連接之焊點BF2。另外，於俯視時，焊點BF2配置在與複數個焊點BF1之配置行Bd1上不同之位置上，而且，焊點BF2之寬度W2比焊點BF1之寬度W1大。

Description

半導體裝置
本發明涉及一種半導體裝置及其製造技術，尤其適用於一種經由引線將半導體晶片之電極和佈線基板之引腳電連接之半導體裝置有效之技術。
在日本特開1986-105851號公報(專利文獻1)中，公開了通過引線焊接將2行焊盤分別連接到互為面對面之兩個區域上之技術。專利文獻1中，將所述2行焊盤行中位於各區域之邊界線外側之焊盤行稱為第1焊盤，將位於分界線內側之焊盤行稱為第2焊盤。
[專利文獻]
專利文獻1 日本特開1986-105851號公報
既有技術中，已經存在經由引線將佈線基板之引腳與搭載於所述佈線基板上之半導體晶片之電極進行電連接之技術。
近年來，隨著半導體裝置高功能化之要求，所述引腳數量(以下簡稱“引腳數”)具有增大之傾向。
但是，如果僅增加引腳數，將會導致佈線基板之平面尺寸變大。而對此之對策只能是縮小每一個引腳之平面尺寸(外型尺寸)，但因此也將導致將引線和引腳穩定連接之容限變小。
下面說明解決上述課題之方法。本發明之所述內容及所述內容以外之目的和新特徵在本說明書之描述及附圖說明中寫明。
本發明一實施方式中之半導體裝置具有：形成於晶片搭載面上之複數個引腳之佈線基板；搭載於所述佈線基板上之半導體晶片；分別具有球形部及針腳部且分別與所述複數個引腳連接之複數條引線等。所述複數個引腳具有分別與複數條第1引線之所述針腳部連接之複數個第1引腳、以及與第2引線之所述球形部連接之第2引腳。另外，於俯視時，所述第2引腳配置在與所述複數個第1引腳之配置行上之不同位置上、而且所述第2引腳之寬度比所述複數個第1引腳之每一個之寬度都大。
根據所述一實施方式，便可提高半導體裝置之可靠性。
1、1A、1B、1C、1D‧‧‧半導體裝置
2‧‧‧半導體晶片
2a‧‧‧表面(主面、上表面)
2b‧‧‧背面(主面、下表面)
2c‧‧‧側面
3‧‧‧佈線基板
3a‧‧‧上表面(晶片搭載面)
3b‧‧‧下表面(安裝面)
3c‧‧‧側面
3e‧‧‧絕緣層(核心絕緣層)
3h‧‧‧阻焊膜(絕緣膜)
3p‧‧‧供電線
3r‧‧‧佈線
4‧‧‧封裝體(樹脂體)
4a‧‧‧上表面
4b‧‧‧下表面
4c‧‧‧側面
5、6‧‧‧晶片黏接材料(黏結材料)
7‧‧‧焊接材料
25‧‧‧佈線基板
25a‧‧‧器件形成部
25b‧‧‧框部
25c‧‧‧切割部(切割線)
Bd1‧‧‧配置行(第1行配置行)
Bd2‧‧‧配置行(第2行配置行)
BF‧‧‧焊點(引腳、晶片搭載面側引腳、焊接引線)
BF1‧‧‧焊點(點焊用之焊點、正向焊接方式用之焊點)
BF2‧‧‧焊點(球焊用之焊點、逆向焊接方式用之焊點)
BMP‧‧‧突起電極(導電性材料)
Bnd1‧‧‧球形部
Bnd2‧‧‧針腳部
BW‧‧‧引線(導電性材料)
BWa‧‧‧引線(正向焊接方式之引線)
BWb‧‧‧引線(逆向焊接方式之引線)
CC‧‧‧控制晶片(半導體晶片)
CP‧‧‧劈刀
CP1、CP2、CP3、CP4、CP5‧‧‧箭頭
DBL‧‧‧劃片刀(旋轉刃)
FC‧‧‧類比晶片(半導體晶片)
Fp1‧‧‧圓形部(部分)
Fp2‧‧‧延伸部(部分)
L1、L2、L3‧‧‧延伸方向之長度
LD‧‧‧焊接盤(外部引腳、電極墊、外部電極墊)
PD、PD1、PD2‧‧‧複數個焊盤(引腳、電極、電極墊、焊盤)
S1、S2、S3、S4‧‧‧邊
SR‧‧‧阻焊膜(絕緣膜)
SRp‧‧‧開口部
W1、W2、W3、W4、Wbt、Wbp‧‧‧寬度
θ1、θ2‧‧‧傾斜角度
圖1係一實施方式中半導體裝置之透視圖。
圖2係圖1中半導體裝置之底視圖。
圖3係除去圖1之封裝體後之狀態下佈線基板上半導體裝置之內部結構之透視平面圖。
圖4係沿著圖1之A-A線截斷之截面圖。
圖5係在圖3之複數條引線中，將下段側之半導體晶片和佈線基板進行電連接之引線之放大截面圖。
圖6係在圖3之複數條引線中，將上段側之半導體晶片和佈線基板進行電連接之引線之放大截面圖。
圖7係在圖3之佈線基板之晶片搭載面側之平面中，將焊點配置密度高之區域進行放大後之放大平面圖。
圖8係將比圖7中焊點配置密度低之區域進行放大後之放大平面 圖。
圖9係一實施方式中半導體裝置之組裝流程之說明圖。
圖10係在圖9所示之基板準備製程中所準備之佈線基板整體結構之平面圖。
圖11係在圖10所示之複數個器件形成部之一個中，將與圖7所示區域對應之部分之放大平面圖。
圖12係將半導體晶片搭載到圖10所示之佈線基板上之狀態之放大平面圖。
圖13係沿著圖12之A-A線截斷之放大截面圖。
圖14係通過引線焊接將圖12之半導體晶片和佈線基板進行電連接之狀態之放大平面圖。
圖15係通過引線焊接將圖13之半導體晶片和佈線基板進行電連接之狀態之放大截面圖。
圖16係在通過正向焊接方式焊接之第1焊盤側中，將球形部接合到焊盤之狀態之放大截面圖。
圖17係在通過正向焊接方式焊接之第2焊盤側中，將針腳部接合到焊點之狀態之放大截面圖。
圖18係在通過逆向焊接方式焊接之第1焊盤側中，將球形部接合到焊點之狀態之放大截面圖。
圖19係在通過逆向焊接方式焊接之第2焊盤側中，將針腳部接合到突起電極之狀態之放大截面圖。
圖20係通過樹脂將圖15所示之半導體晶片及複數條引線進行封裝後之狀態之放大截面圖。
圖21係在圖20之複數個焊接盤之每一個露出面上形成焊錫後之狀態之放大截面圖。
圖22係通過劃片刀將圖21之佈線基板進行切斷後之狀態之放大截 面圖。
圖23係圖7之變形例之放大平面圖。
圖24係在圖3所示之半導體裝置之變形例中，半導體晶片所具有之複數個焊盤和佈線基板之複數個焊點之連接關係之模式放大平面圖。
圖25係圖24之變形例之放大平面圖。
圖26係圖24之其他變形例之放大平面圖。
圖27係焊點形狀及大小都與圖7所示之實施方式不同之焊點之放大平面圖。
圖28係沿著圖27之A-A線截斷之放大截面圖。
圖29係焊點形狀及大小都與圖7所示之實施方式不同之焊點之放大平面圖。
圖30係焊點形狀及大小都與圖7所示之實施方式不同之焊點之放大平面圖。
(關於本專利說明書中敘述方式、基本用語以及用法等說明)
在以下實施方式中，為了方便，在必要時將幾個部分或將實施方式分割來說明，除了需要特別說明之外，這些敘述並非彼此獨立且無關係的，而係與其它一部分或者全部變形例、詳細內容及補充說明等相互關聯的。同樣地，在以下實施方式中提及之構成要素等時，除了原理上已經明確了數量或從前後文來看並非如此時，並非必須之要素。
同樣地，在實施方式等敘述上，對於材料及構成等方面，除了寫明瞭僅限於所述材料外，“由A構成”“具有A”“包括A”等表述還指主要構成要素除了A以外還有其他要素。例如“矽材料”等並非限定於單純矽元素，也可為Si-Ge(鍺化矽)合金或其他以矽為主要成分之多元合 金、以及還含有其他添加物之矽材料等。另外，提到鍍金、Cu層、鍍鎳等時也同樣，除了特別說明情況之外，還分別指以金、銅、鎳等為主要成分之材料。
同樣地，在以下實施方式中提及之特定數值及數量等時，除了特別說明時及原理上已經明確了並非如此時，實質上還指可大於等於該特定數或小於等於該特定數。
另外，為了說明實施方式之所有圖中，原則上對具有同一功能之構件採用同一符號，並且略掉重複說明。
另外，在實施方式所用之圖中，為了使圖面簡單易懂，有時會省略掉剖面圖之剖面線或者給平面圖加上剖面線，或者即使在平面上存在通孔，但在圖面中省略了通孔之背景輪廓線等，在此不再贅言。
以下實施方式中所說明之技術可廣泛適用於如下之半導體裝置，即經由金屬線即引線將形成於半導體晶片表面上之電極墊和搭載有半導體晶片之佈線基板之引腳(焊點)進行電連接之半導體裝置。本實施方式中，以在佈線基板上層積有複數個半導體晶片、且彼此之間都被電連接之SiP(System in Package，系統級封裝)型之半導體裝置為例進行了說明。
圖1係一實施方式中半導體裝置之透視圖。圖2係圖1中之半導體裝置之底視圖。圖3係除去圖1之封裝體後之狀態下佈線基板上半導體裝置之內部結構之透視平面圖。圖4係沿著圖1之A-A線截斷之截面圖。圖4中，為了區分正向焊接方式之引線BWa和逆向焊接方式之引線BWb環形形狀之不同，用雙點虛線示出引線BWb。
<半導體裝置>
下面首先通過圖1~圖4來說明本實施方式中半導體裝置1之結構概要。本實施方式中半導體裝置1具有複數個半導體晶片2(請參照圖3、圖4)、以及搭載有複數個半導體晶片2之佈線基板3。如圖4所示， 以層積在佈線基板3之上表面(晶片搭載面)3a側上之方式搭載有複數個半導體晶片2，且所述複數個半導體晶片2分別被封裝體(樹脂體)4覆蓋。
本實施方式中，搭載于下段側之半導體晶片2例如為形成有類比電路之類比晶片(半導體晶片)FC。另外，搭載在類比晶片FC上之半導體晶片2為在對所述類比電路進行控制之控制電路中形成之控制晶片CC。如上所述，在一個封裝內搭載有複數個複數個半導體晶片2之半導體封裝被稱為多晶片型半導體裝置。另外，將由搭載在一個封裝內且相互電連接之複數個半導體晶片2並構成系統之半導體封裝稱為SiP型半導體裝置。具有SiP型半導體裝置之多晶片型半導體裝置在對每個半導體晶片2進行封裝時都進行比較，由此可減少安裝面積。尤其如本實施方式所述，將複數個半導體晶片2進行層積時，比起將複數個半導體晶片2排列配置更能減小安裝面積。
如圖4所示，封裝體4具有上表面4a、位於上表面4a相反側之下表面4b、以及位於上表面4a和下表面4b之間之側面4c，且於俯視時為四角形。圖1所示之例子中，封裝體4之平面面積(從上表面4a側之平面上看時之面積)與佈線基板3之平面面積相同，且封裝體4之側面4c與佈線基板3之側面3c相連。佈線基板3及封裝體4之平面形狀如由一邊之長度為6mm左右之四角形構成。另外，為了應對半導體裝置1薄型化之要求，還對封裝體4進行了薄型化設計。封裝體4之厚度(高度)即圖4所示從上表面4a到下表面4b之間之距離如為600~800μm左右。
另外，如圖3及圖4所示，搭載在佈線基板3上之複數個半導體晶片2之每一個都具有表面(主面、上表面)2a、位於表面2a相反側之背面(主面、下表面)2b(請參照圖4)、以及位於表面2a和背面2b之間之側面2c(請參照圖4)。為了應對半導體裝置1薄型化之要求，還對半導體晶片2進行薄型化設計。另外，半導體晶片2每一個之厚度(高度)例如為 200~300μm左右。如圖3所示，複數個半導體晶片2之每一個於俯視時都為四角形。本實施方式中，搭載于上段之半導體晶片2(圖3所示之控制晶片CC)之平面尺寸(平面面積)比搭載于下段側之半導體晶片2(圖3所示之類比晶片FC)之平面尺寸(平面面積)小。
具體內容如圖3所示，複數個半導體晶片2之每一個於俯視時都具有邊S1、位於邊S1相反側之邊S2、與邊S1及邊S2相交之邊S3、以及位於邊S3相反側之邊S4。另外，類比晶片FC之邊S1以沿著控制晶片CC之邊S1之方式配置，且類比晶片FC之邊S1比控制晶片CC之邊S1長。類比晶片FC之邊S2以沿著控制晶片CC之邊S2之方式配置，且類比晶片FC之邊S2比控制晶片CC之邊S2長。類比晶片FC之邊S3以沿著控制晶片CC之邊S3之方式配置，且類比晶片FC之邊S3比控制晶片CC之邊S3長。另外，類比晶片FC之邊S4以沿著控制晶片CC之邊S4之方式配置，且類比晶片FC之邊S4比控制晶片CC之邊S4長。
另外，圖3所示之例子中，類比晶片FC各邊之長度比控制晶片各邊之長度長，於俯視時，整個控制晶片CC與類比晶片FC之表面2a重合。於俯視時，類比晶片FC如由一邊之長度為3~5mm左右之四角形構成，而控制晶片CC如由一邊之長度為1~2mm左右之四角形構成。
另外，於俯視時為四角形之半導體晶片2之表面2a上，沿著表面2a各邊分別配置有複數個焊盤PD(引腳、電極、電極墊、焊盤)。另外，雖然圖中未示出，半導體晶片2之主面(具體地說就是設置在半導體晶片2之基材(半導體基板)之主面(半導體元件形成面、上表面)之半導體元件形成區域)上形成有複數個半導體元件(電路元件)。而且，複數個焊盤PD經由佈線(圖中未示出)與所述半導體元件電連接，所述佈線形成於配置在半導體晶片2內部(具體地說是在表面2a與圖中未示出之半導體元件形成區域之間)之佈線層上。
半導體晶片2(具體地說就是半導體晶片2之基材即半導體基板)例 如由矽(Si)構成。另外，表面2a上形成有覆蓋半導體晶片2之基材及佈線之絕緣膜，而且，在形成於所述絕緣膜上之開口部中，複數個焊盤PD每一個之表面從所述絕緣膜露出。另外，所述焊盤PD由金屬構成，如主要由鋁(Al)構成。另外，例如為了使所述焊盤PD上與其他佈線連接而在其他位置上重新配置焊盤即所謂再佈線技術中，所述再佈線之一部分將成為新焊盤。此時，以銅(Cu)為主成分之佈線表面上形成鎳(Ni)，且在鎳(Ni)上形成有金(Au)。
類比晶片FC及控制晶片CC搭載在佈線基板3之上表面3a上。圖3所示之例子中，類比晶片FC搭載於佈線基板3之上表面3a之中央部，控制晶片CC搭載於類比晶片FC之中央部。另外，如圖4所示，在背面2b面向佈線基板3之上表面3a之狀態下，經由晶片黏接材料5將類比晶片FC搭載到佈線基板3上。也就是說，通過將形成有複數個焊盤PD之表面(主面)2a之相反面(背面2b)朝向晶片搭載面(上表面3a)即所謂面朝上安裝方式搭載類比晶片FC。另外，在背面2b面朝向類比晶片FC之表面2a之狀態下，經由晶片黏接材料6將控制晶片CC搭載到類比晶片FC上。
晶片黏接材料5為將半導體晶片2和佈線基板3進行黏接固定之膏狀黏接材料，如通過使膏狀接著材料硬化後使半導體晶片2和佈線基板3進行黏接固定。另外，晶片黏接材料6如為將兩個半導體晶片2進行黏接固定之膜狀黏接材料，例如通過使被稱為DAF(Die Attach Film)之樹脂膜等硬化將上下段之半導體晶片2進行黏結固定。但是，晶片黏接材料5、6並非僅限於此，如還可用所述樹脂膜作為晶片黏接材料5，也可用膏狀黏接材料作為黏接材料6。用做晶片黏接材料5、6之黏接材料不管為樹脂膜或膏狀黏接材料，主要成分多為環氧樹脂。
另外，如圖4所示，佈線基板3具有搭載有半導體晶片2之上表面(晶片搭載面)3a、位於上表面3a相反側之下表面(安裝面)3b、以及配 置在上表面3a和下表面3b之間之複數個側面3c。而且，如圖2及圖3所示，於俯視時，佈線基板3為四角形。
詳情如圖3所示，於俯視時，佈線基板3具有邊S1、位於邊S1相反側之邊S2、與邊S1及邊S2相交之邊S3、以及位於邊S3相反側之邊S4。另外，圖3所示之示例中，半導體晶片2之邊S1、S2、S3、S4分別以沿著佈線基板3之邊S1、S2、S3、S4之方式配置。如上所述，圖1所示之示例中，佈線基板3之平面面積與封裝體4之平面面積相同，而且，佈線基板3之平面形狀如為一邊之長度為6mm左右之四角形。圖1所示之示例為長方形。另外，佈線基板3之厚度(高度)即如圖4所示從上表面3a到下表面3b之間之距離例如為0.2~0.4mm左右。
佈線基板3具有複數個佈線層(圖4所示之示例中為上表面佈線層及下表面佈線層共2層)。配置在各佈線層之間之絕緣層3e如為通過預浸材將樹脂預浸到玻璃纖維或碳纖維中而形成。另外，絕緣層3e之上表面側形成有複數個焊點BF、絕緣層3e之下表面側形成有複數個焊接盤LD，並經由複數條佈線3r將焊點BF和焊接盤LD進行電連接。
另外，如圖3所示，佈線基板3之上表面3a上形成有用於將佈線基板3和半導體晶片2電連接之內部介面用引腳即複數個焊點(引腳、晶片搭載面側引腳、焊接引線)BF。複數個焊點BF沿著半導體晶片2之各邊配置在搭載有半導體晶片2之晶片搭載區域周邊。具體地說就是，在佈線基板3之上表面3a上形成阻焊膜(絕緣膜)SR，所述阻焊膜SR覆蓋形成於絕緣層3e之上表面側之佈線，且複數個焊點BF在阻焊膜SR上形成之開口部SRp中從阻焊膜SR露出。
另外，半導體晶片2之複數個焊盤PD和佈線基板3之複數個焊點BF經由複數條引線(導電性材料)BW分別被電連接。另外，本實施方式中之複數條引線BW例如由金(Au)構成，也可由其他材料如以銅(Cu)為主要成分之金屬構成。關於焊點BF及引線BW之內容後文還有 詳述。
另外，如圖2所示，佈線基板3之下表面3b上形成有複數個焊接盤(外部引腳、電極墊、外部電極墊)LD。複數個焊接盤LD按行列狀(矩陣狀)配置。另外，如圖4所示，複數個焊接盤LD經由形成於佈線基板3上之複數條佈線3r分別與複數個焊點BF電連接。也就是說，複數個焊接盤LD之每一個分別與複數個半導體晶片2之每一個電連接，為將複數個半導體晶片2與圖中未示出之外部設備進行電連接之外部介面用之引腳。
上述之半導體裝置即將外部引腳按行列狀配置在佈線基板之安裝面側上之半導體裝置被稱為面積陣列(Area array)型半導體裝置。面積陣列型之半導體裝置中，由於可將佈線基板3之安裝面(下表面3b)側作為外部引腳之配置空間，所以即使增加了外部引腳數量也可抑制半導體裝置安裝面積之增加。也就是說，隨著高功能化及高集成化之進展，可對增加了外部引腳數之半導體裝置進行省空間安裝。
另外，圖2之示例中外部引腳數為140個，但是引腳數及佈局情況並不僅限於此。圖4中以分別在絕緣層3e之上表面和下表面形成了佈線層之佈線基板3為例進行了說明，但佈線層數並不僅限於此，也可設為2層以上之佈線層之結構。
如圖4所示，構成佈線基板3之導電電路之焊點BF、焊接盤LD及佈線3r通過對金屬膜進行圖案化而形成的，如由以銅(Cu)為主之導電膜構成。另外，佈線3r中，將絕緣層3e之上表面側和下表面側進行導通之佈線3r如由以銅(Cu)為主之導電膜構成，並通過將金屬膜填埋通孔而形成。因此，在以銅為主體之導電膜中，可選擇銅單體、銅合金、或在銅膜上層積了其他金屬膜(如鎳膜等)之金屬膜，可根據佈線基板3所要求之規格來進行選擇。
另外，複數個焊接盤LD分別從覆蓋佈線基板3之下表面3b之阻焊 膜(絕緣膜)3h露出。具體說就是，在佈線基板3之下表面3b上形成有阻焊膜(絕緣膜)3h，所述阻焊膜3h覆蓋形成於絕緣層(核心絕緣層)3e之下表面側上之佈線，而且，各焊接盤LD分別在形成於阻焊膜3h上之複數個開口部中從阻焊膜3h露出。
另外，本實施方式中，焊接盤LD每一個露出面都被焊接材料7所覆蓋。將半導體裝置1安裝到圖中未示出之安裝基板上時，將安裝基板側之引腳與半導體裝置1進行電連接之導電性接合材料大多使用焊錫。因此，通過在外部引腳即焊接盤LD從阻焊膜3h之露出面上形成焊接材料7，在將半導體裝置1安裝到圖中未示出之安裝基板上時，可提高焊錫之可濕性。如圖1、圖2及圖4所示，焊接材料7為球狀時被稱為BGA(Ball Grid Array)型。另外，雖然圖中未示出，將變形例中之半導體裝置稱為LGA(Land Grid Array)型，即不形成焊接材料7，而係露出焊接盤LD之結構、或在焊接盤LD之露出面上形成很薄之焊接材料、或形成由焊接材料以外之金屬材料構成之電鍍膜之半導體裝置。
焊接材料7中不含鉛(Pb)，即所謂無鉛焊錫，如為純錫(Sn)、錫-鉍(Sn-Bi)、或為錫-銀-銅(Sn-Ag-Cu)等。因此，無鉛焊錫係指鉛(Pb)含量不超過0.1wt%之焊錫，該含量係以RoHs(Restriction of Hazardous Substances)指令為准而規定的。後文在提到焊錫時，除了特別說明之情況除外，都指無鉛焊錫。
<引線及焊點之詳細內容>
接下來，對圖3及圖4所示通過引線BW進行電連接之部分之詳細結構進行說明。圖5係在圖3之複數條引線中，將下段側之半導體晶片和佈線基板進行電連接之引線之放大截面圖。圖6係在圖3之複數條引線中，將上段側之半導體晶片和佈線基板進行電連接之引線之放大截面圖。圖7係在圖3之佈線基板之晶片搭載面側之平面中，將焊點配置密度高之區域進行放大後之放大平面圖。圖8係將比圖7中焊點配置密 度低之區域進行放大後之放大平面圖。圖27、圖29、圖30分別示出了焊點形狀及大小都與圖7所示之實施方式不同之焊點之放大平面圖。圖28係沿著圖27之A-A線截斷之放大截面圖。
另外，圖5及圖6中，為了示出正向焊接方式之引線BWa和逆向焊接方式之引線BWb之環形形狀不同，分別用雙點虛線標出了圖5之引線BWb和圖6中之引線BWa。另外，圖7係圖3之半導體晶片2所具有之四個邊中，將沿著邊S1配置之焊點群之一部分放大之平面圖；圖8係將沿著邊S3配置之焊點群之一部分進行放大後之平面圖。圖7及圖8所示之焊點BF中，雖然還形成有用於對金屬圖案進行電鍍之供電線，但為了使圖面簡單易懂，圖中並未示出所述供電線。另外，圖7及圖8中，在與引線BW重合之位置上還形成有圖4所示之佈線3r，但是為了使圖面簡單易懂，圖中並未示出佈線3r之符號。關於佈線3r及供電線之佈局例，將在後文之圖11中詳述。
如圖3所示，本實施方式中，複數個焊盤PD和複數個焊點BF分別經由複數條引線BW彼此電連接。引線BW為一端與焊盤PD連接，另一端與焊點BF連接之金屬細線。按連接順序之不同，將半導體晶片2和佈線基板3進行電連接時之引線焊接方法可分為以下兩種。
首先為所謂正向焊接方式，即以第1焊盤側(先連接之引腳)為半導體晶片2之焊盤PD，以第2焊盤側(後連接之引腳)為佈線基板3之焊點BF。其次還有所謂逆向焊接方式，即以第1焊盤側為佈線基板3之焊點BF，以第2焊盤側為半導體晶片2之焊盤PD。
為正向焊接方式時，與圖5中之引線BWa一樣，在第1焊盤側即半導體晶片2之焊盤PD上，如通過球焊方式與引線BW之一端連接。球焊方式中，將形成於引線尖端之球形金屬塊即球形部Bnd1與焊盤PD接觸，並通過圖中未示出之劈刀進行衝壓，以使焊盤PD與球形部Bnd1鍵合。此時，從劈刀施加超音波，便可提高焊盤PD和球形部 Bnd1之間之接合性。
另外，如通過點焊方式，將位於球形部Bnd1相反側之端部與第2焊盤側即佈線基板3之焊點BF連接。採用點焊方式時，在使引線BW之一部分與第2焊盤側即焊點BF接觸後，通過圖中未示出之劈刀將引線BW向焊點BF衝壓，同時還使其沿著焊點BF之延伸方向移動。根據所述劈刀之動作，在引線BW之第2焊盤側之端部上引線BW因被衝壓而塑性變形，從而形成針腳部Bnd2。
相反地，為逆向焊接方式時，如圖6之引線BWb所示，由於佈線基板3之焊點BF成為第1焊盤側，所以引線BW之一個端部通過球焊方式與佈線基板3之焊點BF連接。換言之就是，焊點BF與球形部Bnd1連接。另外，與成為第2焊盤側之半導體晶片2之焊盤PD之連接部上，通過點焊方式與引線BW之另一端部連接。
如上所述，由於為球形部Bnd1時係將球形金屬塊衝壓到被連接部上的，所以如圖7所示，平面形狀呈圓形(包括橢圓形)。另一方面，針腳部Bnd2係在將引線BW向焊點BF衝壓之同時，沿著焊點BF之延伸方向移動而形成的，所以如圖7所示，平面形狀成為半橢圓形(包括半圓形)。
此時，通過點焊方式將引線BW與圖3所示之半導體晶片2之焊盤PD連接時，也可使引線BW直接與焊盤PD連接。此時，將圖6所示之針腳部Bnd2與焊盤PD接合。但在採用點焊方式時，如上所述，將引線BW之一部分與連線對象衝壓之同時，通過使圖中未示出之劈刀按平面方向移動，便可提高連接強度。因此，為了減小因劈刀之動作而向半導體晶片2之焊盤PD週邊施加之應力，如圖6所示，優選在焊盤PD和針腳部Bnd2之間介有突起電極BMP之結構。突起電極BMP為以在焊盤PD上突出之方式形成之突起電極，如由金(Au)構成。由金構成之突起電極BMP也可通過上述球焊方式來形成。即，在將形成於引 線端部之球狀部分(球形部)與焊盤PD接合後，在接合部分附近將引線切斷。由此，便可形成突起電極BMP。
另外，本實施方式中，圖3所示之複數條引線BW中具有通過正向焊接方式形成之引線BWa、以及通過逆向焊接方式形成之引線BWb。同時採用正向焊接方式和逆向焊接方式理由有各種各樣，本實施方式中採用了如下方式，即下段側之類比晶片FC與正向焊接方式之引線BWa連接，上段側之控制晶片CC與逆向焊接方式之引線BWb連接。
如圖6所示，通過逆向焊接方式形成之引線BWb配置在第2焊盤側之位置比第1焊盤側之位置高(相對來說配置在封裝體4之上表面4a附近)之位置上。因此，將與配置在上段側之半導體晶片2連接之引線BW全部通過逆向焊接方式來形成，便可降低引線BWb之引線高度，並可使封裝體4之厚度變薄。另一方面，由於下段側之半導體晶片2之焊盤PD配置在比上段側之半導體晶片2之焊盤低之位置上，所以即使如圖5所示通過正向焊接方式形成，引線BWa線圈之最高點配置在比引線BWb之線圈之最高點低之位置上。因此，通過正向焊接方式形成與下段側之半導體晶片2連接之引線BW，便無需形成突起電極BMP(請參照圖6)等，從而可提高生產效率。
另外，如圖3所示，本實施方式中半導體裝置1於俯視時，沿著半導體晶片2各邊分別配置有複數個焊點BF。沿著各邊配置之焊點BF數量可適用於各個變形例，如圖3所示之示例中，沿著半導體晶片2之邊S1配置之焊點BF之數量比沿著其他邊即邊S2、S3、S4配置之焊點BF之數量多。如上所述，由於焊點BF為半導體裝置1內部介面用之引腳，所以，為了應對半導體晶片2之電路佈局，沿著半導體晶片2各邊配置之焊點BF數量有時也不同。
本實施方式之示例中，配置在下段側之類比晶片FC所具有之複數個焊盤PD中，邊S1側上密集地配置有向類比電路輸入輸出開關信 號之焊盤PD。如上所述，通過將信號輸入輸出用之焊盤PD沿著半導體晶片2一邊密集配置，便可更加容易實現信號傳送距離之等長化。另外，配置在上段側之控制晶片CC所具有之複數個焊盤PD中，與類比晶片FC之間進行信號輸入輸出之焊盤PD優選配置為比類比晶片FC和控制晶片CC之傳送距離短之配置方式。結果，控制晶片CC所具有之複數個焊盤PD中之一部分沿著控制晶片CC之邊S1配置。而且，與沿著控制晶片CC之邊S1配置之焊盤PD連接之引線BWb與沿著類比晶片FC之邊S1配置之焊點BF連接。另外，為了使控制晶片CC具有通用性，控制晶片CC之複數個焊盤PD沿著控制晶片CC之各邊配置。因此，與控制晶片CC連接之複數條引線BW中之一部分與佈線基板3之複數個焊點BF中，沿著半導體晶片2之邊S1配置之焊點BF連接。
如上所述，本實施方式中，沿著半導體晶片2之邊S1配置之複數個焊點BF比沿著邊S2、S3、S4配置之焊點BF數量多。而且，與沿著半導體晶片2之邊S1配置之焊點BF連接之複數條引線BW同時具有正向焊接方式之引線BWa和逆向焊接方式之引線BWb。
此時，如果焊點BF數量過多，為了抑制半導體裝置1整體之平面尺寸增大，就必須縮小所述焊點BF之寬度及配置間隔。例如在圖3所示之複數個焊點群中，將沿著半導體晶片2之邊S1配置之焊點群之焊點BF之寬度設置為比沿著邊S2、S3、S4配置之焊點群之焊點BF之寬度窄。
通過球焊方式將焊點BF與引線BW進行連接時，從穩定線圈形狀方面來考慮，或者從為了提高引線BW與焊點BF之間之接合強度方面來考慮，優選加大球形部Bnd1(請參照圖6)與焊點BF之間之接合面積。如圖27所示，於俯視時，與球形部Bnd1之一部分從焊點BF被擠壓出之狀態相比，如圖7所示整個球形部Bnd1與焊點BF重合時可加大球形部Bnd1與焊點BF之間之接合面積。
具體如圖28所示，在與延伸方向垂直相交之方向上將焊點BF切斷時之截面形狀成為不等邊四邊形。即，與焊點BF之引線BW之接合面即上表面之寬度Wtp比下表面(與佈線基板3之上表面3a接合之面)之寬度Wbt小。例如，如果設計尺寸為55μm，在將下表面之寬度Wbt設置為55μm時，上表面之寬度Wtp就為40μm左右。因此，在球形部Bnd1之寬度與焊點BF設計尺寸相同時，則在球形部Bnd1與焊點BF之接合面中，球形部Bnd1之一部分將被擠壓出。此時，球形部Bnd1寬度係指於俯視時，與引線BWb(請參照圖7)延伸方向垂直相交之方向上之球形部Bnd1之長度。如果將球形部Bnd1之平面形狀看作圓形時，球形部Bnd1之寬度也可說是球形部Bnd1之直徑。
另一方面，通過點焊方式將焊點BF與引線BW進行連接時，如上所述，在壓住引線BW一部分之同時，使劈刀沿著焊點BF之延伸方向移動以進行接合。因此，即使焊點BF之寬度變窄也沒問題，只需可確保焊點BF之延伸距離便可。另外，如圖28所示，如果針腳部Bnd2之寬度比球形部Bnd1之寬度小時，針腳部Bnd2將難於從焊點BF被擠壓出。此時，針腳部Bnd2之寬度係指於俯視時，在與引線BWa(請參照圖7)延伸方向垂直相交之方向上之針腳部Bnd2之最大長度。在將針腳部Bnd2之平面形狀看作半圓形時，針腳部Bnd2之寬度也可說是針腳部Bnd2之直徑。
本案發明人對如下實施方式進行了研究，即如圖29所示，將與球形部Bnd1連接之焊點BF2之寬度W2設為比與針腳部Bnd2連接之焊點BF1之寬度W1大，且排成一行。如圖29所示之實施方式中，球形部Bnd1與焊點BF之接合面積比圖27所示之接合面積大。另外，由於係選擇性地加大與球形部Bnd1連接之焊點BF2之寬度，所以與加大所有焊點BF寬度之實施方式相比，可有效抑制封裝之平面尺寸增大。但是如果將圖29所示之實施方式與圖27所示之實施方式進行比較，由於 焊點群之長度(圖29所示之Y方向上之長度)變大，所以將導致封裝之平面尺寸變大。
因此，本案發明人對如下實施方式進行了研究，即如圖30所示，將複數個焊點BF排列成多行，即按所謂之字形進行排列之實施方式進行了研究。圖30所示之實施方式中，由於各個焊點BF寬度都將變大，所以球形部Bnd1與焊點BF之間之接合面積比圖27所示之實施方式中之接合面積大。另外，通過將焊點BF配置為多行，便可減小焊點群之長度，所以可抑制封裝之平面尺寸增大。
但是，如果如圖30所示，在第1行配置行Bd1和第2行配置行Bd2上分別通過點焊方式與引線BWa連接時，有可能導致與第2行配置行Bd2連接之引線BWa之一部分接觸到第1行配置行之焊點BF之一部分。而且，如果將配置為多行之焊點BF之間之間隔距離縮小，越縮小則越容易導致引線BWa和焊點BF接觸之現象。換言之就是，為了抑制出現引線BWa和焊點BF接觸之現象，就必須增大第1行配置行Bd1和第2行配置行Bd2之間之間隔距離。結果，根據圖30所示之實施方式將導致封裝之平面尺寸增大之現象。
根據上述研究結果，本案發明人對圖7所示之實施方式進行了探討。本實施方式中，如圖7所示，在配置有複數個焊點BF之焊點群中，焊點BF被配置為多行。首先，在距離圖3所示之半導體晶片2之邊S1相對較近之第1行配置行Bd1上形成有點焊用之焊點BF1。其次，在第2行配置行Bd2上形成有球焊用之焊點BF2，其中，所述第2行配置行Bd2距圖3所示之半導體晶片2之邊S1之距離相對來說比第1行配置行Bd1遠。另外，第2行上並沒形成有點焊用之焊點BF1。換言之就是，本實施方式中，在相對來說離半導體晶片2(請參照圖3)較近之第1行上配置有正向焊接方式用之焊點BF1，相對來說離半導體晶片2較遠之第2行上形成有逆向焊接方式用之焊點BF2。
另外，在焊點BF之配置密度相對較高之焊點群中，通過正向焊接方式與引線BWa連接之第1行焊點BF1於俯視時形成為長方形，而且焊點BF1在延伸方向上之長度L1比與延伸方向垂直相交之方向上之長度(寬度W1)長。圖3所示之示例中，形成半導體晶片2外緣之四個邊中，沿著邊S2、S3、S4配置之焊點群中焊點BF之配置密度比沿著邊S1配置之焊點群中焊點BF之配置密度低。因此，將圖7與圖8進行比較後可知，圖7所示之第1行焊點BF1(與延伸方向垂直相交之方向之長度)之寬度W1比圖8中不同之焊點群中焊點BF之寬度W3小。
如上所述，通過將形成於焊點BF之配置密度較高區域中之焊點BF1之寬度W1縮小，即使如圖7所示在配置行Bd1上形成有複數個焊點BF1，也可抑制封裝之平面尺寸增大(即可抑制圖7中Y方向之長度增大)。
另外，本實施方式中，在一個開口部SRp內還形成有包括焊點BF1及焊點BF2之複數個焊點BF。例如，如圖3所示之示例中，在每一個由複數個焊點BF構成之焊點群中都形成有一個開口部SRp。換言之就是，一個焊點群中，相鄰焊點BF之間並沒配置有阻焊膜SR。如上所述，通過採用在一個開口部SRp內配置有複數個複數個焊點BF之結構，便可縮短相鄰焊點BF之間之間隔。結果，即使在圖7所示之配置行Bd1上形成有複數個焊點BF1，也可抑制封裝之平面尺寸增大(即可抑制圖7中Y方向之長度增大)。但是，在焊點BF之配置空間較寬裕之區域中，也可在一個焊點群中形成複數個開口部SRp。例如，如圖3所示之示例中，沿著半導體晶片2之邊S2、邊S3、邊S4配置之焊點群中，可配置有複數個開口部SRp。
另外，如果將第1行焊點BF1和第2行焊點BF2之寬度方向進行比較，第1行焊點BF1之寬度W1比第2行焊點BF2之寬度W2(圖7中為Y方向上之長度)小。換言之就是，焊點BF2之寬度W2比焊點BF1之寬度 W1大。例如，在圖7所示之示例中，焊點BF1之寬度W1之設計尺寸為55μm左右時，焊點BF2之寬度W2之設計尺寸就為80μm左右。如對圖28所示之示例進一步說明，即焊點BF1(請參照圖7)上表面之寬度Wtp為40μm左右，焊點BF2(請參照圖7)上表面之寬度Wtp為60μm左右。
因此，如圖7所示，即使在引線BWb之球形部Bnd1之寬度(直徑)比引線BWa之針腳部Bnd2之寬度(與引線BW延伸方向垂直相交之方向之長度)大時，也可使球形部Bnd1整個下表面與焊點BF2接合。例如，如果球形部Bnd1之寬度不滿60μm，便可使球形部Bnd1整個下表面與焊點BF之上表面接合。即，根據本實施方式，可充分加大與球形部Bnd1連接之焊點BF2之寬度，因此可加大球形部Bnd1與焊點BF2之間之接合面積。結果，便可保持線圈形狀穩定。或者可提高引線BW與焊點BF之間之接合強度。
另外，本實施方式中，逆向焊接方式用之焊點BF2配置在與配置有正向焊接方式用之焊點BF1之第1行配置行Bd1上之不同位置上(圖7示例中為不與配置行Bd2重合之配置行Bd2上)。因此，便可減小焊點群之延伸方向(圖7中為Y方向)上之長度。另外，不在第2行中進行正向焊接方式之引線焊接。如為逆向焊接方式時，相對於第1焊盤側之連接對象，引線BW之傾斜角度可接近90度。例如，在圖6所示之焊點BF2附近，引線BWb相對於焊點BF2之上表面之傾斜角度(約90度)比在圖5所示之焊點BF1附近，引線BWa相對於焊點BF1之上表面之傾斜角度(約20度)大。因此，根據本實施方式，即使縮小了第1行和第2行之間之隔離距離，與焊點BF2連接之引線BWb也難於與第1行焊點BF1接觸。換言之就是，根據本實施方式，可縮近第1行焊點BF1和第2行焊點BF2之間之距離。所以即使如上所述，將焊點BF配置為多行時，只需縮近各行間之距離，便可抑制封裝之平面尺寸增大(即圖7中X方向之增大)。
另外，由於圖7中之焊點BF2係用於進行球焊之引腳，所以其延伸距離可縮短為比點焊用之焊點BF1短。圖7所示之示例中，焊點BF2之平面形狀例如為圓形。因此，焊點BF2在延伸方向上之長度L2比焊點BF1在延伸方向上之長度小(短)。另外，焊點BF2在延伸方向上之長度L2於俯視時，為焊點BF2在與焊點BF2連接之引線BWa之延伸方向平行之方向上之最大長度。因此，圖7所示之焊點BF2之平面形狀為圓形時，長度L2與寬度W2相同。通過縮短焊點BF2之長度L2，便可抑制封裝之平面尺寸增大(即可抑制圖7中X方向之長度增大)。另外，圖7之示例為第1行配置行Bd1整體不與第2行配置行Bd2之整體重合之示例，但在變形例中，也可以使第1行配置行Bd1之一部分與第2行配置行Bd2之一部分重合之方式使其相互靠近。換言之就是，如可在Y方向上，以使焊點BF1之一部分與焊點BF2之一部分重合之方式靠近配置。
<半導體裝置之製造方法>
下面對圖1至圖8中所說明之半導體裝置1之製造方法進行說明。本實施方式之半導體裝置1為通過圖9所示之組裝流程製造而成。圖9係本實施方式中半導體裝置組裝流程之說明圖。
1.基板之準備製程
首先，在圖9所示之基板準備製程中，準備圖10所示之佈線基板25。圖10係在圖9之基板準備製程中所準備之佈線基板之整體結構之平面圖。圖11係在圖10所示之複數個器件形成部之一個中，與圖7所示區域對應之部分之放大平面圖。
如圖10所示，本製程所準備之佈線基板25在框部25b內側具有複數個器件形成部25a。具體地說就是在框部25b內側按行列狀配置有複數個器件形成部25a。器件形成部25a數量不受圖10所示之方式限定，本實施方式中佈線基板25例如具有按行列狀配置之16個器件形成部 25a(圖10中為2列×8行)。也就是說，佈線基板25為具有複數個器件形成部25a之所謂複數個可斷拼板。
另外，各器件形成部25a週邊還配置有在圖9所示之劃片製程中將佈線基板25進行切斷之預先切斷區域，即切割部(切割線)25c。如圖10所示，切割部25c以圍住相鄰器件形成部25a之間、以及框部25b和器件形成部25a之間之各器件形成部25a之方式配置。
各器件形成部25a相當於圖3及圖4所示之佈線基板3。各器件形成部25a具有：圖4所示之上表面(晶片搭載面)3a、形成於上表面3a上之複數個焊點(引腳、晶片搭載面側引腳、焊接引線)BF、位於上表面3a相反側之下表面(安裝面)3b、以及形成於下表面3b上之複數個焊接盤(引腳、外部引腳)LD。複數個焊點BF與圖4所示之複數個焊接盤LD分別經由形成于各器件形成部25a上之複數條佈線3r而被電連接。
另外，如圖11所示，佈線基板25之上表面3a中，複數個焊點BF分別與佈線3r及供電線3p連接。在通過電焊法形成焊點BF及佈線3r等金屬圖案時，圖11所示之供電線3p將被用作供電線，並以朝向圖10所示之切割部25c延伸之方式形成。焊點BF、佈線3r及供電線3p以覆蓋以銅(Cu)為主成分之基材之表面之方式形成如由鎳(Ni)等構成之電鍍膜。
另外，圖11中列出了複數個焊點BF分別與供電線3p連接之示例，作為變形例之一例，也可以為複數個焊點BF中一部分與供電線3p連接，而其他部分不與供電線3p連接之方式。供電線3p及佈線3r之寬度(與延伸方向垂直相交之方向之長度)比焊點BF1之寬度W1小。
圖11所示之複數個焊點BF之形狀及佈局之詳細內容與通過圖7之內容一致，所以在此不再進行重複說明。
2.半導體晶片之準備製程
圖9所示之半導體晶片之準備製程中，準備圖4所示之複數個半導 體晶片2即類比晶片FC及控制晶片CC之製程。本製程中，準備如下之半導體晶片，即在由矽構成之半導體晶片(圖中未示出)之主面側上由複數個半導體元件或與其電連接之佈線層構成之半導體晶片。類比晶片FC上形成有類比電路、控制晶片CC上形成有對類比電路進行控制之控制電路。
另外，本製程中，如圖6所示通過逆向焊接方式與引線BW連接之焊盤上，優選在焊盤PD上形成突起電極BMP。如上所述，本實施方式中，由於上段側搭載之控制晶片CC之各焊盤PD係通過逆向焊接方式與引線BW連接的，所以在控制晶片CC之焊盤PD上預先形成了突起電極BMP。
之後，使劃片刀沿著半導體晶片之切割線移動(圖中未示出)將半導體晶片進行切斷，便可取得複數個圖4所示之類比晶片FC及控制晶片CC。另外，類比晶片FC與控制晶片CC例如可分別從不同半導體晶片取得。
3.晶片黏貼製程
接下來，在圖9所示之晶片黏貼製程中，如圖12及圖13所示，在佈線基板25之器件形成部25a之晶片搭載面上搭載半導體晶片2並將之進行黏接固定。圖12係將半導體晶片搭載到圖10所示之佈線基板上之狀態之放大平面圖，圖13係沿著圖12之A-A線截斷之放大截面圖。
本實施方式中，將複數個半導體晶片2層積在佈線基板25之晶片搭載面上。首先，將配置在下段側之類比晶片FC搭載(黏接固定)於佈線基板25之各器件形成部25a之上表面3a上。器件形成部25a於俯視時為四角形，具有邊S1、位於邊S1相反側之邊S2、與邊S1及邊S2相交之邊S3、以及位於邊S3相反側之邊S4。因此，在圖12所示之示例中，配置有複數個焊點BF之焊點群中，沿著器件形成部25a之邊S1配置之焊點群中焊點BF之配置密度比其他焊點群中焊點BF之配置密度 高。
本製程中，與焊點BF對應(換言之就是，將與其進行電連接)之焊盤PD於俯視時以面對面之方式搭載半導體晶片2。因此，本製程中如圖12所示，分別以使類比晶片FC之邊S1沿著器件形成部25a之邊S1、類比晶片FC之邊S2沿著器件形成部25a之邊S2、類比晶片FC之邊S3沿著器件形成部25a之邊S3、以及類比晶片FC之邊S4沿著器件形成部25a之邊S4之方式將類比晶片FC配置到佈線基板25上。
另外，如圖13所示，本實施方式中，以使類比晶片FC之背面2b面向佈線基板25之上表面3a之方式，經由晶片黏接材料5將類比晶片FC搭載在佈線基板25上，即通過所謂面朝上安裝方式來搭載類比晶片FC。
晶片黏接材料5為將類比晶片FC與佈線基板25進行黏接固定之黏接材料，如在硬化前為膏狀。使用膏狀黏接材料來搭載類比晶片FC時，在搭載半導體晶片2之前，必須事先在器件形成部25a之晶片搭載區域上預先塗抹膏狀黏接材料。接下來通過將類比晶片FC壓進晶片搭載區域使膏狀黏接材料擴散後，再通過加熱等使其硬化，以此來固定類比晶片FC。另外，在晶片黏接材料5完全硬化時，在搭載類比晶片FC後立即搭載控制晶片CC，之後可使其與晶片黏接材料6同時硬化。
接下來如圖12所示，將配置在上段側之控制晶片CC搭載(黏接固定)在類比晶片FC之表面2a上。本製程中，分別以使控制晶片CC之邊S1沿著器件形成部25a之邊S1、控制晶片CC之邊S2沿著器件形成部25a之邊S2、控制晶片CC之邊S3沿著器件形成部25a之邊S3、控制晶片CC之邊S4沿著器件形成部25a之邊S4之方式將控制晶片CC搭載到類比晶片FC上。
另外，如圖13所示，本實施方式中，以使控制晶片CC之背面2b 面向類比晶片FC之表面2a之方式，經由晶片黏接材料6將控制晶片CC搭載到類比晶片FC上，即以所謂面朝上安裝方式來搭載控制晶片CC。如上所述，晶片黏接材料6係一種將各半導體晶片2進行黏接固定之黏接膜，如通過使被稱為DAF之樹脂膜等硬化後將上下段之半導體晶片2進行黏接固定。此時，例如預先在控制晶片CC之背面2b貼上雙面都是黏接層之黏帶(黏接膜)即晶片黏接材料6，再經由黏帶將控制晶片CC進行黏接。之後，通過使晶片黏接材料6中所具有之熱硬化性樹脂成分熱硬化來固定控制晶片CC。
4.引線焊接製程
接下來在圖9所示之引線焊接製程中，如圖14及圖15所示，經由複數條引線BW將半導體晶片2之複數個焊盤PD與佈線基板25之複數個焊點BF進行電連接。圖14係通過引線焊接將圖12中之複數個半導體晶片與佈線基板分別進行電連接之狀態之放大平面圖。圖15係通過引線焊接將圖13之半導體晶片和佈線基板進行電連接之狀態之放大截面圖。圖15中，為了示出正向焊接方式之引線BWa和逆向焊接方式之引線BWb環形之不同，用雙點虛線表示引線BWb，之後其他截面圖也同樣。圖16係在通過正向焊接方式焊接之第1焊盤側中，將球形部接合到焊盤之狀態之放大截面圖。圖17係在通過正向焊接方式焊接之第2焊盤側中，將針腳部接合到焊點之狀態之放大截面圖。圖18係在通過逆向焊接方式焊接之第1焊盤側中，將球形部接合到焊點之狀態之放大截面圖。圖19係在通過逆向焊接方式焊接之第2焊盤側中，將針腳部接合到突起電極之狀態之放大截面圖。
本製程中，如圖14及圖15所示，經由複數條引線BWa並通過正向焊接方式將形成於佈線基板25之器件形成部25a上之複數個焊點BF中之一部分與形成於類比晶片FC之表面2a上之複數個焊盤PD分別進行電連接。另外，本製程中，還經由複數條引線BWb並通過逆向焊接方 式將複數個焊點BF中之其他部分與形成於控制晶片CC之表面2a上之複數個焊盤PD(具體地說就是形成於焊盤PD上之突起電極BMP)分別進行電連接。
為正向焊接方式時，如圖16所示，首先通過球焊方式在第1焊盤側即半導體晶片2之焊盤PD上與引線BW之一端連接。球焊方式係指如圖16之箭頭CP1所示，將形成於引線BW尖端之球形金屬塊即球形部Bnd1與焊盤PD接觸，並通過劈刀CP衝壓使焊盤PD與球形部Bnd1進行鍵合。此時，有時也會從劈刀CP施加超音波，以此提高焊盤PD和球形部Bnd1之間之接合性。球形部Bnd1係通過在劈刀CP所保持之引線BW之尖端上通過圖中未示出之電焊槍放電而形成球形。另外，如果將球形之球形部Bnd1向焊盤PD衝壓，將按劈刀CP尖端部之形狀形成球形部Bnd1。本實施方式中，雖然將第1焊盤側之尖端部稱為球形部Bnd1，但由於球形部Bnd1係按上述方式形成的，所以在與被連接部連接之狀態下，球形部Bnd1之形狀並不一定為球形。
接下來如圖16之箭頭CP2所示，從劈刀CP拉長引線BW，同時劈刀CP還朝向第2焊盤側即焊點BF1運行。具體地說就是，劈刀CP在沿著箭頭CP2之方向移動之前，先在焊盤PD上運行(上升動作)，隨後朝向離開焊點BF之方向動作(倒轉)。通過使劈刀CP進行上述上升動作及倒轉動作，便可如圖17所示，容易在引線BW之第1焊盤側附近進行彎曲加工。
接下來如圖17所示，通過點焊方式將位於引線BW之球形部Bnd1相反側之一端與焊點BF之上表面進行接合。點焊方式係指如圖17之箭頭CP3所示，使引線BW之一部分與第2焊盤側即焊點BF接觸後，使劈刀CP在將引線BW向焊點BF衝壓之同時沿著焊點BF之延伸方向移動。通過使劈刀CP按上述方式進行移動，便可在引線BW之第2焊盤側之端部使引線BW被衝壓並發生塑性變形，從而形成針腳部Bnd2。 此時，引線BW在針腳部Bnd2被切斷，並使劈刀CP所持有之引線BW和與焊點BF接合之引線BW分離。
接下來如圖17之箭頭CP4所示，劈刀朝向焊點BF上移動，並轉移到下一個引線焊接動作。通過上述各製程及正向焊接方式來形成引線BWa。在通過正向焊接方式形成之引線BWa之第2焊盤側中，引線BWa對於焊點BF1之上表面之傾斜角度θ1例如為20度左右。本實施方式中，圖14所示之複數條引線BW中，與下段側之類比晶片FC連接之引線BW都是通過正向焊接方式形成的。
另一方面，如為逆向焊接方式時，如圖18所示，首先通過球焊方式在第1焊盤側即焊點BF2上與引線BW之一端接合。除了被連接對象即焊盤PD換成焊點BF之外，球焊方式之詳細內容與圖16之球焊方式內容相同，所以不再進行重複說明。
接下來如圖18之箭頭CP2所示，從劈刀CP拉長引線BW，同時劈刀CP還朝向焊點BF之上方運行(上升動作)。在逆向焊接方式之上升動作中，在劈刀CP下端到達比半導體晶片2之表面2a之高度還高之位置之前便使劈刀CP上升，因此，上升量比正向焊接方式時上升動作之上升量大。本實施方式中，劈刀CP之上升量至少比圖15所示之類比晶片FC及控制晶片CC之合計厚度大。如上所述，在第1焊盤側進行比正向焊接方式大之上升動作，便可如圖19所示，使引線BWb對於焊點BF1上表面之傾斜角度θ2比圖17所示之傾斜角度θ1大，如為80~90度左右。
接下來如圖18之箭頭CP3所示，從劈刀CP拉長引線BW之同時，劈刀CP還朝向第2焊盤側即半導體晶片2之焊盤PD運行。具體地說就是，劈刀CP在朝著離開焊盤PD之方向上運行(倒轉)後，沿著箭頭CP3方向運行。通過使劈刀CP進行上述倒轉動作，便可如圖19所示，更易在引線BW之第1焊盤側上進行彎曲加工。
接下來如圖19所示，通過點焊方式使位於引線BWb之球形部Bnd1相反側之端部與形成於焊盤PD上之突起電極BMP接合。點焊方式係指如圖19之箭頭CP4所示，在將引線BWb之一部分與第2焊盤側即突起電極BMP接觸後，使劈刀CP在將引線BW向突起電極BMP衝壓之同時沿著引線BW之延伸方向移動。通過使劈刀CP按上述方式移動，便可在引線BW之第2焊盤側之端部形成針腳部Bnd2。此時，引線BW在針腳部Bnd2被切斷，並使劈刀CP所持有之引線BW和與突起電極BMP接合之引線BW分離。為逆向焊接方式時，由於係在半導體晶片2上與針腳部Bnd2接合，所以在形成針腳部Bnd2時所施加外力之大小必須設定為不會造成半導體晶片2上電路元件受損傷之範圍內。
接下來如圖19之箭頭CP5所示，使劈刀上升至焊盤PD上，並移行至下一個引線焊接動作。通過以上各製程便可以逆向焊接方式形成引線BWb。在通過逆向焊接方式形成之引線BWb之第1焊盤側中，引線BWb相對於焊點BF2上表面之傾斜角度θ2如為80~90度左右。本實施方式中，圖14所示之複數條引線BW中，與上段側之控制晶片CC連接之引線BW都係通過逆向焊接方式形成。
如圖7所示，本實施方式中，相對來說位於內側(圖14所示之半導體晶片2一側)之第1行配置行Bd1之焊點BF1中通過正向焊接方式與針腳部Bnd2連接。另一方面，位於第1行外側(圖14中為器件形成部25a之周邊部側)之第2行配置行Bd2之焊點BF2上通過逆向焊接方式與球形部Bnd1連接。因此，本製程中，相對來說配置在內側之複數個焊點BF1分別與引線BWa連接後，優選在外側之焊點BF2上形成引線BWb。
如圖8所示，複數個焊點BF配置為一行之焊點群中，先形成引線BWa或先形成引線BWb都可。
5.封裝製程
接下來在圖9所示之封裝製程中，如圖20所示，通過樹脂對半導體晶片2及複數條引線BW進行封裝。圖20係通過樹脂將圖15所示之半導體晶片及複數條引線進行封裝之狀態之放大截面圖。
本製程中，在具有圖中未示出之膜槽之成型模具內配置有佈線基板25，通過樹脂對佈線基板25之上表面3a側進行封裝後，使樹脂硬化後形成封裝體4，即通過所謂轉送成型方式形成封裝體4。
另外，圖20所示之示例係示出了通過樹脂對成型模具之一個膜槽一次性地覆蓋並進行樹脂封裝，即採用被稱為MAP(Mold Allay Process)方式來形成封裝體4之示例。採用MAP方式時，由於係以覆蓋複數個器件形成部25a之方式形成一體化之封裝體4，所以切割部25c之上也被封裝體4覆蓋。
6.焊接材料形成製程
接下來，在圖9所示之焊接材料形成製程中，如圖21所示，以覆蓋每一個焊接盤LD露出面之方式形成焊接材料7。圖21係在圖20之複數個焊接盤之每一個露出面上形成焊錫後之狀態之放大截面圖。
本製程中，在佈線基板25之下表面3b側中露出之複數個焊接盤LD之每一個露出面上形成焊接材料7。如圖21所示，形成球狀焊接材料7時，將佈線基板25進行上下翻轉，使下表面3b朝向上方之方式配置之狀態下，在焊接盤LD上配置球形焊錫。接下來在對球形焊錫進行加熱並使其熔融後再使其冷卻，便可使複數個焊接材料7分別與焊接盤LD之露出面進行接合。如上所述，對焊錫進行加熱使其熔融後再冷卻之處理方式被稱為回流焊接處理。
另外，本實施方式中，以形成球形之焊接材料7為例進行了說明，但半導體裝置外部引腳之樣態還有各種變形例。如在電鍍法或在塗布膏狀焊錫之後，通過回流焊接處理，便可如圖21所示形成比焊接材料7更薄之焊接材料。另外，在沒形成焊接材料7之變形例中，也可 省略本製程。
7.劃片製程
接下來在圖9所示之劃片製程中，如圖22所示，對佈線基板25之器件形成部25a按個進行切割，便可取得複數個半導體裝置1。圖22係通過劃片刀將圖21之佈線基板進行切斷後之狀態之放大截面圖。
本製程中，如圖22所示，使劃片刀(旋轉刃)DBL沿著切割部(切割線)25c移動，以將佈線基板25及封裝體4進行切斷(分割)，佈線基板25按器件形成部25a被切斷。複數個器件形成部25a被從各相鄰之器件形成部25a及框部25b切斷後，便可取得複數個半導體裝置1。具體地說就是，在本製程之後，通過外觀檢查、電性測試等必要檢查及驗證後，合格產品便成為圖1~圖8中所說明之半導體裝置1。之後，半導體裝置1便可作為成品輸出、或者被安裝在圖中未示出之安裝基板上。
<變形例>
以上根據實施方式具體地說明了本案發明人所作之發明，但本發明並不受到所述實施方式之限定，在不超出其要旨之範圍內能夠進行種種變更，在此無需贅言。
(變形例1)
圖7所示之示例中，複數個焊點BF中球焊方式用之焊點BF2之平面形狀為圓形。如果將焊點BF2之平面形狀設為圓形，就可使與球形部Bnd1之接合面積最大化，且使焊點BF2之佔有面積最小化。焊點BF2之平面形狀還可有多種變形例，如可為四角形、五角形等。圖23所示之變形例中半導體裝置1A所具有之焊點BF2包括平面形狀為圓形之圓形部Fp1、以及與圓形部Fp1聯接且沿著引線BW之延伸方向延伸之延伸部Fp2。圖23係圖7之變形例之放大平面圖。
圖23所示之半導體裝置1A所具有之焊點BF2之圓形部Fp1與圖7所 示之半導體裝置1所具有之焊點BF2對應。即，圖23所示之圓形部Fp1配置在與配置有複數個焊點BF1之配置行Bd1之上之不同位置(圖23中為配置行Bd2)上。另外，圓形部Fp1之寬度W2比焊點BF1之寬度W1大，其設計尺寸如為80μm左右。因此，如果將圓形部Fp1中央與球形部Bnd1進行連接，便可使球形部Bnd1與圓形部Fp1之接合面積最大化。
圖23中半導體裝置1A所具有之焊點BF2之延伸部Fp2之形狀及佈局與配置在焊點BF2相鄰位置上之焊點BF1對應。即，圖23所示之延伸部Fp2設置在配置有複數個焊點BF1之配置行Bd1上。另外，延伸部Fp2之寬度(與延伸方向垂直相交之方向之長度)W4之設計尺寸與焊點BF1之寬度W1相同。另外，延伸部Fp2在延伸方向上之長度L3比焊點BF1在延伸方向上之長度L1長。
也就是說，圖23中半導體裝置1A所具有之焊點BF2為與圓形部Fp1及延伸部Fp2一體形成之形狀，其中，所述圓形部Fp1與圖7所示之半導體裝置1所具有之焊點BF2對應、所述延伸部Fp2與焊點BF1對應。本變形例中，如果焊點BF2通過逆向焊接方式與引線BW連接時可將圓形部Fp1與引線BW之球形部Bnd1連接，如果通過正向焊接方式將焊點BF2與引線BW連接時可將延伸部Fp2與引線BW之針腳部Bnd2進行連接。也就是說，可提高佈線基板3之通用性。
另外，雖然圖中未示出，圖23之另一變形例之結構為圓形部Fp1上與引線BWb之球形部Bnd1連接、且延伸部Fp2上與引線BWa之針腳部Bnd2連接。此時，由於可減小圖4中上段側之控制晶片CC和下段側之類比晶片FC之間之傳送距離，所以可提高其電特性。
但是，圖23所示之變形例中，相鄰焊點BF1之間必須要確保焊點BF2延伸部之配置空間，所以從縮短圖23中Y方向上封裝之長度方面來考慮，優選圖7所示之結構。
(變形例2)
另外，例如在一個封裝內既有通過正向焊接方式形成之引線BWa也有通過逆向焊接方式形成之引線BWb時，對層積了複數個半導體晶片2之實施方式進行了說明。但是，如果封裝內配置之半導體晶片2只有一個，在一個封裝內也有可能同時存在通過正向焊接方式形成之引線BWa和通過逆向焊接方式形成之引線BWb。圖24係在圖3所示之半導體裝置之變形例中，半導體晶片所具有之複數個焊盤和佈線基板之複數個焊點之連接關係之模式放大平面圖。圖25係圖24之變形例之放大平面圖。圖26係圖24之其他變形例之放大平面圖。
圖24所示之半導體裝置1B、圖25之半導體裝置1C以及圖26之半導體裝置1D之共通點係在一個封裝內都內置有一個半導體晶片2，而且都具有正向焊接方式之引線BWa和逆向焊接方式之引線BWb。
首先，圖24所示之半導體裝置1B之半導體晶片2之焊盤PD被配置為多行，這是與所述實施方式不同之處。具體地說就是，圖24所示之半導體晶片2具有沿著邊S1配置之複數個焊盤PD。而且，所述複數個焊盤PD包括焊盤PD1和焊盤PD2，所述焊盤PD1設置在相對來說離側面2c(換言之就是邊S1)較近之位置上，所述焊盤PD2設置在距側面2c(換言之就是邊S1)之距離比焊盤PD1遠之位置上。
通過引線BW將與焊盤PD2一樣距離半導體晶片2之側面2c較遠之焊盤PD進行連接時，如果採用正向焊接方式，則有可能導致半導體晶片2之周邊部與引線BW發生接觸之現象。換言之就是，為了防止出現半導體晶片2之周邊部與引線BW出現接觸之現象，必須將通過正向焊接方式形成之環狀加大，因此將導致封裝之厚度及平面尺寸增大。此時，與通過正向焊接方式相比，採用逆向焊接方式時，具有使引線BW難於接觸到半導體晶片2之周邊部之優點。因此，如果擔心引線BW與半導體晶片2周邊部接觸時，優選採用逆向焊接方式。例如，於 俯視時，如果引線BW全長1/4以上之部分與半導體晶片2之厚度方向重合時，優選採用逆向焊接方式。相反地，由於正向焊接方式之作業效率比逆向焊接方式好，所以對於引線BW與半導體晶片2接觸幾率小之焊盤PD1，優選採用正向焊接方式進行連接。另外，與逆向焊接方式相比，採用正向焊接方式時更能縮短焊點BF之寬度，所以如果從提高焊點BF之配置密度方面考慮，採用正向焊接方式比較有利。
因此，即使在沒層積有複數個半導體晶片2之實施方式中，在與半導體晶片2連接之複數條引線BW中即使包括通過正向焊接方式連接之引線BWa、以及通過逆向焊接方式連接之引線BWb時，也優選適用上述實施方式中所說明之技術。
接下來，圖25所示之半導體裝置1C於俯視時，引線BWb在與開口部SRp重合之位置上跨過其他信號用(或者電位供給用)之佈線3r，這方面與圖24所示之半導體裝置1B有所不同。流經圖25所示之其他信號用之佈線3r之電流與流經引線BWb之電流不同。在欲增加焊點BF數量時，有可能導致與焊點BF連接之佈線3r佈局複雜化之傾向。因此，如圖25所示，根據佈線3r之佈局方式，有時會將引線BW設置為跨過其他信號用之佈線3r之方式。另外，如上所述，通過在一個開口部SRp內設置複數個焊點BF，便可提高焊點BF之配置密度，所以如圖25所示，有時會以在在與開口部SRp重合之位置上以跨過其他信號用之佈線3r之方式配置引線BW。此時，如果通過正向焊接方式將跨過佈線3r之引線BW進行連接時，有可能導致佈線3r與引線BW接觸之現象。因此，如圖25所示，跨過其他信號用之佈線3r之引線BW優選採用逆向焊接方式進行連接。
因此，半導體裝置1C所具有之複數條引線BW包括通過正向焊接方式連接之引線BWa、以及通過逆向焊接方式連接之引線BWb。因此，半導體裝置1C也優選適用上述實施方式中所說明之技術。
接下來，圖26所示之半導體裝置1D中，於俯視時，引線BWb以跨過其他之引線BWa之方式設置，這方面與圖24所示之半導體裝置1B有所不同。隨著半導體晶片2之高功能化，電路也將變複雜化，所以有可能出現如圖26所示之情況，即於俯視時一部分引線BW與其他之引線BW相交之情況。此時，通過逆向焊接方式與引線BW之一端進行連接，便可抑制引線BW之間出現接觸之現象。
因此，半導體裝置1D所具有之複數條引線BW包括通過正向焊接方式連接之引線BWa、以及通過逆向焊接方式連接之引線BWb。因此，半導體裝置1D也優選適用上述實施方式所說明之技術。
(變形例3)
例如，在所述實施方式中，對於沿著半導體晶片2四個邊配置之複數個焊點群中之一部分焊點群中，焊點BF之配置密度變大之情況進行了說明。但也可適用於其變形例，例如對於沿著半導體晶片2四個邊配置之每個焊點群中焊點BF之配置密度都很高時也可適用。在複數個焊點群中，如果焊點BF之配置密度高且同時存在正向焊接方式之引線BWa和逆向焊接方式之引線BWb時，對於複數個焊點群之每一個優選適用所述實施方式中所說明之技術。
(變形例4)
另外，在所述實施方式中，如圖7所示，對於在一個焊點群上設置有複數個焊點BF1及複數個焊點BF2之實施方式進行了說明，但在通過逆向焊接方式連接之焊點BF2只有一個時也可適用。
(變形例5)
另外，在所述實施方式中，在距半導體晶片2之距離相對較近之第1行配置行Bd1上配置焊點BF1，在距半導體晶片2之距離比第1配置行Bd1遠之第2行配置行Bd2上配置有焊點BF2。但也具有在比焊點BF1更靠近半導體晶片2之位置上配置逆向焊接方式用之焊點BF2之變 形例。逆向焊接方式時，由於引線BW之一部分以在焊點BF上延伸之方式形成，所以與正向焊接方式時相比，可將焊點BF之位置更靠近半導體晶片2配置。如果將逆向焊接方式用之焊點BF2靠近半導體晶片2配置，就可加大焊點BF2和焊點BF1之間之隔離距離。結果，便可抑制與焊點BF1連接之引線BWa與逆向焊接方式用之焊點BF2接觸之現象。另外，將焊點BF2靠近半導體晶片2配置，便可抑制從焊點BF1到半導體晶片2之距離增大之現象，所以可抑制平面尺寸增大。
(變形例6)
另外，本實施方式所說明之技術思想在不脫離其要旨之範圍內還可將變形例進行各種組合，在此無需贅言。

Claims (11)

  1. 一種半導體裝置，其包含：佈線基板，其具有絕緣層、形成於上述絕緣層之上表面之複數個引腳、形成於上述絕緣層之上述上表面且分別與上述複數個引腳連接之複數個佈線、及以上述複數個佈線之各個之一部分與上述複數個引腳之各個露出之方式形成於上述絕緣層之上述上表面的絕緣膜；第1半導體晶片，其具有第1表面、形成於上述第1表面之複數個第1電極、及與上述第1表面相反側之第1背面，並以上述第1背面面向上述佈線基板之上述絕緣層之上述上表面之方式搭載在上述佈線基板之上述絕緣層之上述上表面上；及複數條引線(wire)，所述複數條引線分別具有球形部以及針腳部，並分別與上述複數個引腳連接；其中於俯視時，上述球形部之寬度較上述針腳部之寬度大；上述複數條引線具有第1引線、及第2引線；於俯視時，上述複數個引腳係沿上述第1半導體晶片之上述第1表面之第1邊而配置；上述複數個引腳具有與上述第1引線之上述針腳部連接之第1引腳、及與上述第2引線之上述球形部連接之第2引腳；上述複數個佈線具有與上述第1引腳連接之第1佈線、及與上述第2引腳連接之第2佈線；於俯視時，上述第2引腳具有與上述第2引線之上述球形部連接之第1部分、及連接於上述第1部分且沿著上述第2引線之延伸方向而延伸之第2部分；於俯視時，上述第2引腳之上述第1部分係位在與複數個上述第1引腳之配置行上不同之處；於俯視時，上述第2引腳之上述第2部分係設置於複數個上述第1引腳之配置行上；於俯視時，上述第2引線之上述球形部之寬度較上述第1引線之上述針腳部之寬度大；於俯視時，上述第1引腳之寬度較上述第1佈線之上述一部分之寬度大；於俯視時，上述第2引腳之上述第2部分之寬度較上述第2配線之上述一部分之寬度大；於俯視時，上述第2引腳之上述第1部分之寬度較上述第1引腳及上述第2引腳之上述第2部分之各個之寬度大；上述第1佈線之上述一部分、上述第1引線之上述針腳部及上述第1引腳之各個之寬度係與上述第1引線之延伸方向交叉之方向的長度；且上述第2佈線之上述一部分、上述第2引線之上述球形部、上述第2引腳之上述第1部分及上述第2引腳之上述第2部分之各個之寬度係與上述第2引線之延伸方向交叉之方向的長度。
  2. 如請求項1所記載之半導體裝置，其中於俯視時，包含第1部分及上述第2部分之上述第2引腳之延伸方向上之上述第2引腳之上述第1部分之長度較上述第1引腳之延伸方向上之上述第1引腳之長度小。
  3. 如請求項2所記載之半導體裝置，其中於俯視時，包含上述第1部分及上述第2部分之上述第2引腳之延伸方向上之上述第2引腳之上述第1部分之長度較包含上述第1部分及上述第2部分之上述第2引腳之延伸方向上之上述第2引腳之上述第2部分之長度小。
  4. 如請求項1所記載之半導體裝置，其中在上述第1半導體晶片之上述第1表面上搭載有：第2半導體晶片，其具有與上述第1半導體晶片之上述第1表面對向之第2背面、與上述第2背面相反側之第2表面、及形成於上述第2表面之第2電極；上述第1引線之上述球形部係與上述第1半導體晶片之上述第1電極連接；上述第2引線之上述針腳部與上述第2半導體晶片之上述第2電極連接。
  5. 如請求項1所記載之半導體裝置，其中上述第2引腳之上述第1部分之平面形狀為圓形。
  6. 如請求項1所記載之半導體裝置，其中沿著上述第1半導體晶片之上述第1表面之第1邊配置之上述複數個第1電極具有：第3電極、及第4電極；上述第4電極與上述第1邊之間隔距離較上述第3電極與上述第1邊之間隔距離大；上述第1引線之上述球形部係與上述第3電極連接；且上述第2引線之上述針腳部係與上述第4電極連接。
  7. 如請求項1所記載之半導體裝置，其中沿著上述第1半導體晶片之上述第1表面之第1邊配置之上述複數個第1電極具有：第3電極、及第4電極；上述第1引線之上述球形部係與上述第3電極連接；上述第2引線之上述針腳部係與上述第4電極連接；上述複數個引腳係在形成於上述絕緣膜之一個開口部中從上述絕緣膜露出；於上述開口部，配置有第3佈線，上述第3佈線流動之電流與流至上述第2引線之電流不同；且於俯視時，上述第2引線係在與上述開口部於厚度方向重合之位置，以跨過上述第1佈線之方式設置。
  8. 如請求項1所記載之半導體裝置，其中沿著上述第1半導體晶片之上述第1表面之第1邊配置之上述複數個第1電極具有：第3電極、及第4電極；上述第1引線之上述球形部係與上述第3電極連接；上述第2引線之上述針腳部係與上述第4電極連接；且上述第2引線係以跨過上述第1引線中之一部分之方式設置。
  9. 如請求項1所記載之半導體裝置，其中於俯視時，上述第1引線之延伸方向上之上述第1引腳之長度較上述第1引腳之寬度大。
  10. 如請求項1所記載之半導體裝置，其中上述第1引腳之數目較上述第2引腳之數目多；且於俯視時，上述第2引腳之上述第2部分位在較上述第2引腳之上述第1部分更靠近上述第1半導體晶片之處。
  11. 如請求項1所記載之半導體裝置，其中於俯視時，上述第2引腳之上述第2部分之寬度與上述第1引腳之寬度相同。
TW103125751A 2013-07-30 2014-07-28 半導體裝置 TWI631680B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-158233 2013-07-30
JP2013158233A JP6196092B2 (ja) 2013-07-30 2013-07-30 半導体装置

Publications (2)

Publication Number Publication Date
TW201505145A TW201505145A (zh) 2015-02-01
TWI631680B true TWI631680B (zh) 2018-08-01

Family

ID=52426950

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103125751A TWI631680B (zh) 2013-07-30 2014-07-28 半導體裝置

Country Status (6)

Country Link
US (2) US9281289B2 (zh)
JP (1) JP6196092B2 (zh)
KR (1) KR20150014867A (zh)
CN (2) CN109037184B (zh)
HK (1) HK1206869A1 (zh)
TW (1) TWI631680B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法
JP6991014B2 (ja) 2017-08-29 2022-01-12 キオクシア株式会社 半導体装置
TWI739379B (zh) * 2019-04-24 2021-09-11 日商新川股份有限公司 半導體裝置、半導體裝置的製造方法、以及打線接合裝置
CN110265378B (zh) * 2019-06-19 2020-10-23 福建福顺半导体制造有限公司 一种电子元件
KR20210090521A (ko) * 2020-01-10 2021-07-20 에스케이하이닉스 주식회사 본딩 와이어 분지 구조를 포함한 반도체 패키지
KR20220007444A (ko) 2020-07-10 2022-01-18 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US20220238488A1 (en) * 2021-01-28 2022-07-28 Qualcomm Incorporated Circular bond finger pad

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105851A (ja) * 1984-10-30 1986-05-23 Toshiba Corp ワイヤボンデイング方法
JP2001156107A (ja) * 1999-11-30 2001-06-08 Rohm Co Ltd Ｉｃチップ、およびこれの導体ワイヤ接続方法
JP2002184805A (ja) * 2000-12-15 2002-06-28 Oki Data Corp 半導体装置およびワイヤボンディング方法
US20050258549A1 (en) * 2003-06-18 2005-11-24 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
JP2008171927A (ja) * 2007-01-10 2008-07-24 Renesas Technology Corp 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06103697B2 (ja) * 1988-06-25 1994-12-14 日本電気株式会社 コンパクトｉｃのワイヤボンディング構造体
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP2002237567A (ja) * 2001-02-09 2002-08-23 Nec Corp 半導体装置
US7042073B2 (en) * 2001-06-07 2006-05-09 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
JP4967524B2 (ja) * 2006-08-15 2012-07-04 ヤマハ株式会社 半導体装置及びワイヤーボンディング方法
JP2009043793A (ja) * 2007-08-07 2009-02-26 Panasonic Corp 半導体装置、およびその半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61105851A (ja) * 1984-10-30 1986-05-23 Toshiba Corp ワイヤボンデイング方法
JP2001156107A (ja) * 1999-11-30 2001-06-08 Rohm Co Ltd Ｉｃチップ、およびこれの導体ワイヤ接続方法
JP2002184805A (ja) * 2000-12-15 2002-06-28 Oki Data Corp 半導体装置およびワイヤボンディング方法
US20050258549A1 (en) * 2003-06-18 2005-11-24 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
US20070170573A1 (en) * 2006-01-20 2007-07-26 Kuroda Soshi Semiconductor device, interposer chip and manufacturing method of semiconductor device
JP2008171927A (ja) * 2007-01-10 2008-07-24 Renesas Technology Corp 半導体装置

Also Published As

Publication number Publication date
CN104347549B (zh) 2018-08-10
US20150035172A1 (en) 2015-02-05
CN109037184B (zh) 2022-05-03
TW201505145A (zh) 2015-02-01
US9281289B2 (en) 2016-03-08
JP2015029022A (ja) 2015-02-12
KR20150014867A (ko) 2015-02-09
HK1206869A1 (zh) 2016-01-15
CN109037184A (zh) 2018-12-18
US20160163625A1 (en) 2016-06-09
JP6196092B2 (ja) 2017-09-13
CN104347549A (zh) 2015-02-11
US10170402B2 (en) 2019-01-01

Similar Documents

Publication Publication Date Title
TWI631680B (zh) 半導體裝置
JP5789431B2 (ja) 半導体装置の製造方法
JP2546192B2 (ja) フィルムキャリア半導体装置
US9455240B2 (en) Method of manufacturing semiconductor device and semiconductor device
JP5271949B2 (ja) 半導体装置
US20150340342A1 (en) Semiconductor device
US20020192855A1 (en) Semiconductor device and method for manufacturing the same
JP6169713B2 (ja) 半導体装置およびその製造方法
KR20060052333A (ko) 반도체 장치 및 그 제조 방법
JP5970348B2 (ja) 半導体装置
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
JP2012138476A (ja) 半導体装置の製造方法
JP5946511B2 (ja) 半導体装置の製造方法
US8217517B2 (en) Semiconductor device provided with wire that electrically connects printed wiring board and semiconductor chip each other
JP2003258011A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP3972182B2 (ja) 半導体装置の製造方法
JP3670625B2 (ja) 半導体装置およびその製造方法
JP2011124487A (ja) 半導体装置の製造方法
JP5992078B2 (ja) 半導体装置
JP2015015362A (ja) 半導体装置の製造方法
JP2013258347A (ja) 半導体装置
JP6028908B2 (ja) 半導体装置
JP2009238984A (ja) 半導体装置およびその製造方法
JP2014225565A (ja) 半導体装置の製造方法および半導体装置
JP2006140329A (ja) 半導体装置の製造方法