HK1206869A1 - 半導體器件及其製造方法 - Google Patents

半導體器件及其製造方法

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Publication number
HK1206869A1
HK1206869A1 HK15107383.3A HK15107383A HK1206869A1 HK 1206869 A1 HK1206869 A1 HK 1206869A1 HK 15107383 A HK15107383 A HK 15107383A HK 1206869 A1 HK1206869 A1 HK 1206869A1
Authority
HK
Hong Kong
Prior art keywords
manufacturing
same
semiconductor device
semiconductor
Prior art date
Application number
HK15107383.3A
Other languages
English (en)
Inventor
洋輔 今關
壯司 黑田
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of HK1206869A1 publication Critical patent/HK1206869A1/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/1025—Semiconducting materials
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing & Machinery (AREA)
HK15107383.3A 2013-07-30 2015-08-01 半導體器件及其製造方法 HK1206869A1 (zh)

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JP2017092212A (ja) * 2015-11-09 2017-05-25 株式会社東芝 半導体装置およびその製造方法
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TWI739379B (zh) * 2019-04-24 2021-09-11 日商新川股份有限公司 半導體裝置、半導體裝置的製造方法、以及打線接合裝置
CN110265378B (zh) * 2019-06-19 2020-10-23 福建福顺半导体制造有限公司 一种电子元件
KR20210090521A (ko) * 2020-01-10 2021-07-20 에스케이하이닉스 주식회사 본딩 와이어 분지 구조를 포함한 반도체 패키지
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JP4068974B2 (ja) * 2003-01-22 2008-03-26 株式会社ルネサステクノロジ 半導体装置
US6927156B2 (en) * 2003-06-18 2005-08-09 Intel Corporation Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
JP4726640B2 (ja) * 2006-01-20 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
JP4967524B2 (ja) * 2006-08-15 2012-07-04 ヤマハ株式会社 半導体装置及びワイヤーボンディング方法
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