JP5977051B2 - 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 - Google Patents
半導体パッケージ、半導体装置及び半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP5977051B2 JP5977051B2 JP2012063947A JP2012063947A JP5977051B2 JP 5977051 B2 JP5977051 B2 JP 5977051B2 JP 2012063947 A JP2012063947 A JP 2012063947A JP 2012063947 A JP2012063947 A JP 2012063947A JP 5977051 B2 JP5977051 B2 JP 5977051B2
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- Prior art keywords
- insulating layer
- metal plate
- semiconductor chip
- layer
- semiconductor package
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
- H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/121—Arrangements for protection of devices protecting against mechanical damage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W95/00—Packaging processes not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
- H05K2203/1469—Circuit made after mounting or encapsulation of the components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/10—Configurations of laterally-adjacent chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012063947A JP5977051B2 (ja) | 2012-03-21 | 2012-03-21 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
| KR1020130023263A KR101998150B1 (ko) | 2012-03-21 | 2013-03-05 | 반도체 패키지, 반도체 장치 및 반도체 패키지의 제조 방법 |
| US13/833,036 US8994193B2 (en) | 2012-03-21 | 2013-03-15 | Semiconductor package including a metal plate, semiconductor chip, and wiring structure, semiconductor apparatus and method for manufacturing semiconductor package |
| EP13160222.9A EP2654388B1 (en) | 2012-03-21 | 2013-03-20 | Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012063947A JP5977051B2 (ja) | 2012-03-21 | 2012-03-21 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013197382A JP2013197382A (ja) | 2013-09-30 |
| JP2013197382A5 JP2013197382A5 (https=) | 2015-02-19 |
| JP5977051B2 true JP5977051B2 (ja) | 2016-08-24 |
Family
ID=47891553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012063947A Active JP5977051B2 (ja) | 2012-03-21 | 2012-03-21 | 半導体パッケージ、半導体装置及び半導体パッケージの製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8994193B2 (https=) |
| EP (1) | EP2654388B1 (https=) |
| JP (1) | JP5977051B2 (https=) |
| KR (1) | KR101998150B1 (https=) |
Families Citing this family (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101947722B1 (ko) * | 2012-06-07 | 2019-04-25 | 삼성전자주식회사 | 적층 반도체 패키지 및 이의 제조방법 |
| JP5662551B1 (ja) * | 2013-12-20 | 2015-01-28 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
| CN103730379A (zh) * | 2014-01-16 | 2014-04-16 | 苏州晶方半导体科技股份有限公司 | 芯片封装方法及结构 |
| JP6031059B2 (ja) * | 2014-03-31 | 2016-11-24 | 信越化学工業株式会社 | 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 |
| JP6031060B2 (ja) | 2014-03-31 | 2016-11-24 | 信越化学工業株式会社 | 半導体装置、積層型半導体装置、封止後積層型半導体装置、及びこれらの製造方法 |
| US9257414B2 (en) * | 2014-04-10 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor structure and method |
| KR102250997B1 (ko) * | 2014-05-02 | 2021-05-12 | 삼성전자주식회사 | 반도체 패키지 |
| WO2015183184A1 (en) * | 2014-05-30 | 2015-12-03 | Nguyen Phu Cuong Dao | Compact substrate and method for making the same |
| US9799622B2 (en) * | 2014-06-18 | 2017-10-24 | Dyi-chung Hu | High density film for IC package |
| US9756738B2 (en) * | 2014-11-14 | 2017-09-05 | Dyi-chung Hu | Redistribution film for IC package |
| CN107210269B (zh) * | 2015-03-11 | 2020-07-28 | 英特尔公司 | 利用应变重分布层的可拉伸电子器件制造方法 |
| US9929100B2 (en) | 2015-04-17 | 2018-03-27 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
| KR102065943B1 (ko) * | 2015-04-17 | 2020-01-14 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 및 그 제조 방법 |
| JP6456232B2 (ja) * | 2015-04-30 | 2019-01-23 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US10043769B2 (en) * | 2015-06-03 | 2018-08-07 | Micron Technology, Inc. | Semiconductor devices including dummy chips |
| KR102595276B1 (ko) | 2016-01-14 | 2023-10-31 | 삼성전자주식회사 | 반도체 패키지 |
| CN106971993B (zh) | 2016-01-14 | 2021-10-15 | 三星电子株式会社 | 半导体封装件 |
| JP2017162849A (ja) * | 2016-03-07 | 2017-09-14 | イビデン株式会社 | 配線基板及びその製造方法 |
| US10204870B2 (en) * | 2016-04-28 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing the same |
| KR101952864B1 (ko) * | 2016-09-30 | 2019-02-27 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
| CN109804446B (zh) | 2016-10-06 | 2021-05-07 | 株式会社村田制作所 | 固体电解电容器 |
| CN109804445B (zh) | 2016-10-06 | 2021-07-02 | 株式会社村田制作所 | 固体电解电容器 |
| JPWO2019098043A1 (ja) * | 2017-11-16 | 2020-11-19 | 三菱瓦斯化学株式会社 | パターニングされた金属箔付き積層体の製造方法及びパターニングされた金属箔付き積層体 |
| KR102061852B1 (ko) | 2017-12-18 | 2020-01-02 | 삼성전자주식회사 | 반도체 패키지 |
| US10714361B2 (en) | 2017-12-21 | 2020-07-14 | Foundation For Research And Business, Seoul National University Of Science And Technology | Method of fabricating a semiconductor package using an insulating polymer layer |
| KR102024227B1 (ko) * | 2017-12-21 | 2019-11-04 | 서울과학기술대학교 산학협력단 | 반도체 패키지의 제조방법 |
| KR102154166B1 (ko) * | 2018-12-03 | 2020-09-09 | 서울과학기술대학교 산학협력단 | 반도체 패키지의 제조방법 |
| JP7199898B2 (ja) * | 2018-10-04 | 2023-01-06 | 新光電気工業株式会社 | 電子部品内蔵基板、電子部品内蔵基板の製造方法 |
| US10999926B2 (en) | 2019-06-24 | 2021-05-04 | Flex Ltd. | Stress relief encapsulation for flexible hybrid electronics |
| KR102609157B1 (ko) | 2019-06-28 | 2023-12-04 | 삼성전기주식회사 | 반도체 패키지 |
| WO2021006297A1 (ja) | 2019-07-10 | 2021-01-14 | 株式会社デンソー | 半導体パッケージ、電子装置、および半導体パッケージの製造方法 |
| TWI715234B (zh) * | 2019-10-04 | 2021-01-01 | 瑞昱半導體股份有限公司 | 晶片封裝模組 |
| KR102762886B1 (ko) * | 2019-12-11 | 2025-02-07 | 삼성전기주식회사 | 전자부품 내장기판 |
| US11335650B2 (en) * | 2020-06-11 | 2022-05-17 | Advanced Semiconductor Engineering, Inc. | Package substrate, electronic device package and method for manufacturing the same |
| KR102852782B1 (ko) | 2020-07-10 | 2025-08-29 | 삼성전자주식회사 | 반도체 패키지 |
| KR102882371B1 (ko) | 2020-09-04 | 2025-11-06 | 삼성전자주식회사 | 반도체 패키지 |
| KR102843285B1 (ko) | 2020-09-28 | 2025-08-06 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
| TWI789682B (zh) * | 2021-01-15 | 2023-01-11 | 友達光電股份有限公司 | 封裝結構及其製作方法 |
| JP7435823B2 (ja) * | 2021-06-16 | 2024-02-21 | 株式会社村田製作所 | コンデンサアレイ |
| US11694974B2 (en) * | 2021-07-08 | 2023-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die with warpage release layer structure in package and fabricating method thereof |
| US20240243074A1 (en) * | 2023-01-12 | 2024-07-18 | Bae Systems Information And Electronic Systems Integration Inc. | Coaxial i/o die |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
| JP3850260B2 (ja) * | 2001-04-27 | 2006-11-29 | イビデン株式会社 | 半導体チップの製造方法 |
| JP4387231B2 (ja) * | 2004-03-31 | 2009-12-16 | 新光電気工業株式会社 | キャパシタ実装配線基板及びその製造方法 |
| JPWO2007126090A1 (ja) * | 2006-04-27 | 2009-09-17 | 日本電気株式会社 | 回路基板、電子デバイス装置及び回路基板の製造方法 |
| JPWO2008120755A1 (ja) * | 2007-03-30 | 2010-07-15 | 日本電気株式会社 | 機能素子内蔵回路基板及びその製造方法、並びに電子機器 |
| JP4881211B2 (ja) * | 2007-04-13 | 2012-02-22 | 新光電気工業株式会社 | 配線基板の製造方法及び半導体装置の製造方法及び配線基板 |
| JP2011151048A (ja) * | 2008-05-13 | 2011-08-04 | Panasonic Corp | 電子部品の製造方法および電子部品 |
| JP4489821B2 (ja) | 2008-07-02 | 2010-06-23 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| WO2010101163A1 (ja) * | 2009-03-04 | 2010-09-10 | 日本電気株式会社 | 機能素子内蔵基板及びそれを用いた電子デバイス |
| US8120158B2 (en) * | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
| JP5581519B2 (ja) | 2009-12-04 | 2014-09-03 | 新光電気工業株式会社 | 半導体パッケージとその製造方法 |
| WO2011108308A1 (ja) * | 2010-03-04 | 2011-09-09 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
| JP5879692B2 (ja) * | 2010-03-04 | 2016-03-08 | 株式会社リコー | インクジェット記録用インクセット、インクジェット記録方法、及び記録物 |
| WO2011125380A1 (ja) * | 2010-04-08 | 2011-10-13 | 日本電気株式会社 | 半導体素子内蔵配線基板 |
| US8343810B2 (en) * | 2010-08-16 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers |
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| EP2654388A3 (en) | 2017-07-26 |
| US8994193B2 (en) | 2015-03-31 |
| EP2654388A2 (en) | 2013-10-23 |
| KR20130107218A (ko) | 2013-10-01 |
| EP2654388B1 (en) | 2022-06-29 |
| JP2013197382A (ja) | 2013-09-30 |
| US20130249075A1 (en) | 2013-09-26 |
| KR101998150B1 (ko) | 2019-07-09 |
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