WO2015183184A1 - Compact substrate and method for making the same - Google Patents

Compact substrate and method for making the same Download PDF

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Publication number
WO2015183184A1
WO2015183184A1 PCT/SG2014/000238 SG2014000238W WO2015183184A1 WO 2015183184 A1 WO2015183184 A1 WO 2015183184A1 SG 2014000238 W SG2014000238 W SG 2014000238W WO 2015183184 A1 WO2015183184 A1 WO 2015183184A1
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WO
WIPO (PCT)
Prior art keywords
circuit
solder resist
metal
resist layer
metal pads
Prior art date
Application number
PCT/SG2014/000238
Other languages
French (fr)
Inventor
Nguyen Phu Cuong Dao
Original Assignee
Nguyen Phu Cuong Dao
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nguyen Phu Cuong Dao filed Critical Nguyen Phu Cuong Dao
Priority to PCT/SG2014/000238 priority Critical patent/WO2015183184A1/en
Publication of WO2015183184A1 publication Critical patent/WO2015183184A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier

Definitions

  • the present invention relates to a compact substrate and a method for making the same.
  • FIG. 1 shows schematic views of a method for making a conventional substrate.
  • a core substrate 01 is provided.
  • the core substrate 01 has a first surface Oil and a second surface 112.
  • Through via holes 02 are formed and penetrate through the substrate 01.
  • a first circuit is formed on the first surface 011 and a second circuit is formed on the second surface 012 of the core substrate 01.
  • the first circuit comprises metal pads 031 and metal lines 032.
  • the second circuit comprises metal pads 041 and metal lines 042.
  • a dielectric layer 051 is formed on the first surface 011 covering all metal pads 031 and metal lines 032.
  • a dielectric layer 052 is formed on the second surface 012 covering all metal pads 041 and metal lines 042.
  • Blind via holes 061 are formed and penetrate through the dielectric layer 051 to expose some of the metal pads 031.
  • Blind via holes 062 are formed and penetrate through the dielectric layer 052 to expose some of the metal pads 041.
  • a third circuit is formed on top of the dielectric layer 051 and a fourth circuit is formed on top of the dielectric layer 052.
  • the third circuit comprises metal pads 071 and metal lines 072.
  • the fourth circuit comprises metal pads 081 and metal lines 082.
  • a solder resist layer 091 is formed on top of the dielectric layer 051 covering all metal pads 071 and metal lines 072.
  • a solder resist layer 092 is formed on top of the dielectric layer 052 covering all metal pads 081 and metal lines 082. Parts of the solder resist layer 091 are removed to expose some of the metal pads 071 and some of the metal lines 072. Parts of the solder resist layer 092 are removed to expose some of the metal pads 081 and some of the metal lines 082, and a conventional substrate 1 is formed.
  • FIG. 1 A shows schematic views of a method for making a conventional DSLD via structure.
  • a core substrate 01 is provided.
  • the core substrate 01 has a first surface 011 and a second surface 112.
  • DSLD via holes 10 are formed that penetrate through the substrate 01.
  • DSLD via hole 10 has its largest opening 101 at its both ends and its smallest opening 102 somewhere near its middle portion.
  • a first circuit is formed on the first surface 011 and a second circuit is formed on the second surface 012 of the core substrate 01.
  • the first circuit comprises metal pads 111 and metal lines 112.
  • the second circuit comprises metal pads 121 and metal lines 122.
  • Metal pads 111 and 121 are formed with diameters large enough to cover the largest opening 101 completely, given the misalignment that occurs during the process of forming the first and second circuits.
  • FIG. IB illustrates both the ideally desired position of the first and second circuits and the misaligned position of them.
  • the method for making the conventional substrate 1 has the following disadvantages.
  • the through via holes 02, blind via holes 061 and 062; and the DSLD via holes 10 have relatively large diameters due to the thickness of the core substrate 01 and dielectric layers 051 and 052.
  • the metal pads 031, 041, 071, 081, 111 and 121 need to have relatively large diameters in order to cover these via holes completely, given the misalignment that occurs during the process of forming the circuits. Due to this, there are few metal lines and metal pads that can be formed on and within the substrate 1. To achieve higher density of layout, additional dielectric layers and circuits are added to the substrate 1, which causes the manufacturing cost to be high, the processing time to be long and the total thickness of the substrate 1 to be thick.
  • the present invention is directed to a vialess structure.
  • the vialess structure comprises a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer.
  • the present invention is directed to a vialess structure.
  • the vialess structure comprises a first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer.
  • the present invention is directed to a double vialess structure.
  • the double vialess structure comprises a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; and a third circuit formed on the second solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the second solder resist layer.
  • the present invention is directed to a double vialess structure.
  • the double vialess structure comprises a first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; and a third circuit formed ; on the second solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the second solder resist layer.
  • the present invention is directed to a double via structure.
  • the double via structure comprises a core substrate having a first surface and a second surface; at least one double via hole comprising a blind via hole formed on the first surface of the core substrate and at least one through via hole formed at the base of the blind via hole; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate; and a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate.
  • the present invention is directed to a compact DSLD via structure.
  • the Compact DSLD via structure comprises a core substrate having a first surface and a second surface; at least one DSLD via hole having its largest opening at its both ends and its smallest opening somewhere near its middle portion; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate; and a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate.
  • the first and second metal pads are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening of the DSLD via hole, given the misalignment that occurs during the process of forming the first and second circuits;
  • the present invention is directed to a compact substrate.
  • the compact substrate comprises a viaiess structure; a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; and a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines.
  • the present invention is directed to a compact substrate.
  • the compact substrate comprises a double viaiess structure; a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; and a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines.
  • the present invention is directed to a compact substrate.
  • the compact substrate comprises a double via structure; a first viaiess structure formed on the first circuit of the double via structure; a second solder resist layer covering the third circuit of the first viaiess structure and exposing some of the third metal pads and some of the third metal lines; and a third solder resist layer covering the second circuit of the double via structure and exposing some of the second metal pads and some of the second metal lines.
  • the present invention is directed to a compact substrate.
  • the compact substrate comprises a double via structure; a first viaiess structure formed on the first circuit of the double via structure; a second viaiess structure formed on the second circuit of the double via structure; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; and a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines.
  • the present invention is directed to a compact substrate.
  • the compact substrate comprises a compact DSLD via structure; a first viaiess structure formed on the first circuit of the compact DSLD via structure; a second viaiess structure formed on the second circuit of the compact DSLD via structure; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; and a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines.
  • FIG. 1 shows schematic views of a method for making a conventional substrate
  • FIGS. 1 A and IB are schematic views of a method for making a conventional DSLD via structure
  • FIGS. 2, 2A, 3, 4, 5, 6, 6A are schematic views of a method for making a vialess structure
  • FIG. 6B shows sectional and top view of a vialess structure
  • FIGS. 3, 7, 7A, 8, 9, 9A are schematic views of a method for making a vialess structure with a resin layer
  • FIG. 10A shows the comparison between a traditional through via structure and the two types of a vialess structure. More metal lines can be formed between two adjacent metal pads of the vialess structures;
  • FIG. 10B shows the comparison between a traditional blind via structure and the two types of a vialess structure. More metal lines can be formed between two adjacent metal pads of the vialess structures;
  • FIGS. 11, HA, 12, 13, 14, 15A, 15B, 15C, 15D, 16A and 16B are schematic views of a method for making a double via structure
  • FIGS. 17 to 19, 19A, 19B, 20A and 20B are schematic views of a method for making a compact DSLD via structure
  • FIGS. 6, 21, 21A and 22 are schematic views of a method for making a compact substrate according to a first embodiment of the present invention
  • FIGS. 21, 21A and 23 illustrate schematic views of a method for making a compact substrate according to another type of the first embodiment of the present invention
  • FIG. 24 illustrates schematic views of a double vialess structure
  • FIGS. 9, 25, 25 A and 26 are schematic views of a method for making a compact substrate according to a second embodiment of the present invention
  • FIGS. 25, 25A and 27 illustrate schematic views of a method for making a compact substrate according to another type of the second embodiment of the present invention
  • FIG. 28 illustrates schematic views of a method for making a compact substrate according to a third embodiment of the present invention.
  • FIG. 29 illustrates schematic views of a method for making a compact substrate according to another type of the third embodiment of the present invention.
  • FIG. 30 illustrates schematic views of a method for making a compact substrate according to a fourth embodiment of the present invention.
  • FIGS. 2, 2A, 3, 4, 5, 6, 6A are schematic views of a method for making a vialess structure.
  • an insulating carrier 13 and a first conductive layer 131 are provided.
  • the first conductive layer 131 comprises two detachable layers 1311 and 1312 as shown in FIG. 2A.
  • a first photoresist layer 14 is formed on top of the first conductive layer 131. Parts of the first photoresist layer 14 are removed to create openings 140.
  • a first conductive material 15 is electroplated on the openings 140 to form a first circuit 150 comprising first metal pads 151 and first metal lines 152.
  • the first conductive material 15 can be a single metal, an alloy or a series of a few metal layers.
  • the first circuit 150 has a first surface 1501 and a second surface 1502. The first photoresist layer 14 is removed to form the structure as shown in FIG. 3.
  • a first solder resist layer 16 is formed on the entire surface of the first conductive layer 131 and covers the first surface 1501 of the first circuit 150.
  • a PID material can also be used to form the first solder resist layer 16.
  • the first solder resist layer 16 is processed by being exposed to ultra violet (UV) light followed by being developed in an alkaline solution to remove certain parts of it so as to create openings 160.
  • the first solder resist layer 16 can also be processed by direct laser imaging technology or laser drilling to form openings 160. Openings 160 expose some of the first metal pads 151 and some of the first metal lines 152.
  • a second conductive layer 132 (not shown) is formed by physical vapour deposition or electroless plating process.
  • the second conductive layer 132 covers the entire surface of the first solder resist layer 16 and the openings 160.
  • a second photoresist layer 17 is formed on top of the second conductive layer 132. Parts of the second photoresist layer 17 are removed to create openings 170 as illustrated in FIG. 5.
  • a second conductive material 18 is electroplated on the openings 170 to form a second circuit 180 comprising second metal pads 181 and second metal lines 182.
  • Metal pads 181 cover the exposed first metal pads 151 and exposed first metal lines 152.
  • the second photoresist layer 17 is removed followed by the removal of the second conductive layer 132; and a vialess structure is formed on the first circuit 150 as shown in FIG. 6.
  • All the described processes that involve the insulating carrier 13 can be carried out on one side of the carrier 13 to produce one substrate as shown in FIG. 6 or on both sides of the carrier 13 to produce two identical substrates as shown in FIG. 6A.
  • FIG. 6B shows sectional and top view of a vialess structure.
  • FIGS. 3, 7, 7A, 8, 9, 9A are schematic views of a method for making a vialess structure with a resin layer.
  • a structure as shown in FIG. 3 is provided.
  • a resin coated copper comprising a resin layer 161 and a copper layer 162 is laminated onto the first conductive layer 131 and covers the first circuit 150 as shown in FIG. 7.
  • the copper layer 162 is removed by etching process.
  • a desmear or grinding process is performed on the resin layer 161 in order to remove the resin residue so that the first surface 1501 of the first circuit 150 is exposed as shown in FIG. 7A.
  • a first solder resist layer 16 is formed on the entire surface of the resin layer 161 and covers the first surface 1501 of the first circuit 150.
  • a PID material can also be used to form the first solder resist layer 16.
  • the first solder resist layer 16 is processed by being exposed to ultra violet (UV) light followed by being developed in an alkaline solution to remove certain parts of it so as to create openings 160.
  • the first solder resist layer 16 can also be processed by direct laser imaging technology or laser drilling to form openings 160. Openings 160 expose some of the first metal pads 151 and some of the first metal lines 152.
  • a second conductive layer 132 (not shown) is formed by physical vapour deposition or electroless plating process.
  • the second conductive layer 132 covers the entire surface of the first solder resist layer 16 and the openings 160.
  • a second photoresist layer 17 is formed on top of the second conductive layer 132. Parts of the second photoresist layer 17 are removed to create openings 170 as illustrated in FIG. 8.
  • a second conductive material 18 is electroplated on the openings 170 to form a second circuit 180 comprising second metal pads 181 and second metal lines 182.
  • Metal pads 181 cover the exposed first metal pads 151 and exposed first metal lines 152-
  • the second photoresist layer 17 is removed followed by the removal of the second conductive layer 132; and a viaiess structure with a resin layer is formed on the first circuit 150 as shown in FIG. 9.
  • All the described processes that involve the insulating carrier 13 can be carried out on one side of the carrier 13 to produce one substrate as shown in FIG. 9 or on both sides of the carrier 13 to produce two identical substrates as shown in FIG. 9 A.
  • FIG. 1 OA shows the comparison between a traditional through via structure and the two types of a viaiess structure. More metal lines can be formed between two adjacent metal pads of the viaiess structures.
  • FIG. 10B shows the comparison between a traditional blind via structure and the two types of a viaiess structure. More metal lines can be formed between two adjacent metal pads of the viaiess structures.
  • FIGS. 1 1, 1 1 A, 12, 13, 14, 15A, 15B, 15C, 15D, 16A and 16B are schematic views of a method for making a double via structure.
  • a core substrate 19 is provided.
  • the core substrate 19 has a first surface 191 and a second surface 192.
  • Blind via holes 201 are formed on the first surface 191 by laser.
  • blind via holes 201 can be formed by laminating the core substrate 19 on a preformed mold as illustrated in FIG. 1 1A.
  • the mold is coated with an anti-stick material in order to ease the separating process after lamination.
  • At least one through via holes 202 are formed at the base of the blind via hole 201.
  • the through via hole 202 can be as small as ten micron in diameter. Usually the diameter of the through via hole 202 is larger in value as compared to its depth so that it can be filled effectively by electroplating processes.
  • the combination of the blind via holes 201 and the through via holes 202 forms the double via holes 20 as shown in FIG. 12.
  • a first conductive layer 133 (not shown) is formed on the entire first surface 191 and the entire second surface 192 of the core substrate 19.
  • the first conductive layer 133 also covers the double via holes 20.
  • a first photoresist layer 211 is formed on the first conductive layer 133 on the first surface 191.
  • a second photoresist layer 212 is formed on the first conductive layer 133 on the second surface 192. Parts of the first photoresist layer 211 are removed to create openings 2110. Parts of the second photoresist layer 212 are removed to create openings 2120 as shown in FIG. 13.
  • a first conductive material 22 is electroplated on the openings 2110 and 2120 to form a first circuit 220 on the first surface 191 and a second circuit 230 on the second surface 192 simultaneously.
  • the first circuit 220 comprises first metal pads 221 and first metal, lines 222. Some of the first metal pads 221 are located at the bottom of the blind via hole 201 and capture the through via hole 202 completely. This forms a pad in via structure.
  • the second circuit 230 comprises second metal pads 231 and second metal lines 232. Both first and second photoresist layers 211 and 212 are removed.
  • the first conductive layer 133 is also removed, and a double via structure is formed as shown in FIG. 14.
  • FIG. 15A illustrates a pad in via structure, a double via structure where the blind via hole is completely filled by electroplating process and a double via structure where the wall of the blind via hole is electroplated with a conductive material.
  • More than one through via holes 202 can be formed in one blind via hole 201; and the base of blind via holes 201 can be formed in different shapes such as a circle, a square or a rectangular as shown in FIG. 15B.
  • FIGS. 15C and 15D show the method of forming a traditional bumps structure during a flip chip attach process.
  • a semiconductor die 90 is placed on the substrate 91 where the bumps 901 of the die sit on the metal pads 911 of the substrate 91 in the presence of a flux or non-conductive paste (not shown).
  • the bumps 901 melt and make good contact with the metal pads 911.
  • the bumps 901 are seated on top of the substrate 91 surface and are exposed to the environment.
  • FIGS. 15C and 15D also illustrate a method of forming an embedded bumps structure during a flip chip attach process.
  • a semiconductor die 90 is placed on the substrate 92 where the bumps 901 of the die sit on the metal pads 921 of the substrate 92 in the presence of a flux or non-conductive paste (not shown).
  • the bumps 901 melt and make good contact with the metal pads 921.
  • the bumps 901 are totally embedded in the blind via holes forming an embedded bumps structure.
  • FIG. 16A shows the comparison between a traditional through via structure and a double via structure. In the double via structure, the through via holes are small in diameter and more metal lines can be formed between two adjacent metal pads.
  • FIG. ⁇ 6 ⁇ shows the comparison between a traditional blind via structure and a double via structure.
  • the through, via holes are small in diameter and more metal lines can be formed between two adjacent metal pads.
  • FIGS. 17 to 19, 19A, 19B, 20A and 20B are schematic views of a method for making a compact DSLD via structure.
  • a core substrate 24 is provided.
  • the core substrate 24 has a first surface 241 and a second surface 242.
  • DSLD via holes 25 are formed and penetrate through the substrate 24.
  • the DSLD via hole 25 has its largest opening 251 at its both ends and its smallest opening 252 somewhere near its middle portion.
  • a first conductive layer 134 (not shown) is formed on the entire first surface 241 and the entire second surface 242 of the core substrate 24.
  • the first conductive layer 134 also covers the DSLD via holes 25.
  • a first photoresist layer 261 is formed on the first conductive layer 134 on the first surface 241.
  • a second photoresist layer 262 is formed on the first conductive layer 134 on the second surface 242. Parts of the first photoresist layer 261 are removed to create openings 2610. Parts of the second photoresist layer 262 are removed to create openings 2620 as shown in FIG. 18.
  • a first conductive material 27 is electroplated on the openings 2610 and 2620 to form a first circuit 270 on the first surface 241 and a second circuit 280 on the second surface 242 simultaneously.
  • the first circuit 270 comprises first metal pads 271 and first metal lines 272.
  • the second circuit 280 comprises second metal pads 281 and second metal lines 282.
  • the metal pads 271 and 281 are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening 252, given the misalignment that occurs during the process of forming the first and second circuits.
  • a compact DSLD via structure is formed as shown in FIG. 19.
  • FIG. 19A illustrates both the ideally desired position of the first and second circuits in a compact DSLD via structure and the misaligned position of them.
  • the metal pads 271 and 281 can be formed in the shape of a square or a rectangular for better coverage over the DSLD via hole.
  • FIG. 19B illustrates both the ideally desired position of the first and second circuits in a compact DSLD via structure with rectangular metal pads and the misaligned position of them.
  • FIG. 20 A shows the comparison between a traditional DSLD via structure and a compact DSLD via structure.
  • the metal pads are small in diameter so that more metal lines can be formed between two adjacent metal pads.
  • FIG. 20B shows the comparison between a traditional DSLD via structure and a compact DSLD via structure with rectangular metal pads.
  • the shorter edge of the metal pads are short in length so that more metal lines can be formed between two adjacent metal pads.
  • FIGS. 6, 21 , 21 A and 22 are schematic views of a method for making a compact substrate according to a first embodiment of the present invention.
  • a structure as shown in FIG. 6 is provided.
  • a dielectric layer with reinforced fiber 29 is formed on the first solder resist layer 16 and the second circuit 180 by laminating process either with or without a metal foil 291 as shown in FIG. 21.
  • the carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131.
  • the detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150.
  • a second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 2 is formed as shown in FIG. 22.
  • FIGS. 21, 21A and 23 are schematic views of a method for making a compact substrate according to another type of the first embodiment of the present invention.
  • a structure as shown in FIG. 21 or FIG. 21 A is provided.
  • the carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131.
  • the detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150.
  • a second vialess structure is formed on the second surface 1502 of the first circuit 150.
  • the procedures of forming the second vialess structure are described as follows.
  • a second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152.
  • a conductive layer 135 is formed on the second solder resist 30 and the exposed first metal pads 151 and exposed first metal lines 152.
  • a photo resist layer 171 is formed on the conductive layer 135. Parts of the photo resist layer 171 are removed to form openings 1710.
  • a conductive material 31 is electroplated on the openings 1710 to form a third circuit 310 comprising third metal pads 311 and third metal lines 312. The third metal pads 311 cover the exposed first metal pads 151 and exposed first metal lines 152.
  • the photo resist layer 171 is removed followed by the removal of the conductive layer 135.
  • a third solder resist layer 32 is formed on the second solder resist layer 30 covering the third circuit 310. Parts of the third solder resist layer 32 are removed to expose parts of the third metal pads 311 and parts of the third metal lines 312. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 2A is formed as shown in FIG. 23.
  • substrate 2A There is a double vialess structure in substrate 2A, which is further illustrated in FIG. 24.
  • FIG. 24 shows schematic views of a double vialess structure where two vialess structures are formed on both sides of a metal line or a metal pad.
  • FIGS. 9, 25, 25A and 26 are schematic views of a method for making a compact substrate according to a second embodiment of the present invention.
  • a structure as shown in FIG. 9 is provided.
  • a dielectric layer with reinforced fiber 29 is formed on the first solder resist layer 16 and the second circuit 180 by laminating process either with or without a metal foil 291 as shown in FIG. 25.
  • the carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131.
  • the detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150.
  • a second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 3 is formed as shown in FIG. 26.
  • FIGS. 25, 25A and 27 illustrate schematic views of a method for making a compact substrate according to another type of the second embodiment of the present invention. A structure as shown in FIG. 25 or FIG. 25A is provided.
  • the carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131.
  • the detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150.
  • a second vialess structure is formed on the second surface 1502 of the first circuit 150. The procedures of forming the second vialess structure are described as follows.
  • a second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152.
  • a conductive layer 136 is formed on the second solder resist 30 and the exposed first metal pads 151 and exposed first metal lines 152.
  • a photo resist layer 172 is formed on the conductive layer 136.
  • Parts of the photo resist layer 172 are removed to form openings 1720.
  • a conductive material 31 is electroplated on the openings 1720 to form a third circuit 310 comprising third metal pads 311 and third metal lines 312.
  • the third metal pads 311 cover the exposed first metal pads 151 and exposed first metal lines 152.
  • the photo resist layer 172 is removed followed by the removal of the conductive layer 136.
  • a third solder resist layer 32 is formed on the second solder resist layer 30 covering the third circuit 310. Parts of the third solder resist layer 32 are removed to expose parts of the third metal pads 311 and parts of the third metal lines 312. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 3A is formed as shown in FIG. 27.
  • FIG. 28 illustrates schematic views of a method for making a compact substrate according to a third embodiment of the present invention.
  • a double via structure as shown in FIG. 14 is provided.
  • a first vialess structure is formed on the first metal pads 221 and first metal lines 222.
  • the procedures of forming the first vialess structure are described as follows.
  • a first solder resist layer 40 is formed and covers the first circuit 220. Parts of the first solder resist 40 are removed to expose some of the first metal pads 221 and some of the first metal lines 222.
  • a conductive layer 137 is formed on the first solder resist 40 and the exposed first metal pads 221 and exposed first metal lines 222.
  • a photo resist layer 173 is formed on the conductive layer 137. Parts of the photo resist layer 173 are removed to form openings 1730.
  • a conductive material 41 is electroplated on the openings 1730 to form a third circuit 410 comprising third metal pads 411 and third metal lines 412. The third metal pads 411 cover the exposed first metal pads 221 and exposed first metal lines 222.
  • the photo resist layer 173 is removed followed by the removal of the conductive layer 137.
  • a second solder resist layer 42 is formed on the first solder resist layer 40 covering the third circuit 410.
  • a third solder resist layer 43 is formed on the second circuit 230. Parts of the second solder resist layer 42 are removed to expose parts of the third metal pads 411 and parts of the third metal lines 412. Parts of the third solder resist layer 43 are removed to expose parts of the second metal pads 231 and parts of the second metal lines 232, and a substrate 4 is formed as shown in FIG. 28.
  • FIG. 29 illustrates schematic views of a method for making a compact substrate according to another type of the third embodiment of the present invention.
  • a double via structure as shown in FIG. 14 is provided.
  • a first vialess structure is formed on the first metal pads 221 and first metal lines 222 and a second vialess structure is formed on the second metal pads 231 and second metal lines 232 simultaneously.
  • the procedures of forming the first vialess structure and the second vialess structure are described as follows.
  • a first solder resist layer 44 and second solder resist layer 45 are formed and covers the first circuit 220 and the second circuit 230 respectively. Parts of the first solder resist layer 44 are removed to expose some of the first metal pads 221 and some of the first metal lines 222. Parts of the second solder resist layer 45 are removed to expose some of the second metal pads 231 and some of the second metal lines 232.
  • a conductive layer 138 is formed on the first solder resist layer 44 and second solder resist layer 45.
  • the conductive layer 138 also covers the exposed first metal pads 221, exposed first metal lines 222, exposed second metal pads 231 and exposed second metal lines 232.
  • a photo resist layer 174 is formed on the conductive layer 138 on the solder resist layer 44.
  • a photo resist layer 175 is formed on the conductive layer 138 on the solder resist layer 45. Parts of the photo resist layer 174 are removed to form openings 1740. Parts of the photo resist layer 175 are removed to form openings 1750.
  • a conductive material 46 is electroplated on the openings 1740 to form a third circuit 460 comprising third metal pads 461 and third metal lines 462 and on the openings 1750 to form a fourth circuit 470 comprising fourth metal pads 471 and fourth metal lines 472.
  • the third metal pads 461 cover the exposed first metal pads 221 and exposed first metal lines 222 and the fourth metal pads 471 cover the exposed second metal pads 231 and exposed second metal lines 232. Both photo resist layer 174 and 175 are removed followed by the removal of the conductive layer 138.
  • a third and fourth solder resist layers 48 and 49 are formed where the third solder resist layer 48 is formed on the first solder resist layer 44 covering the third circuit 460 and fourth solder resist layer 49 is formed on the second solder resist layer 45 covering the fourth circuit 470. Parts of the third solder resist layer 48 are removed to expose parts of the third metal pads 461 and parts of the third metal lines 462. Parts of the fourth solder resist layer 49 are removed to expose parts of the fourth metal pads 471 and parts of the fourth metal lines 472, and a substrate 4A is formed as shown in FIG. 29.
  • FIG. 30 illustrates schematic views of a method for making a compact substrate according to a fourth embodiment of the present invention.
  • a compact DSLD via structure as shown in FIG. 19 is provided.
  • a first vialess structure is formed on the first metal pads 271 and first metal lines 272 and a second vialess structure is formed on the second metal pads 281 and second metal lines 282 simultaneously.
  • the procedures of forming the first vialess structure and the second vialess structure are described as follows.
  • a first solder resist layer 51 and second solder resist layer 52 are formed and covers the first circuit 270 and the second circuit 280 respectively. Parts of the first solder resist layer 51 are removed to expose some of the first metal pads 271 and some of the first metal lines 272. Parts of the second solder resist layer 52 are removed to expose some of the second metal pads 281 and some of the second metal lines 282.
  • a conductive layer 138 is formed on the first solder resist layer 51 and second solder resist layer 52.
  • the conductive layer 138 also covers the exposed first metal pads 271, exposed first metal lines 272, exposed second metal pads 281 and exposed second metal lines 282.
  • a photo resist layer 174 is formed on the conductive layer 138 on the solder resist layer 51.
  • a photo resist layer 175 is formed on the conductive layer 138 on the solder resist layer 52. Parts of the photo resist layer 174 are removed to form openings 1740. Parts of the photo resist layer 175 are removed to form openings 1750.
  • a conductive material 53 is electroplated on the openings 1740 to form a third circuit 530 comprising third metal pads 531 and third metal lines 532 and on the openings 1750 to form a fourth circuit 540 comprising fourth metal pads 541 and fourth metal lines 542.
  • the third metal pads 531 cover the exposed first metal pads 271 and exposed first metal lines 272 and the fourth metal pads 541 cover the exposed second metal pads 281 and exposed second metal lines 282. Both photo resist layer 174 and 175 are removed followed by the removal of the conductive layer 138.
  • a third and fourth solder resist layers 55 and 56 are formed where the third solder resist layer 55 is formed on the first solder resist layer 51 covering the third circuit 530 and fourth solder resist layer 56 is formed on the second solder resist layer 52 covering the fourth circuit 540. Parts of the third solder resist layer 55 are removed to expose parts of the third metal pads 531 and parts of the third metal lines 532. Parts of the fourth solder resist layer 56 are removed to expose parts of the fourth metal pads 541 and parts of the fourth metal lines 542, and a substrate 5 is formed as shown in FIG. 30.
  • the compact substrates 2, 2A, 3, 3A, 4, 4A and 5 of the present invention have high density of layout; involve low manufacturing cost and shorter cycle time.

Abstract

The present invention relates to a compact substrate and a method for making the same. The compact substrate comprises at least one or a combination of a coreless structure, a double via structure and a compact double sided laser drilled (DSLD) via structure. The coreless structure has a first circuit comprising a plurality of first metal pads (151) and first metal lines (152). A first solder resist layer (16) is formed to cover parts of the first circuit and expose parts of the first metal pads (151) and parts of the first metal lines (152). Some Photo-Imageable Dielectric (PID) material can also be used to form the first solder resist layer (16). A second circuit comprising second metal pads (181) and second metal lines (182) are formed on the first solder resist layer (16). The second metal pads (181) cover the exposed first metal pads (151) and exposed first metal lines (152). The double via structure comprises a core substrate (19) having a first surface (191) and a second surface (192). Blind via holes (201) are formed on the first surface (191) of the core substrate (19). At least one through via holes (202) are formed on the base of the blind Via holes. The through via holes (202) are smaller in diameter as compared to that of the blind via holes (201). The through via holes (202) are located within the base of the blind via holes (201): The combination of the blind via holes (201) and the through via holes (202) forms the double via holes that penetrate through the core substrate (19). A compact double sided laser drilled (DSLD) via structure comprises a core substrate (19) having a first surface (191) and a second surface (192). DSLD via holes are formed and penetrate through the core substrate (19). Having the shape of two cones combined heads on, the DSLD via hole has its largest opening at its both ends and has its smallest opening somewhere near its middle portion.

Description

COMPACT SUBSTRATE AND METHOD FOR MAKING THE SAME DESCRIPTIO
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compact substrate and a method for making the same.
2. Description of the Related Art
FIG. 1 shows schematic views of a method for making a conventional substrate. First, a core substrate 01 is provided. The core substrate 01 has a first surface Oil and a second surface 112. Through via holes 02 are formed and penetrate through the substrate 01. A first circuit is formed on the first surface 011 and a second circuit is formed on the second surface 012 of the core substrate 01. The first circuit comprises metal pads 031 and metal lines 032. The second circuit comprises metal pads 041 and metal lines 042. A dielectric layer 051 is formed on the first surface 011 covering all metal pads 031 and metal lines 032. A dielectric layer 052 is formed on the second surface 012 covering all metal pads 041 and metal lines 042. Blind via holes 061 are formed and penetrate through the dielectric layer 051 to expose some of the metal pads 031. Blind via holes 062 are formed and penetrate through the dielectric layer 052 to expose some of the metal pads 041. A third circuit is formed on top of the dielectric layer 051 and a fourth circuit is formed on top of the dielectric layer 052. The third circuit comprises metal pads 071 and metal lines 072. The fourth circuit comprises metal pads 081 and metal lines 082. A solder resist layer 091 is formed on top of the dielectric layer 051 covering all metal pads 071 and metal lines 072. A solder resist layer 092 is formed on top of the dielectric layer 052 covering all metal pads 081 and metal lines 082. Parts of the solder resist layer 091 are removed to expose some of the metal pads 071 and some of the metal lines 072. Parts of the solder resist layer 092 are removed to expose some of the metal pads 081 and some of the metal lines 082, and a conventional substrate 1 is formed.
FIG. 1 A shows schematic views of a method for making a conventional DSLD via structure. First, a core substrate 01 is provided. The core substrate 01 has a first surface 011 and a second surface 112. DSLD via holes 10 are formed that penetrate through the substrate 01. DSLD via hole 10 has its largest opening 101 at its both ends and its smallest opening 102 somewhere near its middle portion. A first circuit is formed on the first surface 011 and a second circuit is formed on the second surface 012 of the core substrate 01. The first circuit comprises metal pads 111 and metal lines 112. The second circuit comprises metal pads 121 and metal lines 122. Metal pads 111 and 121 are formed with diameters large enough to cover the largest opening 101 completely, given the misalignment that occurs during the process of forming the first and second circuits.
FIG. IB illustrates both the ideally desired position of the first and second circuits and the misaligned position of them.
The method for making the conventional substrate 1 has the following disadvantages. The through via holes 02, blind via holes 061 and 062; and the DSLD via holes 10 have relatively large diameters due to the thickness of the core substrate 01 and dielectric layers 051 and 052. The metal pads 031, 041, 071, 081, 111 and 121 need to have relatively large diameters in order to cover these via holes completely, given the misalignment that occurs during the process of forming the circuits. Due to this, there are few metal lines and metal pads that can be formed on and within the substrate 1. To achieve higher density of layout, additional dielectric layers and circuits are added to the substrate 1, which causes the manufacturing cost to be high, the processing time to be long and the total thickness of the substrate 1 to be thick.
Therefore, it is necessary to provide a compact substrate and a method for making the same to solve the above problems.
SUMMARY OF THE INVENTION
The present invention is directed to a vialess structure. The vialess structure comprises a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer.
The present invention is directed to a vialess structure. The vialess structure comprises a first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer. The present invention is directed to a double vialess structure. The double vialess structure comprises a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; and a third circuit formed on the second solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the second solder resist layer.
The present invention is directed to a double vialess structure. The double vialess structure comprises a first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; and a third circuit formed ; on the second solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the second solder resist layer.
The present invention is directed to a double via structure. The double via structure comprises a core substrate having a first surface and a second surface; at least one double via hole comprising a blind via hole formed on the first surface of the core substrate and at least one through via hole formed at the base of the blind via hole; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate; and a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate.
The present invention is directed to a compact DSLD via structure. The Compact DSLD via structure comprises a core substrate having a first surface and a second surface; at least one DSLD via hole having its largest opening at its both ends and its smallest opening somewhere near its middle portion; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate; and a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate. The first and second metal pads are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening of the DSLD via hole, given the misalignment that occurs during the process of forming the first and second circuits;
The present invention is directed to a compact substrate. The compact substrate comprises a viaiess structure; a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; and a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines.
The present invention is directed to a compact substrate. The compact substrate comprises a double viaiess structure; a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; and a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines.
The present invention is directed to a compact substrate. The compact substrate comprises a double via structure; a first viaiess structure formed on the first circuit of the double via structure; a second solder resist layer covering the third circuit of the first viaiess structure and exposing some of the third metal pads and some of the third metal lines; and a third solder resist layer covering the second circuit of the double via structure and exposing some of the second metal pads and some of the second metal lines.
The present invention is directed to a compact substrate. The compact substrate comprises a double via structure; a first viaiess structure formed on the first circuit of the double via structure; a second viaiess structure formed on the second circuit of the double via structure; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; and a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines.
The present invention is directed to a compact substrate. The compact substrate comprises a compact DSLD via structure; a first viaiess structure formed on the first circuit of the compact DSLD via structure; a second viaiess structure formed on the second circuit of the compact DSLD via structure; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; and a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines. BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows schematic views of a method for making a conventional substrate; FIGS. 1 A and IB are schematic views of a method for making a conventional DSLD via structure; FIGS. 2, 2A, 3, 4, 5, 6, 6A are schematic views of a method for making a vialess structure; FIG. 6B shows sectional and top view of a vialess structure;
FIGS. 3, 7, 7A, 8, 9, 9A are schematic views of a method for making a vialess structure with a resin layer;
FIG. 10A shows the comparison between a traditional through via structure and the two types of a vialess structure. More metal lines can be formed between two adjacent metal pads of the vialess structures;
FIG. 10B shows the comparison between a traditional blind via structure and the two types of a vialess structure. More metal lines can be formed between two adjacent metal pads of the vialess structures;
FIGS. 11, HA, 12, 13, 14, 15A, 15B, 15C, 15D, 16A and 16B are schematic views of a method for making a double via structure;
FIGS. 17 to 19, 19A, 19B, 20A and 20B are schematic views of a method for making a compact DSLD via structure;
FIGS. 6, 21, 21A and 22 are schematic views of a method for making a compact substrate according to a first embodiment of the present invention;
FIGS. 21, 21A and 23 illustrate schematic views of a method for making a compact substrate according to another type of the first embodiment of the present invention;
FIG. 24 illustrates schematic views of a double vialess structure;
FIGS. 9, 25, 25 A and 26 are schematic views of a method for making a compact substrate according to a second embodiment of the present invention; FIGS. 25, 25A and 27 illustrate schematic views of a method for making a compact substrate according to another type of the second embodiment of the present invention;
FIG. 28 illustrates schematic views of a method for making a compact substrate according to a third embodiment of the present invention;
FIG. 29 illustrates schematic views of a method for making a compact substrate according to another type of the third embodiment of the present invention;
FIG. 30 illustrates schematic views of a method for making a compact substrate according to a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 2, 2A, 3, 4, 5, 6, 6A are schematic views of a method for making a vialess structure. As shown in FIG. 2, an insulating carrier 13 and a first conductive layer 131 are provided. The first conductive layer 131 comprises two detachable layers 1311 and 1312 as shown in FIG. 2A. A first photoresist layer 14 is formed on top of the first conductive layer 131. Parts of the first photoresist layer 14 are removed to create openings 140.
A first conductive material 15 is electroplated on the openings 140 to form a first circuit 150 comprising first metal pads 151 and first metal lines 152. The first conductive material 15 can be a single metal, an alloy or a series of a few metal layers. The first circuit 150 has a first surface 1501 and a second surface 1502. The first photoresist layer 14 is removed to form the structure as shown in FIG. 3.
As shown in FIG. 4, a first solder resist layer 16 is formed on the entire surface of the first conductive layer 131 and covers the first surface 1501 of the first circuit 150. A PID material can also be used to form the first solder resist layer 16. The first solder resist layer 16 is processed by being exposed to ultra violet (UV) light followed by being developed in an alkaline solution to remove certain parts of it so as to create openings 160. Alternatively, the first solder resist layer 16 can also be processed by direct laser imaging technology or laser drilling to form openings 160. Openings 160 expose some of the first metal pads 151 and some of the first metal lines 152.
A second conductive layer 132 (not shown) is formed by physical vapour deposition or electroless plating process. The second conductive layer 132 covers the entire surface of the first solder resist layer 16 and the openings 160. A second photoresist layer 17 is formed on top of the second conductive layer 132. Parts of the second photoresist layer 17 are removed to create openings 170 as illustrated in FIG. 5.
A second conductive material 18 is electroplated on the openings 170 to form a second circuit 180 comprising second metal pads 181 and second metal lines 182. Metal pads 181 cover the exposed first metal pads 151 and exposed first metal lines 152. The second photoresist layer 17 is removed followed by the removal of the second conductive layer 132; and a vialess structure is formed on the first circuit 150 as shown in FIG. 6.
All the described processes that involve the insulating carrier 13 can be carried out on one side of the carrier 13 to produce one substrate as shown in FIG. 6 or on both sides of the carrier 13 to produce two identical substrates as shown in FIG. 6A.
FIG. 6B shows sectional and top view of a vialess structure.
FIGS. 3, 7, 7A, 8, 9, 9A are schematic views of a method for making a vialess structure with a resin layer. A structure as shown in FIG. 3 is provided. A resin coated copper comprising a resin layer 161 and a copper layer 162 is laminated onto the first conductive layer 131 and covers the first circuit 150 as shown in FIG. 7.
The copper layer 162 is removed by etching process. A desmear or grinding process is performed on the resin layer 161 in order to remove the resin residue so that the first surface 1501 of the first circuit 150 is exposed as shown in FIG. 7A.
A first solder resist layer 16 is formed on the entire surface of the resin layer 161 and covers the first surface 1501 of the first circuit 150. A PID material can also be used to form the first solder resist layer 16. The first solder resist layer 16 is processed by being exposed to ultra violet (UV) light followed by being developed in an alkaline solution to remove certain parts of it so as to create openings 160. Alternatively, the first solder resist layer 16 can also be processed by direct laser imaging technology or laser drilling to form openings 160. Openings 160 expose some of the first metal pads 151 and some of the first metal lines 152.
A second conductive layer 132 (not shown) is formed by physical vapour deposition or electroless plating process. The second conductive layer 132 covers the entire surface of the first solder resist layer 16 and the openings 160. A second photoresist layer 17 is formed on top of the second conductive layer 132. Parts of the second photoresist layer 17 are removed to create openings 170 as illustrated in FIG. 8.
A second conductive material 18 is electroplated on the openings 170 to form a second circuit 180 comprising second metal pads 181 and second metal lines 182. Metal pads 181 cover the exposed first metal pads 151 and exposed first metal lines 152- The second photoresist layer 17 is removed followed by the removal of the second conductive layer 132; and a viaiess structure with a resin layer is formed on the first circuit 150 as shown in FIG. 9.
All the described processes that involve the insulating carrier 13 can be carried out on one side of the carrier 13 to produce one substrate as shown in FIG. 9 or on both sides of the carrier 13 to produce two identical substrates as shown in FIG. 9 A.
FIG. 1 OA shows the comparison between a traditional through via structure and the two types of a viaiess structure. More metal lines can be formed between two adjacent metal pads of the viaiess structures.
FIG. 10B shows the comparison between a traditional blind via structure and the two types of a viaiess structure. More metal lines can be formed between two adjacent metal pads of the viaiess structures.
FIGS. 1 1, 1 1 A, 12, 13, 14, 15A, 15B, 15C, 15D, 16A and 16B are schematic views of a method for making a double via structure. As shown in FIG. 1 1, a core substrate 19 is provided. The core substrate 19 has a first surface 191 and a second surface 192. Blind via holes 201 are formed on the first surface 191 by laser. Alternatively, blind via holes 201 can be formed by laminating the core substrate 19 on a preformed mold as illustrated in FIG. 1 1A. The mold is coated with an anti-stick material in order to ease the separating process after lamination.
At least one through via holes 202 are formed at the base of the blind via hole 201. The through via hole 202 can be as small as ten micron in diameter. Usually the diameter of the through via hole 202 is larger in value as compared to its depth so that it can be filled effectively by electroplating processes.
The combination of the blind via holes 201 and the through via holes 202 forms the double via holes 20 as shown in FIG. 12.
A first conductive layer 133 (not shown) is formed on the entire first surface 191 and the entire second surface 192 of the core substrate 19. The first conductive layer 133 also covers the double via holes 20. A first photoresist layer 211 is formed on the first conductive layer 133 on the first surface 191. A second photoresist layer 212 is formed on the first conductive layer 133 on the second surface 192. Parts of the first photoresist layer 211 are removed to create openings 2110. Parts of the second photoresist layer 212 are removed to create openings 2120 as shown in FIG. 13.
A first conductive material 22 is electroplated on the openings 2110 and 2120 to form a first circuit 220 on the first surface 191 and a second circuit 230 on the second surface 192 simultaneously. The first circuit 220 comprises first metal pads 221 and first metal, lines 222. Some of the first metal pads 221 are located at the bottom of the blind via hole 201 and capture the through via hole 202 completely. This forms a pad in via structure. The second circuit 230 comprises second metal pads 231 and second metal lines 232. Both first and second photoresist layers 211 and 212 are removed. The first conductive layer 133 is also removed, and a double via structure is formed as shown in FIG. 14.
FIG. 15A illustrates a pad in via structure, a double via structure where the blind via hole is completely filled by electroplating process and a double via structure where the wall of the blind via hole is electroplated with a conductive material.
More than one through via holes 202 can be formed in one blind via hole 201; and the base of blind via holes 201 can be formed in different shapes such as a circle, a square or a rectangular as shown in FIG. 15B.
FIGS. 15C and 15D show the method of forming a traditional bumps structure during a flip chip attach process. A semiconductor die 90 is placed on the substrate 91 where the bumps 901 of the die sit on the metal pads 911 of the substrate 91 in the presence of a flux or non-conductive paste (not shown). During reflow process, the bumps 901 melt and make good contact with the metal pads 911. After reflow process, the bumps 901 are seated on top of the substrate 91 surface and are exposed to the environment.
FIGS. 15C and 15D also illustrate a method of forming an embedded bumps structure during a flip chip attach process. A semiconductor die 90 is placed on the substrate 92 where the bumps 901 of the die sit on the metal pads 921 of the substrate 92 in the presence of a flux or non-conductive paste (not shown). During reflow process, the bumps 901 melt and make good contact with the metal pads 921. After reflow process, the bumps 901 are totally embedded in the blind via holes forming an embedded bumps structure. FIG. 16A shows the comparison between a traditional through via structure and a double via structure. In the double via structure, the through via holes are small in diameter and more metal lines can be formed between two adjacent metal pads.
FIG. Γ6Β shows the comparison between a traditional blind via structure and a double via structure. In a double via structure, the through, via holes are small in diameter and more metal lines can be formed between two adjacent metal pads.
FIGS. 17 to 19, 19A, 19B, 20A and 20B are schematic views of a method for making a compact DSLD via structure. As shown in FIG. 17, a core substrate 24 is provided. The core substrate 24 has a first surface 241 and a second surface 242. DSLD via holes 25 are formed and penetrate through the substrate 24. The DSLD via hole 25 has its largest opening 251 at its both ends and its smallest opening 252 somewhere near its middle portion.
A first conductive layer 134 (not shown) is formed on the entire first surface 241 and the entire second surface 242 of the core substrate 24. The first conductive layer 134 also covers the DSLD via holes 25. A first photoresist layer 261 is formed on the first conductive layer 134 on the first surface 241. A second photoresist layer 262 is formed on the first conductive layer 134 on the second surface 242. Parts of the first photoresist layer 261 are removed to create openings 2610. Parts of the second photoresist layer 262 are removed to create openings 2620 as shown in FIG. 18.
A first conductive material 27 is electroplated on the openings 2610 and 2620 to form a first circuit 270 on the first surface 241 and a second circuit 280 on the second surface 242 simultaneously. The first circuit 270 comprises first metal pads 271 and first metal lines 272. The second circuit 280 comprises second metal pads 281 and second metal lines 282. The metal pads 271 and 281 are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening 252, given the misalignment that occurs during the process of forming the first and second circuits. And a compact DSLD via structure is formed as shown in FIG. 19.
FIG. 19A illustrates both the ideally desired position of the first and second circuits in a compact DSLD via structure and the misaligned position of them.
In a compact DSLD via structure, the metal pads 271 and 281 can be formed in the shape of a square or a rectangular for better coverage over the DSLD via hole. FIG. 19B illustrates both the ideally desired position of the first and second circuits in a compact DSLD via structure with rectangular metal pads and the misaligned position of them.
FIG. 20 A shows the comparison between a traditional DSLD via structure and a compact DSLD via structure. In the compact DSLD via structure, the metal pads are small in diameter so that more metal lines can be formed between two adjacent metal pads.
FIG. 20B shows the comparison between a traditional DSLD via structure and a compact DSLD via structure with rectangular metal pads. In the compact DSLD via structure with rectangular metal pads, the shorter edge of the metal pads are short in length so that more metal lines can be formed between two adjacent metal pads.
FIGS. 6, 21 , 21 A and 22 are schematic views of a method for making a compact substrate according to a first embodiment of the present invention.
A structure as shown in FIG. 6 is provided. A dielectric layer with reinforced fiber 29 is formed on the first solder resist layer 16 and the second circuit 180 by laminating process either with or without a metal foil 291 as shown in FIG. 21.
These processes can also be carried out on both sides of the earner 13 to form two identical structures as shown in FIG. 21 A.
The carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131. The detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150. A second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 2 is formed as shown in FIG. 22.
FIGS. 21, 21A and 23 are schematic views of a method for making a compact substrate according to another type of the first embodiment of the present invention. A structure as shown in FIG. 21 or FIG. 21 A is provided. The carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131. The detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150. A second vialess structure is formed on the second surface 1502 of the first circuit 150. The procedures of forming the second vialess structure are described as follows. A second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. A conductive layer 135 is formed on the second solder resist 30 and the exposed first metal pads 151 and exposed first metal lines 152. A photo resist layer 171 is formed on the conductive layer 135. Parts of the photo resist layer 171 are removed to form openings 1710. A conductive material 31 is electroplated on the openings 1710 to form a third circuit 310 comprising third metal pads 311 and third metal lines 312. The third metal pads 311 cover the exposed first metal pads 151 and exposed first metal lines 152. The photo resist layer 171 is removed followed by the removal of the conductive layer 135.
A third solder resist layer 32 is formed on the second solder resist layer 30 covering the third circuit 310. Parts of the third solder resist layer 32 are removed to expose parts of the third metal pads 311 and parts of the third metal lines 312. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 2A is formed as shown in FIG. 23.
There is a double vialess structure in substrate 2A, which is further illustrated in FIG. 24.
FIG. 24 shows schematic views of a double vialess structure where two vialess structures are formed on both sides of a metal line or a metal pad.
FIGS. 9, 25, 25A and 26 are schematic views of a method for making a compact substrate according to a second embodiment of the present invention. A structure as shown in FIG. 9 is provided. A dielectric layer with reinforced fiber 29 is formed on the first solder resist layer 16 and the second circuit 180 by laminating process either with or without a metal foil 291 as shown in FIG. 25.
These processes can also be carried out on both sides of the carrier 13 to form two identical structures as shown in FIG. 25 A.
The carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131. The detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150. A second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 3 is formed as shown in FIG. 26.
FIGS. 25, 25A and 27 illustrate schematic views of a method for making a compact substrate according to another type of the second embodiment of the present invention. A structure as shown in FIG. 25 or FIG. 25A is provided.
The carrier 13 is then removed by separating the two detachable layers 1311 and 1312 of the first conductive layer 131. The detachable layer 1312 and the metal foil 291 are also removed to expose the second surface 1502 of the first circuit 150. A second vialess structure is formed on the second surface 1502 of the first circuit 150. The procedures of forming the second vialess structure are described as follows. A second solder resist layer 30 is formed and covers the second surface 1502. Parts of the second solder resist 30 are removed to expose some of the first metal pads 151 and some of the first metal lines 152. A conductive layer 136 is formed on the second solder resist 30 and the exposed first metal pads 151 and exposed first metal lines 152. A photo resist layer 172 is formed on the conductive layer 136. Parts of the photo resist layer 172 are removed to form openings 1720. A conductive material 31 is electroplated on the openings 1720 to form a third circuit 310 comprising third metal pads 311 and third metal lines 312. The third metal pads 311 cover the exposed first metal pads 151 and exposed first metal lines 152. The photo resist layer 172 is removed followed by the removal of the conductive layer 136.
A third solder resist layer 32 is formed on the second solder resist layer 30 covering the third circuit 310. Parts of the third solder resist layer 32 are removed to expose parts of the third metal pads 311 and parts of the third metal lines 312. Parts of the dielectric layer with reinforced fiber 29 are removed by laser to expose parts of the second metal pads 181, and a substrate 3A is formed as shown in FIG. 27.
There is a double vialess structure in substrate 3A.
FIG. 28 illustrates schematic views of a method for making a compact substrate according to a third embodiment of the present invention. A double via structure as shown in FIG. 14 is provided.
A first vialess structure is formed on the first metal pads 221 and first metal lines 222. The procedures of forming the first vialess structure are described as follows. A first solder resist layer 40 is formed and covers the first circuit 220. Parts of the first solder resist 40 are removed to expose some of the first metal pads 221 and some of the first metal lines 222. A conductive layer 137 is formed on the first solder resist 40 and the exposed first metal pads 221 and exposed first metal lines 222. A photo resist layer 173 is formed on the conductive layer 137. Parts of the photo resist layer 173 are removed to form openings 1730. A conductive material 41 is electroplated on the openings 1730 to form a third circuit 410 comprising third metal pads 411 and third metal lines 412. The third metal pads 411 cover the exposed first metal pads 221 and exposed first metal lines 222. The photo resist layer 173 is removed followed by the removal of the conductive layer 137.
A second solder resist layer 42 is formed on the first solder resist layer 40 covering the third circuit 410. A third solder resist layer 43 is formed on the second circuit 230. Parts of the second solder resist layer 42 are removed to expose parts of the third metal pads 411 and parts of the third metal lines 412. Parts of the third solder resist layer 43 are removed to expose parts of the second metal pads 231 and parts of the second metal lines 232, and a substrate 4 is formed as shown in FIG. 28.
FIG. 29 illustrates schematic views of a method for making a compact substrate according to another type of the third embodiment of the present invention. A double via structure as shown in FIG. 14 is provided.
A first vialess structure is formed on the first metal pads 221 and first metal lines 222 and a second vialess structure is formed on the second metal pads 231 and second metal lines 232 simultaneously. The procedures of forming the first vialess structure and the second vialess structure are described as follows. A first solder resist layer 44 and second solder resist layer 45 are formed and covers the first circuit 220 and the second circuit 230 respectively. Parts of the first solder resist layer 44 are removed to expose some of the first metal pads 221 and some of the first metal lines 222. Parts of the second solder resist layer 45 are removed to expose some of the second metal pads 231 and some of the second metal lines 232. A conductive layer 138 is formed on the first solder resist layer 44 and second solder resist layer 45. The conductive layer 138 also covers the exposed first metal pads 221, exposed first metal lines 222, exposed second metal pads 231 and exposed second metal lines 232. A photo resist layer 174 is formed on the conductive layer 138 on the solder resist layer 44. A photo resist layer 175 is formed on the conductive layer 138 on the solder resist layer 45. Parts of the photo resist layer 174 are removed to form openings 1740. Parts of the photo resist layer 175 are removed to form openings 1750. A conductive material 46 is electroplated on the openings 1740 to form a third circuit 460 comprising third metal pads 461 and third metal lines 462 and on the openings 1750 to form a fourth circuit 470 comprising fourth metal pads 471 and fourth metal lines 472. The third metal pads 461 cover the exposed first metal pads 221 and exposed first metal lines 222 and the fourth metal pads 471 cover the exposed second metal pads 231 and exposed second metal lines 232. Both photo resist layer 174 and 175 are removed followed by the removal of the conductive layer 138.
A third and fourth solder resist layers 48 and 49 are formed where the third solder resist layer 48 is formed on the first solder resist layer 44 covering the third circuit 460 and fourth solder resist layer 49 is formed on the second solder resist layer 45 covering the fourth circuit 470. Parts of the third solder resist layer 48 are removed to expose parts of the third metal pads 461 and parts of the third metal lines 462. Parts of the fourth solder resist layer 49 are removed to expose parts of the fourth metal pads 471 and parts of the fourth metal lines 472, and a substrate 4A is formed as shown in FIG. 29.
FIG. 30 illustrates schematic views of a method for making a compact substrate according to a fourth embodiment of the present invention. A compact DSLD via structure as shown in FIG. 19 is provided.
A first vialess structure is formed on the first metal pads 271 and first metal lines 272 and a second vialess structure is formed on the second metal pads 281 and second metal lines 282 simultaneously. The procedures of forming the first vialess structure and the second vialess structure are described as follows. A first solder resist layer 51 and second solder resist layer 52 are formed and covers the first circuit 270 and the second circuit 280 respectively. Parts of the first solder resist layer 51 are removed to expose some of the first metal pads 271 and some of the first metal lines 272. Parts of the second solder resist layer 52 are removed to expose some of the second metal pads 281 and some of the second metal lines 282. A conductive layer 138 is formed on the first solder resist layer 51 and second solder resist layer 52. The conductive layer 138 also covers the exposed first metal pads 271, exposed first metal lines 272, exposed second metal pads 281 and exposed second metal lines 282. A photo resist layer 174 is formed on the conductive layer 138 on the solder resist layer 51. A photo resist layer 175 is formed on the conductive layer 138 on the solder resist layer 52. Parts of the photo resist layer 174 are removed to form openings 1740. Parts of the photo resist layer 175 are removed to form openings 1750. A conductive material 53 is electroplated on the openings 1740 to form a third circuit 530 comprising third metal pads 531 and third metal lines 532 and on the openings 1750 to form a fourth circuit 540 comprising fourth metal pads 541 and fourth metal lines 542. The third metal pads 531 cover the exposed first metal pads 271 and exposed first metal lines 272 and the fourth metal pads 541 cover the exposed second metal pads 281 and exposed second metal lines 282. Both photo resist layer 174 and 175 are removed followed by the removal of the conductive layer 138. A third and fourth solder resist layers 55 and 56 are formed where the third solder resist layer 55 is formed on the first solder resist layer 51 covering the third circuit 530 and fourth solder resist layer 56 is formed on the second solder resist layer 52 covering the fourth circuit 540. Parts of the third solder resist layer 55 are removed to expose parts of the third metal pads 531 and parts of the third metal lines 532. Parts of the fourth solder resist layer 56 are removed to expose parts of the fourth metal pads 541 and parts of the fourth metal lines 542, and a substrate 5 is formed as shown in FIG. 30.
Therefore, the compact substrates 2, 2A, 3, 3A, 4, 4A and 5 of the present invention have high density of layout; involve low manufacturing cost and shorter cycle time.
While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope defined in the appended claims.
PATENT CITATIONS
Publication
Cited Patent Filing date Applicant Title
date
Advanced Coreless substrate
US8416577 B2 Jan 21, 2010 . Apr 9, 2013 Semiconductor and method for gineenng, Inc making the same

Claims

> CLAIMS (26) What is claimed is:
1. A vialess structure, comprising:
a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer.
2. The vialess structure as claimed in claim 1, wherein the first circuit is formed by electroplating a single metal, an alloy or a series of a few metal layers.
3. The vialess structure as claimed in claim 1 , wherein the first solder resist layer can be formed from a photo-imageable dielectric material.
4. The vialess structure as claimed in claim 1, wherein the first solder resist layer is processed by photolithography processes including being exposed under UV light and being developed by an alkaline solution.
5. The vialess structure as claimed in claim 1, wherein the first solder resist layer is processed by laser.
6. The vialess structure as claimed in claim 1, wherein the second circuit is formed by electroplating.
7. The vialess structure as claimed in claim 1, further comprising:
a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines.
8. The vialess structure as claimed in claim 1, wherein the first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer, where the entire first surface and the entire second surface of the first circuit are not covered by the resin layer.
9. The vialess structure as claimed in claim 8, wherein the resin layer is formed by laminating a resin coated copper onto the first surface of the first circuit; followed by etching to remove the copper foil and desmearing or grinding the resin layer to expose the entire first surface of the first circuit.
10. A double vialess structure, comprising:
a first circuit comprising first metal pads and first metal lines and having a first surface and a second surface; a first solder resist layer covering the first surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second solder resist layer covering the second surface of the first circuit and exposing some of the first metal pads and some of the first metal lines; a second circuit formed on the first solder resist layer and containing second metal lines and second metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; a third circuit formed on the second solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the second solder resist layer.
11. The double vialess structure as claimed in claim 10, further comprising:
a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines.
12. The double vialess structure as claimed in claim 10, wherein the first circuit having a first surface and a second surface and comprising first metal pads and first metal lines embedded in a resin layer, where the entire first surface and the entire second surface of the first circuit are not covered by the resin layer.
13. The double vialess structure as claimed in claim 10, wherein the resin layer is formed by laminating a resin coated copper onto the first surface of the first circuit; followed by etching to remove the copper foil and desmearing or grinding the resin layer to expose the entire first surface of the first circuit.
14. The double vialess structure as claimed in claim 12, further comprising:
a dielectric layer with reinforced fiber laminated on top of the first solder resist layer covering the second circuit but exposing some of the second metal pads; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines.
15. A double via structure, comprising:
a core substrate having a first surface and a second surface; at least one double via hole comprising a blind via hole formed on the first surface of the core substrate and at least one through via hole formed at the base of the blind via hole. The double via hole penetrates through the core substrate; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate. Some first metal pads locate at the base of the blind via hole forming a pad in via structure; a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate. The second circuit connect to the first circuit through the double via holes.
16. The double via holes as described in claim 15, wherein the blind via hole is formed by laser or by laminating the core substrate on a pre-formed mold. The base of the blind via hole can be formed in the shape of a circle, a square or a rectangular. The through via hole is formed by laser.
17. The double via structure as claimed in claim 15, wherein an embedded flip chip bumps structure can be formed in the pad in via structure of the double via structure. After reflow process, the bumps of the Semiconductor die are embedded totally in the blind via holes of the double via structure.
18. The double via structure as claimed in claim 15, wherein the first and second circuits are formed in the same electroplating process.
19. The double via structure as claimed in claim 15, further comprising:
a first vialess structure formed on the first circuit comprising: a first solder resist layer covering the first circuit and exposing some of the first metal pads and some of the first metal lines; a third circuit formed on the first solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; a second solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; a third solder resist layer covering the second circuit and exposing some of the second metal pads and some of the second metal lines.
20. The double via structure as claimed in claim 15, further comprising:
a first vialess structure formed on the first circuit comprising: a first solder resist layer covering the first circuit and exposing some of the first metal pads and some of the first metal lines; a third circuit formed on the first solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; a second vialess structure formed on the second circuit comprising: a second solder resist layer covering the second circuit and exposing some of the second metal pads and some of the second metal lines; a fourth circuit formed on the second solder resist layer and containing fourth metal lines and fourth metal pads that are in contact with the exposed second metal pads and exposed second metal lines through the second solder resist layer; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines.
21. The double via structure as claimed in claim 20, wherein the first vialess structure and the second vialess structure are formed simultaneously.
22. A compact double sided laser drilled (DSLD) via structure, comprising:
a core substrate having a first surface and a second surface; at least one DSLD via hole having its largest opening at its both ends and its smallest opening somewhere near its middle portion. The DSLD via hole penetrates through the core substrate; a first circuit comprising first metal pads and first metal lines formed on the first surface of the substrate. The first metal pads are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening of the DSLD via hole, given the misalignment that occurs during the process of forming the first circuit; a second circuit comprising second metal pads and second metal lines formed on the second surface of the substrate. The second metal pads are formed with diameters large enough to cover at least three quarters the diameter of the smallest opening of the DSLD via hole, given the misalignment that occurs during the process of forming the second circuit. The second circuit connect to the first circuit through the DSLD via holes.
23. The compact DSLD via structure as claimed in claim 22, wherein the first and second circuits are formed in the same electroplating process.
24. The compact DSLD via structure as claimed in claim 22, wherein the first and second metal pads are formed in a square or rectangular shape for better coverage over the DSLD via holes.
25. The compact DSLD via structure as claimed in claim 22, further comprising:
a first vialess structure formed on the first circuit comprising: a first solder resist layer covering the first circuit and exposing some of the first metal pads and some of the first metal lines; a. third circuit formed on the first solder resist layer and containing third metal lines and third metal pads that are in contact with the exposed first metal pads and exposed first metal lines through the first solder resist layer; a second vialess structure formed on the second circuit comprising: a second solder resist layer covering the second circuit and exposing some of the second metal pads and some of the second metal lines; a fourth circuit formed on the second solder resist layer and containing fourth metal lines and fourth metal pads that are in contact with the exposed second metal pads and exposed second metal lines through the second solder resist layer; a third solder resist layer covering the third circuit and exposing some of the third metal pads and some of the third metal lines; a fourth solder resist layer covering the fourth circuit and exposing some of the fourth metal pads and some of the fourth metal lines.
26. The double via structure as claimed in claim 25, wherein the first vialess structure and the second vialess structure are formed simultaneously.
PCT/SG2014/000238 2014-05-30 2014-05-30 Compact substrate and method for making the same WO2015183184A1 (en)

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