KR101067074B1 - Printed circuit board and method for fabricating printed circuit board - Google Patents

Abstract

The present invention provides a method of manufacturing a printed circuit board, the method comprising: forming circuit patterns on a first carrier substrate and a second carrier substrate including a seed layer to provide a printed circuit board having improved via connection reliability; Placing an insulating layer between the formed circuit patterns, and heating and pressing the first and second carrier substrates to attach the insulating layers; Exposing the seed layer by separating the first and second carrier substrates; removing the seed layer of the first carrier substrate corresponding to a position where a via hole is to be formed; Removing a circuit pattern corresponding to a position where the via hole is to be formed among circuit patterns of the first carrier substrate; Forming the via hole by removing the insulating layer corresponding to the position where the via hole is to be formed; And simultaneously plating the via holes and the regions of the removed circuit pattern to form vias and via lands at the same time.

Description

Printed Circuit Board and Manufacturing Method of Printed Circuit Board {PRINTED CIRCUIT BOARD AND METHOD FOR FABRICATING PRINTED CIRCUIT BOARD}

The present invention relates to a printed circuit board and a method of manufacturing the same. More specifically, the laser drill processing for via processing is not performed through the via land, but the resin smear of the via land remains by directly laser processing the insulating layer. The present invention relates to a printed circuit board for a semiconductor package and a method of manufacturing the same, which can improve interlayer via connection reliability of a printed circuit board.

Recently, due to the trend toward miniaturization, light weight, thinness, and high functionality of electronic products, printed circuit boards for semiconductor packaging have also been required to be denser and thinner. Accordingly, various researches and developments on the implementation and thinning of high-density microcircuits are underway, and one of them is a circuit transfer method.

This is a method of forming a fine circuit in a semi-additive method on a carrier substrate including a metal seed layer, and then transferring to an insulating layer to achieve high circuit density and thinner substrate thickness. However, in the case of adopting such a method, if the desmear is not appropriate in the via land part after processing by using a drill, smear of the insulating layer remains, which may weaken the connection reliability after plating.

Hereinafter, a method of manufacturing a multilayer printed circuit board according to a conventional method will be described with reference to FIGS. 1A to 1G.

The circuit pattern 130 is formed on one surface of the first and second carrier substrates 110 and 120 including the metal seed layer. Two via lands 150 are formed on the first carrier substrate 110 at both ends of positions corresponding to later-formed vias of the circuit patterns 130 (FIG. 1A).

After the insulating layer 140 is disposed between the first and second carrier substrates 110 and 120 to be heated and pressed, only the seed layers 111 and 121 of the first and second carrier substrates 110 and 120 are pressed. Leave on (FIG. 1B).

The etching resist 160 is applied except for a region corresponding to the via land 150 (FIG. 1C), and a portion of the exposed seed layer 111 to which the etching resist 160 is not applied is removed (FIG. 1D). .

After removing a part of the seed layer 111, a via hole is formed in the insulating layer 140 using a laser drill, and desmeared after via processing. At this time, if the desmear process is not properly performed on the via land 150, a resin smear 170 remains on the side of the via land 150 (FIG. 1E).

Thereafter, the via 180 is plated by an electroplating method (FIG. 1F), and when the plating is completed, the seed layers 111 and 121 and the surface electrolytic plating layer 190 are removed.

As a result, there is still a resin smear 170 between the via 180 and the via land 150, which is a disadvantage of deteriorating the connection reliability (Fig. 1G).

The present invention has been proposed to solve the above problems, the object of which is to solve the problem that the resin smear of the via land by directly processing the insulating layer instead of the laser drill processing for via processing through the via land. The present invention provides a printed circuit board for a semiconductor package and a method of manufacturing the same, which may improve the interlayer via connection reliability of a printed circuit board by simultaneously plating the inside of the via and the via land.

The present invention provides a method of manufacturing a printed circuit board, the method comprising: forming circuit patterns on a first and a second carrier substrate including a seed layer to provide a printed circuit board having improved via connection reliability; Placing an insulating layer between the formed circuit patterns, and heating and pressing the first and second carrier substrates to attach the insulating layers; Exposing the seed layer by separating the first and second carrier substrates; removing the seed layer of the first carrier substrate corresponding to a position where a via hole is to be formed; Removing a circuit pattern corresponding to a position where the via hole is to be formed among circuit patterns of the first carrier substrate; Forming the via hole by removing the insulating layer corresponding to the position where the via hole is to be formed; And simultaneously plating regions of the via holes and the removed circuit patterns to simultaneously form vias and via lands.

In addition, it is preferable that step d) and step e) are performed simultaneously.

In addition, in the step g), it is preferable that the via and the vialand are integrally formed.

Further, in the step a), it is preferable to form a circuit pattern corresponding to the via land on the first carrier substrate.

In addition, the circuit pattern of step e) preferably corresponds to the via land.

The method may further include removing the seed layers of the first and second carrier substrates.

On the other hand, a printed circuit board having improved via connection reliability of the present invention includes: an insulating layer; First circuit patterns buried in one surface of the insulating layer; Second circuit patterns buried in the other surface of the insulating layer; And a via electrically connecting the first circuit pattern and the second circuit pattern, wherein the insulating layer has a predetermined thickness between the first circuit patterns and the second circuit patterns, and the first circuit pattern includes: The first circuit pattern connected to the via of the patterns is integrally formed with the via.

The first circuit pattern connected to the via of the first circuit pattern may be integrally formed by the same plating process as that of the via.

In the printed circuit board and the manufacturing method thereof according to the present invention, laser drilling for via processing is not performed through the via land, but directly processing the insulating layer, thereby solving the problem of resin smear in the via land remaining. The present invention provides a printed circuit board for a semiconductor package and a method of manufacturing the same, by simultaneously plating an inside and a via land, thereby improving reliability of interlayer via connection of the printed circuit board.

1A to 1G are cross-sectional views illustrating a method of manufacturing a multilayer printed circuit board according to the related art.
2A to 2G are cross-sectional views illustrating a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention.

The printed circuit board according to the present invention and a method for manufacturing the same will be clearly understood by the detailed description with reference to the accompanying drawings in which preferred embodiments of the present invention are shown, including the technical configuration for the above object.

Hereinafter, a method of manufacturing a multilayer printed circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2G.

2A is a cross-sectional view illustrating a process of forming a circuit pattern on a carrier substrate.

A first carrier substrate 210 comprising a seed layer 211 and consisting of three layers 211, 212 and 213, and a second carrier comprising a seed layer 221 and consisting of three layers 221, 222 and 223. The substrate 220 is prepared. Each of the layers 211, 212, 213, 221, 222, and 223 of the first and second carrier substrates 210 and 220 is made of a metal that is easily electroplated and etched.

Circuit patterns 230 are formed on the seed layers 211 and 221 of the first and second carrier substrates 210 and 220. The circuit pattern 230 may be formed by forming a plating resist corresponding to the circuit pattern 230, plating the circuit pattern 230 by electroplating, and then peeling off the plating resist. Additive method is adopted.

When the circuit pattern 230 is formed, a circuit pattern corresponding to the via land 270 to be subsequently formed on a portion of the seed layer 211 of the first carrier substrate 210 corresponding to the region where the via is to be formed later. 250 is formed. That is, in the conventional method, a circuit pattern of two via lands 150 disposed at both ends of the openings of vias to be formed later is formed. Corresponding circuit patterns 250 are formed. To this end, electroplating is performed at a position corresponding to the entire opening of the via to be formed later.

2B, the insulating layer 240 is positioned between the circuit patterns 230 of the formed first and second carrier substrates 210 and 220, and the first and second carrier substrates 210 and 220 are positioned. Is heated, pressurized and bonded. The seed layers 211 and 221 are exposed by separating the first and second carrier substrates 210 and 220. That is, the metal layers 212, 213, 222, and 223 except for the seed layers 211 and 221 of the first and second carrier substrates 210 and 220 are removed.

In order to form vias for connecting the first and second carrier substrates 210 and 220, photosensitive etching resists are formed on the seed layers 211 and 221 except for the region of the seed layer 211 on the circuit pattern 250. 260 is applied (FIG. 2C). Thereafter, an exposure process, a developing process, and an etching process are performed to remove the seed layer on the circuit pattern 250 and to remove the circuit pattern 250 (FIG. 2D). As a result, the seed layer on the circuit pattern 250 and the circuit pattern 250 are simultaneously removed by a single process.

After removing the seed layer on the circuit pattern 250 and the circuit pattern 250, via holes are formed in the insulating layer 240 under the removed region using a laser drill (FIG. 2E).

After the via processing, the desmear process is performed to remove the remaining foreign substances, and a thin plating layer serving as the seed layer is formed on the seed layers 211 and 221 and the via holes through an electroless chemical copper treatment. Thereafter, in order to increase the thickness of the plating layer, electroplating is performed by electroplating to form an electroplating layer 290 on the seed layers 211 and 221 of the first and second carrier substrates 210 and 220. .

Through the plating process, the via 280 and the via land 270 are plated with the same metal. That is, the via 280 and the via land 270 are integrally formed simultaneously through the same process (FIG. 2F). Therefore, even though the desmear process is conventionally performed, the resin smear 170, which must remain on the side of the via land 150, is formed between the via 180 and the via land 150 formed through the plating process. Resin smear 170 may remain to solve the problem of deteriorating inter-layer via connection reliability.

Subsequently, when via plating is completed for interlayer connection, an etching process is performed to remove the seed layers 211 and 221 of the electroplating layer 290 and the first and second carrier substrates 210 and 220 (FIG. 2G).

According to the method of manufacturing a printed circuit board according to the present invention, the laser drill via process is not performed through the via land (the circuit pattern 250 corresponding thereto), and the insulating layer 240 is processed directly to the via land 270. This can solve the problem of resin smear remaining. In addition, since the via 280 and the via land 270 are integrally formed at the same time through a single process, connection reliability may be improved after via plating.

As illustrated in FIG. 2G, a printed circuit board having improved via connection reliability according to an embodiment of the present invention may include an insulating layer 240, first circuit patterns 231, and second circuit pattern 232. And vias 280.

The first circuit patterns 231 are formed to be buried in one surface of the insulating layer 240, and the second circuit patterns 232 are formed to be buried in the other surface of the insulating layer 240. The insulating layer 240 has a predetermined thickness between the first circuit patterns 231 and the second circuit patterns 232.

The via 280 electrically connects the first circuit pattern 231, that is, the via land 270 and the second circuit pattern 232.

The first circuit pattern, ie, the via land 270, connected to the via of the first circuit patterns 231 is integrally formed with the via 280.

As described above with reference to FIGS. 2A to 2G, the via land 270 and the via 280 are integrally formed by the same plating process, thereby eliminating the possibility of foreign substances such as resin smears therebetween.

This is different from the conventional printed circuit board according to FIG. 1G. In other words, in FIG. 1G, the via land 150 is formed by the same process as the other circuit patterns 130 and is already formed before the via hole is processed. Therefore, there is a problem that smear may remain if the desmear treatment is not appropriate on the side after the via hole processing.

In addition, the vias 180 are formed by a process different from the via land 150 formed by the process of forming the circuit pattern 130 after the via holes are processed and the plating process is performed.

Due to the resin smear 170 and the via 180 and the via land 150 not integrally formed, the connection reliability after the via plating is deteriorated.

On the contrary, in the printed circuit board according to the exemplary embodiment of the present invention, the via 280 and the via land 270 are integrally formed by a single process to fundamentally block the problem with the resin smear, and thus, after the via plating, Can improve the ash.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications and changes within the scope of the technical spirit of the present invention for those skilled in the art to which the present invention pertains. Changes may be made, but such substitutions, changes and the like should be regarded as belonging to the following claims.

210: first carrier substrate 220: second carrier substrate
230: circuit pattern 240: insulating layer
250: circuit pattern corresponding to via land
260 photosensitive etching resist
270: Vialand 280: Via

Claims (8)

a) forming circuit patterns on the first and second carrier substrates including the seed layer;
b) placing an insulating layer between the formed circuit patterns, and heating and pressing the first and second carrier substrates to attach the insulating layers;
c) exposing the seed layer by separating the first and second carrier substrates;
d) removing the seed layer of the first carrier substrate corresponding to the position where the via hole is to be formed;
e) removing a circuit pattern corresponding to a position where the via hole is to be formed among circuit patterns of the first carrier substrate;
f) forming the via hole by removing the insulating layer corresponding to the position where the via hole is to be formed; And
g) simultaneously plating the via holes and regions of the removed circuit pattern to form vias and via lands at the same time;
And a step of forming the printed circuit board.
The method of claim 1,
And d) and e) are performed at the same time.
The method of claim 1,
And in step g), the via and the via land are integrally formed.
The method of claim 1,
In the step a), a circuit pattern for forming a printed circuit board corresponding to the via land on the first carrier substrate.
The method of claim 1,
The circuit pattern of step e) is a manufacturing method of a printed circuit board corresponding to the via land.
The method of claim 1,
And removing the seed layer of the first and second carrier substrates.
Insulating layer;
First circuit patterns buried in one surface of the insulating layer;
Second circuit patterns buried in the other surface of the insulating layer; And
A via electrically connecting the first circuit pattern and the second circuit pattern;
Including,
The insulating layer has a constant thickness between the first circuit patterns and the second circuit patterns,
The first circuit pattern of the first circuit patterns connected to the via is integrally formed with the via.
The method of claim 7, wherein
The first circuit pattern of the first circuit pattern connected to the via is integrally formed by the same plating process as the via.

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