JP5864044B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP5864044B2 JP5864044B2 JP2011157783A JP2011157783A JP5864044B2 JP 5864044 B2 JP5864044 B2 JP 5864044B2 JP 2011157783 A JP2011157783 A JP 2011157783A JP 2011157783 A JP2011157783 A JP 2011157783A JP 5864044 B2 JP5864044 B2 JP 5864044B2
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- oxide semiconductor
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- electrode
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- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Description
本実施の形態では、半導体装置および半導体装置の作製方法の一形態を、図1乃至図6を用いて説明する。
本実施の形態では、実施の形態1とは異なる、開示する発明の一態様に係る半導体装置の作製方法の一形態を、図7を参照して説明する。なお、図7において、図1乃至図3と対応する箇所については同じ符号を用い、同じ箇所の詳細な説明については省略する。
本実施の形態では、先の実施の形態に示す半導体装置の作製方法を用いて形成する半導体装置の一例として、記憶媒体(メモリ素子)を示す。本実施の形態では、先の実施の形態において示す半導体装置の作製方法で形成した、酸化物半導体を用いたトランジスタと、酸化物半導体以外の材料を用いたトランジスタとを同一基板上に形成する。
本実施の形態では、開示する発明の一態様に係る半導体装置の応用例について、図9を用いて説明する。
本実施の形態では、上述の実施の形態で説明した半導体装置を電子機器に適用する場合について、図10を用いて説明する。本実施の形態では、コンピュータ、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯情報端末(携帯型ゲーム機、音響再生装置なども含む)、デジタルカメラ、デジタルビデオカメラ、電子ペーパー、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)などの電子機器に、上述の半導体装置を適用する場合について説明する。
102 酸化物半導体層
102a 第1の結晶性酸化物半導体層
102b 第2の結晶性酸化物半導体層
104a ソース電極
104b ドレイン電極
106a 絶縁層
106b 絶縁層
108 ゲート絶縁層
110 導電層
110a ゲート電極
110b 導電層
110c 配線
112 絶縁膜
112a 絶縁膜
114a レジストマスク
114b レジストマスク
116 絶縁膜
116a 絶縁膜
120 導電層
120a ゲート電極
120b 導電層
120c 配線
151 絶縁層
152 絶縁層
154 電極
156 配線
200 トランジスタ
210 トランジスタ
220 トランジスタ
230 トランジスタ
240 トランジスタ
250 トランジスタ
300 トランジスタ
400 基板
406 素子分離絶縁層
408 ゲート絶縁層
410 ゲート電極
416 チャネル形成領域
420 不純物領域
424 金属化合物領域
428 絶縁層
430 絶縁層
500 トランジスタ
510 トランジスタ
520 容量素子
550 メモリセル
601 筐体
602 筐体
603 表示部
604 キーボード
611 本体
612 スタイラス
613 表示部
614 操作ボタン
615 外部インターフェイス
620 電子書籍
621 筐体
623 筐体
625 表示部
627 表示部
631 電源
633 操作キー
635 スピーカー
637 軸部
640 筐体
641 筐体
642 表示パネル
643 スピーカー
644 マイクロフォン
645 操作キー
646 ポインティングデバイス
647 カメラ用レンズ
648 外部接続端子
649 太陽電池セル
650 外部メモリスロット
661 本体
663 接眼部
664 操作スイッチ
665 表示部
666 バッテリー
667 表示部
670 テレビジョン装置
671 筐体
673 表示部
675 スタンド
680 リモコン操作機
Claims (7)
- 絶縁表面上に、酸化物半導体層と、前記酸化物半導体層と接する領域を有するソース電極と、前記酸化物半導体層と接する領域を有するドレイン電極と、前記ソース電極上の第1の絶縁層と、前記ドレイン電極上の第2の絶縁層と、を形成し、
前記酸化物半導体層上、前記ソース電極上、前記ドレイン電極上、前記第1及び前記第2の絶縁層上にゲート絶縁層を形成し、
前記ソース電極と前記ドレイン電極とに挟まれた領域の少なくとも一部と重畳するように、前記ゲート絶縁層上に導電層を形成し、
前記導電層を覆うように絶縁膜を形成し、
前記導電層における前記ソース電極または前記ドレイン電極と重畳する領域の少なくとも一部が露出するように前記絶縁膜を加工し、
前記導電層の露出した領域をエッチングして、前記ソース電極と前記ドレイン電極とに挟まれた領域の少なくとも一部と重畳するゲート電極を自己整合的に形成し、
前記ゲート電極の前記ゲート絶縁層の最上面より上部は、前記ソース電極および前記ドレイン電極とは重畳しないことを特徴とする半導体装置の作製方法。 - 絶縁表面上に、酸化物半導体層と、前記酸化物半導体層と接する領域を有するソース電極と、前記酸化物半導体層と接する領域を有するドレイン電極と、前記ソース電極上の絶縁層と、前記ドレイン電極上の絶縁層と、を形成し、
前記酸化物半導体層上、前記ソース電極上、前記ドレイン電極上、および前記絶縁層上にゲート絶縁層を形成し、
前記ソース電極と前記ドレイン電極とに挟まれた領域の少なくとも一部と重畳するように、前記ゲート絶縁層上に導電層を形成し、
前記ゲート絶縁層における前記ソース電極または前記ドレイン電極と重畳する領域の少なくとも一部が露出するように前記導電層を加工して、前記ソース電極と前記ドレイン電極とに挟まれた領域の少なくとも一部と重畳するゲート電極を自己整合的に形成し、
前記ゲート電極の上面は、前記ゲート絶縁層の最上面より低い領域を有することを特徴とする半導体装置の作製方法。 - 請求項1又は2において、
前記ソース電極および前記ドレイン電極は、少なくとも前記酸化物半導体層の上面の一部と接することを特徴とする半導体装置の作製方法。 - 請求項1乃至3のいずれか一において、
前記酸化物半導体層は、少なくとも前記ソース電極および前記ドレイン電極の上面の一部と接することを特徴とする半導体装置の作製方法。 - 請求項1乃至4のいずれか一において、
前記ゲート電極を形成する際に残存した前記導電層の一部を加工して、配線を形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至5のいずれか一において、
前記ソース電極の端部と前記ドレイン電極の端部との間隔が10nm以上200nm以下であることを特徴とする半導体装置の作製方法。 - 請求項1乃至6のいずれか一において、
前記酸化物半導体層は、In、Ga、及びZnを有することを特徴とする半導体装置の作製方法。
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KR101915251B1 (ko) | 2009-10-16 | 2018-11-06 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
KR20120091243A (ko) | 2009-10-30 | 2012-08-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
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2011
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- 2011-07-19 JP JP2011157783A patent/JP5864044B2/ja not_active Expired - Fee Related
- 2011-07-27 US US13/192,161 patent/US9559211B2/en active Active
- 2011-07-28 TW TW105113605A patent/TWI588870B/zh not_active IP Right Cessation
- 2011-07-28 TW TW100126776A patent/TWI541855B/zh active
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JP6178836B2 (ja) | 2017-08-09 |
TWI541855B (zh) | 2016-07-11 |
JP2012049514A (ja) | 2012-03-08 |
WO2012014786A1 (en) | 2012-02-02 |
US20120025191A1 (en) | 2012-02-02 |
TW201220352A (en) | 2012-05-16 |
TW201732875A (zh) | 2017-09-16 |
US20170236848A1 (en) | 2017-08-17 |
US9559211B2 (en) | 2017-01-31 |
TW201631627A (zh) | 2016-09-01 |
TWI588870B (zh) | 2017-06-21 |
JP2016076725A (ja) | 2016-05-12 |
TWI629708B (zh) | 2018-07-11 |
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