JP6717815B2 - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP6717815B2 JP6717815B2 JP2017520039A JP2017520039A JP6717815B2 JP 6717815 B2 JP6717815 B2 JP 6717815B2 JP 2017520039 A JP2017520039 A JP 2017520039A JP 2017520039 A JP2017520039 A JP 2017520039A JP 6717815 B2 JP6717815 B2 JP 6717815B2
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Description
本発明の一態様は、第1の絶縁体上に第2の絶縁体を成膜し、第2の絶縁体上に半導体を成膜し、半導体上に第1の導電体を成膜し、第1の導電体、半導体および第2の絶縁体の一部をエッチングすることで第1の導電体、半導体および第2の絶縁体を有する多層膜を形成し、第1の絶縁体上および多層膜上に第3の絶縁体を成膜し、第3の絶縁体上に第2の導電体を成膜し、第2の導電体上に第4の絶縁体を成膜し、第4の絶縁体上にリソグラフィー法によってレジストマスクを形成し、レジストマスクをマスクとして、第4の絶縁体の一部をエッチングすることで第1の絶縁層を形成し、レジストマスクおよび第1の絶縁層をマスクとして、第2の導電体の一部をエッチングすることで第1の導電体層を形成し、第4の絶縁体の一部のエッチングおよび第2の導電体の一部のエッチングによってレジストマスクを消失させ、第1の絶縁層および第1の導電体層をマスクとして、第3の絶縁体をエッチングすることで、第3の絶縁体に開口部を形成し、第3の絶縁体のエッチングによって第1の絶縁層を消失させ、第1の導電体層をマスクとして、第1の導電体を半導体が露出するまでエッチングすることで、第1の導電体を第2の導電体層と第3の導電体層とに分離し、第1の導電体のエッチングによって第1の導電体層を消失させ、第3の絶縁体上および半導体上に第5の絶縁体を成膜し、第5の絶縁体上に第6の絶縁体を成膜し、第6の絶縁体上に第3の導電体を成膜し、第3の導電体、第6の絶縁体および第5の絶縁体を化学的機械研磨することで第3の絶縁体を露出させ、第1の導電体は第2の導電体の有する主成分元素を有することを特徴とする半導体装置の作製方法である。
または、本発明の一態様は、第3の絶縁体および第4の絶縁体は、酸化シリコンを含む絶縁体であることを特徴とする(1)に記載の半導体装置の作製方法である。
<トランジスタ構造1>
以下では、本発明の一態様に係る半導体装置が有するトランジスタの構造について説明する。
ここでは、図1と異なる構成のトランジスタについて、図2を用いて説明する。図2(A)、(B)および(C)は、本発明の一態様に係る半導体装置の上面図および断面図である。図2(A)は上面図である。図2(B)は、図2(A)に示す一点鎖線A1−A2に対応する断面図である。図2(C)は、図2(A)に示す一点鎖線A3−A4に対応する断面図である。なお、図2(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
ここでは、図2と異なる構成のトランジスタについて、図4を用いて説明する。図4(A)、(B)および(C)は、本発明の一態様に係る半導体装置の上面図および断面図である。図4(A)は上面図である。図4(B)は、図4(A)に示す一点鎖線A1−A2に対応する断面図である。図4(C)は、図4(A)に示す一点鎖線A3−A4に対応する断面図である。なお、図4(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
ここでは、図2と異なる構成のトランジスタについて、図5を用いて説明する。図5(A)、(B)および(C)は、本発明の一態様に係る半導体装置の上面図および断面図である。図5(A)は上面図である。図5(B)は、図5(A)に示す一点鎖線A1−A2に対応する断面図である。図5(C)は、図5(A)に示す一点鎖線A3−A4に対応する断面図である。なお、図5(A)の上面図では、図の明瞭化のために一部の要素を省いて図示している。
<酸化物半導体の構造>
以下では、酸化物半導体の構造について説明する。
まずは、CAAC−OSについて説明する。
次に、nc−OSについて説明する。
a−like OSは、nc−OSと非晶質酸化物半導体との間の構造を有する酸化物半導体である。
<トランジスタの作製方法>
以下では、本発明に係る図1のトランジスタの作製方法を図12から図26を用いて説明する。
<記憶装置1>
本発明の一態様に係るトランジスタを用いた、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を図27に示す。
図28は、図27(A)に対応する半導体装置の断面図である。図28に示す半導体装置は、トランジスタ3200と、トランジスタ3300と容量素子3400と、を有する。また、トランジスタ3300および容量素子3400は、トランジスタ3200の上方に配置する。なお、トランジスタ3300としては、図1に示したトランジスタを用いた例を示しているが、本発明の一態様に係る半導体装置は、これに限定されるものではない。よって適宜上述したトランジスタについての記載を参酌する。
図27(B)に示す半導体装置は、トランジスタ3200を有さない点で図27(A)に示した半導体装置と異なる。この場合も図27(A)に示した半導体装置と同様の動作により情報の書き込みおよび保持動作が可能である。
<半導体装置の構造2>
本実施の形態では、本発明の一態様のトランジスタを利用した回路の一例について図面を参照して説明する。
<断面構造>
図30(A)および(B)に本発明の一態様の半導体装置の断面図を示す。図30(A)において、X1−X2方向はチャネル長方向、図30(B)において、Y1−Y2方向はチャネル幅方向を示す。図30(A)および(B)に示す半導体装置は、下部に第1の半導体材料を用いたトランジスタ2200を有し、上部に第2の半導体材料を用いたトランジスタ2100を有している。図30(A)および(B)では、第2の半導体材料を用いたトランジスタ2100として、図4に例示したトランジスタを適用した例を示している。
〔CMOS回路〕
図30(C)に示す回路図は、pチャネル型のトランジスタ2200とnチャネル型のトランジスタ2100を直列に接続し、かつそれぞれのゲートを接続した、いわゆるCMOS回路の構成を示している。
また図30(D)に示す回路図は、トランジスタ2100とトランジスタ2200のそれぞれのソースとドレインを接続した構成を示している。このような構成とすることで、いわゆるアナログスイッチとして機能させることができる。本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。
<CPU>
以下では、上述したトランジスタや上述した記憶装置などの半導体装置を含むCPUについて説明する。
<撮像装置>
図33(A)は、本発明の一態様に係る撮像装置200の例を示す上面図である。撮像装置200は、画素部210と、画素部210を駆動するための周辺回路260と、周辺回路270、周辺回路280と、周辺回路290と、を有する。画素部210は、p行q列(pおよびqは2以上の整数)のマトリクス状に配置された複数の画素211を有する。周辺回路260、周辺回路270、周辺回路280および周辺回路290は、それぞれ複数の画素211に接続し、複数の画素211を駆動するための信号を供給する機能を有する。なお、本明細書等において、周辺回路260、周辺回路270、周辺回路280および周辺回路290などの全てを指して「周辺回路」または「駆動回路」と呼ぶ場合がある。例えば、周辺回路260は周辺回路の一部といえる。
撮像装置200が有する1つの画素211を複数の副画素212で構成し、それぞれの副画素212に特定の波長帯域の光を透過するフィルタ(カラーフィルタ)を組み合わせることで、カラー画像表示を実現するための情報を取得することができる。
以下では、シリコンを用いたトランジスタと、本発明に係る酸化物半導体を用いたトランジスタと、を用いて画素を構成する一例について説明する。
<RFタグ>
本実施の形態では、先の実施の形態で説明したトランジスタ、または記憶装置を含むRFタグについて、図37を参照して説明する。
<表示装置>
以下では、本発明の一態様に係る表示装置について、図38、図39および図40を用いて説明する。
本実施の形態では、本発明の一態様の半導体装置を適用した表示モジュールについて、図41を用いて説明を行う。
図41に示す表示モジュール6000は、上部カバー6001と下部カバー6002との間に、FPC6003に接続されたタッチパネル6004、FPC6005に接続された表示パネル6006、バックライトユニット6007、フレーム6009、プリント基板6010、バッテリー6011を有する。なお、バックライトユニット6007、バッテリー6011、タッチパネル6004などは、設けられない場合もある。
<リードフレーム型のインターポーザを用いたパッケージ>
図42(A)に、リードフレーム型のインターポーザを用いたパッケージの断面構造を表す斜視図を示す。図42(A)に示すパッケージは、本発明の一態様に係る半導体装置に相当するチップ551が、ワイヤボンディング法により、インターポーザ550上の端子552と接続されている。端子552は、インターポーザ550のチップ551がマウントされている面上に配置されている。そしてチップ551はモールド樹脂553によって封止されていてもよいが、各端子552の一部が露出した状態で封止されるようにする。
本実施の形態では、本発明の一態様の電子機器および照明装置について、図面を用いて説明する。
本発明の一態様の半導体装置を用いて、電子機器や照明装置を作製できる。また、本発明の一態様の半導体装置を用いて、信頼性の高い電子機器や照明装置を作製できる。また本発明の一態様の半導体装置を用いて、タッチセンサの検出感度が向上した電子機器や照明装置を作製できる。
本実施の形態では、本発明の一態様に係る半導体装置を用いたRFタグの使用例について図46を用いながら説明する。
RFタグの用途は広範にわたるが、例えば、紙幣、硬貨、有価証券類、無記名債券類、証書類(運転免許証や住民票等、図46(A)参照)、乗り物類(自転車等、図46(B)参照)、包装用容器類(包装紙やボトル等、図46(C)参照)、記録媒体(DVDやビデオテープ等、図46(D)参照)、身の回り品(鞄や眼鏡等)、食品類、植物類、動物類、人体、衣類、生活用品類、薬品や薬剤を含む医療品、または電子機器(液晶表示装置、EL表示装置、テレビジョン装置、または携帯電話)等の物品、若しくは各物品に取り付ける荷札(図46(E)、図46(F)参照)等に設けて使用することができる。
201 スイッチ
202 スイッチ
203 スイッチ
210 画素部
211 画素
212 副画素
212B 副画素
212G 副画素
212R 副画素
220 光電変換素子
230 画素回路
231 配線
247 配線
248 配線
249 配線
250 配線
253 配線
254 フィルタ
254B フィルタ
254G フィルタ
254R フィルタ
255 レンズ
256 光
257 配線
260 周辺回路
270 周辺回路
280 周辺回路
290 周辺回路
291 光源
300 シリコン基板
301 絶縁体
302 絶縁体
303 電子捕獲層
305 層
310a 導電体
310b 導電体
310c 導電体
320 層
331 層
340 層
351 トランジスタ
352 トランジスタ
353 トランジスタ
354 トランジスタ
360 フォトダイオード
361 アノード
362 カソード
363 低抵抗領域
365 フォトダイオード
366 半導体層
367 半導体層
368 半導体層
370 プラグ
371 配線
372 配線
373 配線
374 配線
380 絶縁体
381 絶縁体
400 基板
401 絶縁体
402 絶縁体
403w 開口寸法
404 導電体
404a 導電体
404w 間隔
406a 絶縁体
406a_1 絶縁体
406b 半導体
406b_1 半導体
406c 絶縁体
406c_1 絶縁体
407 領域
408 絶縁体
410 絶縁体
410a 絶縁体
412 絶縁体
412a 絶縁体
414 導電体
415 導電体
416a1 導電体
416a2 導電体
417 導電体
417a 導電体
418 絶縁体
419 絶縁体
419a 絶縁体
420 レジストマスク
421a 有機塗布膜
428 絶縁体
429 導電体
430 導電体
431 導電体
432 導電体
433 導電体
434 導電体
437 導電体
438 導電体
440 導電体
442 導電体
444 導電体
450 半導体基板
454 導電体
460 領域
462 絶縁体
464 絶縁体
465 絶縁体
466 絶縁体
467 絶縁体
468 絶縁体
469 絶縁体
470 絶縁体
472 絶縁体
474a 領域
474b 領域
475 絶縁体
476a 導電体
476b 導電体
476c 導電体
477a 導電体
477b 導電体
477c 導電体
478a 導電体
478b 導電体
478c 導電体
479a 導電体
479b 導電体
479c 導電体
480a 導電体
480b 導電体
480c 導電体
483a 導電体
483b 導電体
483c 導電体
483d 導電体
483e 導電体
483f 導電体
484a 導電体
484b 導電体
484c 導電体
484d 導電体
485a 導電体
485b 導電体
485c 導電体
485d 導電体
487a 導電体
487b 導電体
487c 導電体
488a 導電体
488b 導電体
488c 導電体
489a 導電体
489b 導電体
490a 導電体
490b 導電体
491a 導電体
491b 導電体
491c 導電体
492a 導電体
492b 導電体
492c 導電体
494 導電体
496 導電体
498 絶縁体
550 インターポーザ
551 チップ
552 端子
553 モールド樹脂
600 パネル
601 プリント配線基板
602 パッケージ
603 FPC
604 バッテリー
700 基板
704a 導電体
704b 導電体
706a 絶縁体
706b 半導体
706c 絶縁体
706d 絶縁体
706e 半導体
706f 絶縁体
710 絶縁体
712a 絶縁体
714a 導電体
714b 導電体
716a1 導電体
716a2 導電体
716a3 導電体
716a4 導電体
718a 絶縁体
718b 絶縁体
719 発光素子
720 絶縁体
721 絶縁体
728 絶縁体
731 端子
732 FPC
733a 配線
734 シール材
735 駆動回路
736 駆動回路
737 画素
741 トランジスタ
742 容量素子
743 スイッチ素子
744 信号線
750 基板
751 トランジスタ
752 容量素子
753 液晶素子
754 走査線
755 信号線
781 導電体
782 発光層
783 導電体
784 隔壁
791 導電体
792 絶縁体
793 液晶層
794 絶縁体
795 スペーサ
796 導電体
797 基板
800 RFタグ
801 通信器
802 アンテナ
803 無線信号
804 アンテナ
805 整流回路
806 定電圧回路
807 復調回路
808 変調回路
809 論理回路
810 記憶回路
811 ROM
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
1200 記憶素子
1201 回路
1202 回路
1203 スイッチ
1204 スイッチ
1206 論理素子
1207 容量素子
1208 容量素子
1209 トランジスタ
1210 トランジスタ
1213 トランジスタ
1214 トランジスタ
1220 回路
2100 トランジスタ
2200 トランジスタ
2201 絶縁体
2202 配線
2203 プラグ
2204 絶縁体
2205 配線
2207 絶縁体
2208 絶縁体
2211 半導体基板
2212 絶縁体
2213 ゲート電極
2214 ゲート絶縁体
2215 ソース領域およびドレイン領域
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3200 トランジスタ
3300 トランジスタ
3400 容量素子
4000 RFタグ
4500 OG
6000 表示モジュール
6001 上部カバー
6002 下部カバー
6003 FPC
6004 タッチパネル
6005 FPC
6006 表示パネル
6007 バックライトユニット
6008 光源
6009 フレーム
6010 プリント基板
6011 バッテリー
7101 筐体
7102 筐体
7103 表示部
7104 表示部
7105 マイク
7106 スピーカー
7107 操作キー
7108 スタイラス
7302 筐体
7304 表示部
7311 操作ボタン
7312 操作ボタン
7313 接続端子
7321 バンド
7322 留め金
7501 筐体
7502 表示部
7503 操作ボタン
7504 外部接続ポート
7505 スピーカー
7506 マイク
7701 筐体
7702 筐体
7703 表示部
7704 操作キー
7705 レンズ
7706 接続部
7921 電柱
7922 表示部
8000 カメラ
8001 筐体
8002 表示部
8003 操作ボタン
8004 シャッターボタン
8005 結合部
8006 レンズ
8100 ファインダー
8101 筐体
8102 表示部
8103 ボタン
8121 筐体
8122 表示部
8123 キーボード
8124 ポインティングデバイス
8200 ヘッドマウントディスプレイ
8201 装着部
8202 レンズ
8203 本体
8204 表示部
8205 ケーブル
8206 バッテリー
9700 自動車
9701 車体
9702 車輪
9703 ダッシュボード
9704 ライト
9710 表示部
9711 表示部
9712 表示部
9713 表示部
9714 表示部
9715 表示部
9721 表示部
9722 表示部
9723 表示部
Claims (2)
- 第1の絶縁体上に第2の絶縁体を成膜し、
前記第2の絶縁体上に半導体を成膜し、
前記半導体上に第1の導電体を成膜し、
前記第1の導電体の一部、前記半導体の一部および前記第2の絶縁体の一部をエッチングすることで前記第1の導電体、前記半導体および前記第2の絶縁体を有する多層膜を形成し、
前記第1の絶縁体上および前記多層膜上に第3の絶縁体を成膜し、
前記第3の絶縁体上に第2の導電体を成膜し、
前記第2の導電体上に第4の絶縁体を成膜し、
前記第4の絶縁体上にレジストマスクを形成し、
前記レジストマスクをマスクとして、前記第4の絶縁体の一部をエッチングすることで第1の絶縁層を形成し、
前記レジストマスクおよび前記第1の絶縁層をマスクとして、前記第2の導電体の一部をエッチングすることで第1の導電体層を形成し、
前記第4の絶縁体の一部をエッチングすること、および前記第2の導電体の一部をエッチングすることで前記レジストマスクを消失させ、
前記第1の絶縁層および前記第1の導電体層をマスクとして、前記第3の絶縁体をエッチングすることで前記第3の絶縁体に開口部を形成し、
前記第3の絶縁体をエッチングすることで前記第1の絶縁層を消失させ、
前記第1の導電体層をマスクとして、前記半導体が露出するように前記第1の導電体をエッチングすることで前記第1の導電体から第2の導電体層と第3の導電体層とを形成し、
前記第1の導電体をエッチングすることで前記第1の導電体層を消失させ、
前記第3の絶縁体上および前記半導体上に第5の絶縁体を成膜し、
前記第5の絶縁体上に第6の絶縁体を成膜し、
前記第6の絶縁体上に第3の導電体を成膜し、
前記第3の導電体、前記第6の絶縁体および前記第5の絶縁体を化学的機械研磨することで前記第3の絶縁体を露出させ、
前記第1の導電体は前記第2の導電体の有する主成分元素を有することを特徴とする半導体装置の作製方法。 - 前記第3の絶縁体および前記第4の絶縁体は、酸化シリコンを含む絶縁体であることを特徴とする請求項1に記載の半導体装置の作製方法。
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