JP5603600B2 - 配線基板及びその製造方法、並びに半導体パッケージ - Google Patents

配線基板及びその製造方法、並びに半導体パッケージ Download PDF

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Publication number
JP5603600B2
JP5603600B2 JP2010005017A JP2010005017A JP5603600B2 JP 5603600 B2 JP5603600 B2 JP 5603600B2 JP 2010005017 A JP2010005017 A JP 2010005017A JP 2010005017 A JP2010005017 A JP 2010005017A JP 5603600 B2 JP5603600 B2 JP 5603600B2
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Prior art keywords
layer
wiring
insulating layer
wiring board
electrode pad
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JP2010005017A
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Japanese (ja)
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JP2011146477A (ja
JP2011146477A5 (enExample
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順一 中村
和弘 小林
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2010005017A priority Critical patent/JP5603600B2/ja
Priority to US12/968,405 priority patent/US8525356B2/en
Priority to TW099144418A priority patent/TWI500373B/zh
Priority to KR1020110000067A priority patent/KR101764686B1/ko
Publication of JP2011146477A publication Critical patent/JP2011146477A/ja
Publication of JP2011146477A5 publication Critical patent/JP2011146477A5/ja
Priority to US13/911,259 priority patent/US8673744B2/en
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
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US12/968,405 US8525356B2 (en) 2010-01-13 2010-12-15 Wiring substrate, manufacturing method thereof, and semiconductor package
TW099144418A TWI500373B (zh) 2010-01-13 2010-12-17 配線基板、其製造方法、以及半導體封裝
KR1020110000067A KR101764686B1 (ko) 2010-01-13 2011-01-03 배선 기판, 그 제조 방법, 및 반도체 패키지
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5590985B2 (ja) * 2010-06-21 2014-09-17 新光電気工業株式会社 半導体装置及びその製造方法
US8802554B2 (en) * 2011-02-15 2014-08-12 Marvell World Trade Ltd. Patterns of passivation material on bond pads and methods of manufacture thereof
US10074600B2 (en) 2012-03-30 2018-09-11 Ati Technologies Ulc Method of manufacturing interposer-based damping resistor
TWI562295B (en) 2012-07-31 2016-12-11 Mediatek Inc Semiconductor package and method for fabricating base for semiconductor package
US10991669B2 (en) 2012-07-31 2021-04-27 Mediatek Inc. Semiconductor package using flip-chip technology
US9177899B2 (en) 2012-07-31 2015-11-03 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
EP2897447A4 (en) * 2012-09-11 2016-05-25 Meiko Electronics Co Ltd METHOD FOR PRODUCING A SUBSTRATE WITH AN EMBEDDED COMPONENT AND SUBSTRATE PRODUCED IN THIS METHOD WITH AN EMBEDDED COMPONENT
JP6092555B2 (ja) * 2012-09-24 2017-03-08 新光電気工業株式会社 配線基板の製造方法
US9035194B2 (en) * 2012-10-30 2015-05-19 Intel Corporation Circuit board with integrated passive devices
US20140167900A1 (en) 2012-12-14 2014-06-19 Gregorio R. Murtagian Surface-mount inductor structures for forming one or more inductors with substrate traces
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP6291738B2 (ja) 2013-07-25 2018-03-14 富士通株式会社 回路基板、回路基板の製造方法及び電子機器
JP2015032649A (ja) * 2013-08-01 2015-02-16 イビデン株式会社 配線板の製造方法および配線板
DE102013218404A1 (de) * 2013-09-13 2015-03-19 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zu seiner Herstellung
KR20150064445A (ko) * 2013-12-03 2015-06-11 삼성전기주식회사 반도체 패키지용 코어리스 기판 및 그 제조 방법, 이를 이용한 반도체 패키지 제조 방법
CN104701185B (zh) * 2013-12-06 2018-01-02 碁鼎科技秦皇岛有限公司 封装基板、封装结构以及封装基板的制作方法
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9679841B2 (en) * 2014-05-13 2017-06-13 Qualcomm Incorporated Substrate and method of forming the same
JP2016039290A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板および半導体パッケージ
JP2016039302A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板とその製造方法および半導体パッケージ
JP5795415B1 (ja) 2014-08-29 2015-10-14 新光電気工業株式会社 配線基板及びその製造方法
JP6510884B2 (ja) * 2015-05-19 2019-05-08 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
US9691699B2 (en) * 2015-11-03 2017-06-27 Unimicron Technology Corp. Circuit structure and method for manufacturing the same
KR102534940B1 (ko) * 2016-07-28 2023-05-22 삼성전기주식회사 인쇄회로기판
JP7271081B2 (ja) * 2017-10-18 2023-05-11 日東電工株式会社 配線回路基板
US10147721B1 (en) 2017-12-20 2018-12-04 Advanced Micro Devices, Inc. Method and apparatus for dynamic calibration of on-die-precision-resistors
JP7448309B2 (ja) * 2018-11-27 2024-03-12 日東電工株式会社 配線回路基板およびその製造方法
JP2020202205A (ja) * 2019-06-06 2020-12-17 イビデン株式会社 プリント配線板とプリント配線板の製造方法
US12089329B2 (en) 2019-12-04 2024-09-10 Lg Innotek Co., Ltd. Printed circuit board comprising via portions
JP2022047385A (ja) * 2020-09-11 2022-03-24 キオクシア株式会社 プリント配線基板およびメモリシステム
JP7216139B2 (ja) * 2021-04-20 2023-01-31 Ｆｉｃｔ株式会社 回路基板の製造方法

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835950A (ja) * 1981-08-28 1983-03-02 Hitachi Ltd 半導体装置
JPS59134840A (ja) * 1982-12-02 1984-08-02 Stanley Electric Co Ltd オ−ミツク接続された金属電極の像および位置を照明により検知する方法およびシステム
JPH078447B2 (ja) * 1987-08-06 1995-02-01 株式会社神戸製鋼所 薄板加工用ドリル
JPH03268316A (ja) * 1990-03-16 1991-11-29 Fujitsu Ltd 半導体装置の製造方法
US5627110A (en) * 1994-10-24 1997-05-06 Advanced Micro Devices, Inc. Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used
JP3855320B2 (ja) 1996-10-16 2006-12-06 株式会社トッパンＮｅｃサーキットソリューションズ 半導体装置用基板の製造方法及び半導体装置の製造方法
EP0952762B1 (en) * 1996-12-19 2011-10-12 Ibiden Co, Ltd. Printed wiring board and method for manufacturing the same
US5898227A (en) * 1997-02-18 1999-04-27 International Business Machines Corporation Alignment targets having enhanced contrast
US6156243A (en) * 1997-04-25 2000-12-05 Hoya Corporation Mold and method of producing the same
JPH1140908A (ja) 1997-07-22 1999-02-12 Ibiden Co Ltd プリント配線板
WO1999021224A1 (en) * 1997-10-17 1999-04-29 Ibiden Co., Ltd. Package substrate
WO1999034654A1 (en) * 1997-12-29 1999-07-08 Ibiden Co., Ltd. Multilayer printed wiring board
EP1583407B1 (en) * 1998-02-26 2007-05-30 Ibiden Co., Ltd. Multilayer printed wiring board with filled viaholes
JP4797310B2 (ja) * 2000-09-29 2011-10-19 住友ベークライト株式会社 アライメントマーク
JP3546961B2 (ja) * 2000-10-18 2004-07-28 日本電気株式会社 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
JP2004047898A (ja) * 2002-07-15 2004-02-12 Sumitomo Bakelite Co Ltd プリント配線板の製造方法及び多層プリント配線板の製造方法
JP3987781B2 (ja) * 2002-09-30 2007-10-10 日本特殊陶業株式会社 配線基板の製造方法
JP2004200187A (ja) * 2002-12-16 2004-07-15 Nikon Corp プリント配線板
US20050067378A1 (en) * 2003-09-30 2005-03-31 Harry Fuerhaupter Method for micro-roughening treatment of copper and mixed-metal circuitry
TW200806144A (en) * 2004-02-04 2008-01-16 Ibiden Co Ltd Multilayer printed wiring board
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
JP2006216711A (ja) * 2005-02-02 2006-08-17 Ibiden Co Ltd 多層プリント配線板
JP4768994B2 (ja) * 2005-02-07 2011-09-07 ルネサスエレクトロニクス株式会社 配線基板および半導体装置
JP2006278929A (ja) * 2005-03-30 2006-10-12 Shinko Electric Ind Co Ltd フレキシブル回路基板の製造方法
TWI294678B (en) * 2006-04-19 2008-03-11 Phoenix Prec Technology Corp A method for manufacturing a coreless package substrate
US7911038B2 (en) * 2006-06-30 2011-03-22 Renesas Electronics Corporation Wiring board, semiconductor device using wiring board and their manufacturing methods
JP5214139B2 (ja) * 2006-12-04 2013-06-19 新光電気工業株式会社 配線基板及びその製造方法
JP2008258520A (ja) * 2007-04-09 2008-10-23 Shinko Electric Ind Co Ltd 配線基板の製造方法及び配線基板
JP2009194321A (ja) * 2008-02-18 2009-08-27 Shinko Electric Ind Co Ltd 配線基板及びその製造方法、半導体パッケージ
JP4256454B2 (ja) * 2008-09-01 2009-04-22 新光電気工業株式会社 配線基板の製造方法及び配線基板
JP5203108B2 (ja) * 2008-09-12 2013-06-05 新光電気工業株式会社 配線基板及びその製造方法
US8365402B2 (en) * 2008-09-30 2013-02-05 Ibiden Co., Ltd. Method for manufacturing printed wiring board
JP5561460B2 (ja) * 2009-06-03 2014-07-30 新光電気工業株式会社 配線基板および配線基板の製造方法

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US8525356B2 (en) 2013-09-03
JP2011146477A (ja) 2011-07-28
TW201136481A (en) 2011-10-16
TWI500373B (zh) 2015-09-11
KR101764686B1 (ko) 2017-08-03
US20130269185A1 (en) 2013-10-17
KR20110083506A (ko) 2011-07-20
US8673744B2 (en) 2014-03-18

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