JP2011146477A - 配線基板及びその製造方法、並びに半導体パッケージ - Google Patents
配線基板及びその製造方法、並びに半導体パッケージ Download PDFInfo
- Publication number
- JP2011146477A JP2011146477A JP2010005017A JP2010005017A JP2011146477A JP 2011146477 A JP2011146477 A JP 2011146477A JP 2010005017 A JP2010005017 A JP 2010005017A JP 2010005017 A JP2010005017 A JP 2010005017A JP 2011146477 A JP2011146477 A JP 2011146477A
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- Prior art keywords
- layer
- wiring
- alignment mark
- wiring board
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
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- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
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- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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Abstract
【解決手段】本配線基板は、絶縁層と、前記絶縁層の表面に形成された凹部内に設けられた位置合わせマークと、を有し、前記位置合わせマークの一方の面は、粗化面とされており、前記一方の面は、前記絶縁層の前記表面に対して窪んだ位置に露出している。
【選択図】図7
Description
[第1の実施の形態に係る配線基板の構造]
始めに、第1の実施の形態に係る配線基板の構造について説明する。図7は、第1の実施の形態に係る配線基板を例示する断面図である。図7を参照するに、配線基板10は、第1配線層11、第1絶縁層12、第2配線層13、第2絶縁層14、第3配線層15、第3絶縁層16、第4配線層17、ソルダーレジスト層18が順次積層された構造を有する。
続いて、第1の実施の形態に係る配線基板の製造方法について説明する。図8〜図20は、第1の実施の形態に係る配線基板の製造工程を例示する図である。図8〜図20において、図7と同一部品については、同一符号を付し、その説明は省略する場合がある。
第2の実施の形態では、図7に示す配線基板10の他の製造方法について例示する。図22〜図25は、第2の実施の形態に係る配線基板の製造工程を例示する図である。図22〜図25において、図7と同一部品については、同一符号を付し、その説明は省略する場合がある。
第3の実施の形態では、図7に示す配線基板10の他の製造方法について例示する。図26は、第3の実施の形態に係る配線基板の製造工程を例示する図である。図26において、図7と同一部品については、同一符号を付し、その説明は省略する場合がある。
第4の実施の形態では、図7に示す配線基板10の凹部12yの深さを調整する方法について例示する。
第5の実施の形態では、配線基板10に半導体チップを搭載した半導体パッケージについて例示する。
始めに、第5の実施の形態に係る半導体パッケージの構造について説明する。図32は、第5の実施の形態に係る半導体パッケージを例示する断面図である。図32において、図7と同一部品については、同一符号を付し、その説明は省略する場合がある。
続いて、第5の実施の形態に係る半導体パッケージの製造方法について説明する。図33及び図34は、第5の実施の形態に係る半導体パッケージの製造工程を例示する図である。図33及び図34において、図21及び図32と同一部品については、同一符号を付し、その説明は省略する場合がある。
第5の実施の形態では、電極パッド11aを半導体チップ搭載用の電極パッドとして用い、位置合わせマーク11bを半導体チップを搭載する際の位置合わせの基準等として用いる例を示した。第5の実施の形態の変形例では、電極パッド11aをチップキャパシタ等の各種電子部品搭載用の電極パッドやマザーボード等の実装基板と接続するための外部接続端子を形成する電極パッド(BGAパッドやPGAパッド)として用い、位置合わせマーク11bをチップキャパシタ等の各種電子部品や外部接続端子となるはんだボール等を搭載する際の位置合わせの基準等として用いる例を示す。第5の実施の形態の変形例において、第5の実施の形態と共通する部分についてはその説明を省略し、第5の実施の形態と異なる部分を中心に説明する。
11 第1配線層
11a 電極パッド
11b 位置合わせマーク
11s、12a、12b、23s 面
12 第1絶縁層
12x 第1ビアホール
12y 凹部
13 第2配線層
14 第2絶縁層
14x 第2ビアホール
15 第3配線層
16 第3絶縁層
16x 第3ビアホール
17 第4配線層
18 ソルダーレジスト層
18x、22x、22y 開口部
21 支持体
22 レジスト層
23 金属層
24 深さ調整層
40、40A 半導体パッケージ
50 半導体チップ
51 半導体基板
52 電極パッド
55 チップキャパシタ
56 はんだ
57 外部接続端子
60 はんだバンプ
61、62 プレソルダー
70 アンダーフィル樹脂
91 光源
92 受光部
Claims (10)
- 絶縁層と、前記絶縁層の表面に形成された凹部内に設けられた位置合わせマークと、を有し、
前記位置合わせマークの一方の面は、粗化面とされており、
前記一方の面は、前記絶縁層の前記表面に対して窪んだ位置に露出している配線基板。 - 前記位置合わせマークの側面と他方の面は、前記絶縁層と接していることを特徴とする請求項1記載の配線基板。
- 支持体の一方の面に金属層を形成する第1工程と、
前記金属層に位置合わせマークとなる配線層を積層形成する第2工程と、
前記金属層及び前記位置合わせマークとなる配線層を覆うように、前記支持体の前記一方の面に絶縁層を形成する第3工程と、
前記位置合わせマークとなる配線層の一方の面を粗化面とする工程、及び前記位置合わせマークとなる配線層の一方の面を前記絶縁層から露出する露出面とする工程を含む第4工程と、を有する配線基板の製造方法。 - 前記第2工程は、前記金属層の前記支持体と接する面の反対面を粗化面とする第2A工程と、
前記金属層の前記反対面に位置合わせマークとなる配線層を積層形成し、前記位置合わせマークとなる配線層の前記反対面と接する面に前記粗化面を転写する第2B工程と、を有し、
前記第4工程では、前記支持体及び前記金属層を除去して、前記粗化面が転写された前記位置合わせマークとなる配線層の前記反対面と接していた面を前記絶縁層から露出する露出面とする請求項3記載の配線基板の製造方法。 - 前記第2A工程では、前記支持体を給電層に利用する電解めっき法により前記金属層を形成すると同時に、前記金属層の前記支持体と接する面の反対面を粗化面とする請求項4記載の配線基板の製造方法。
- 前記第2A工程では、エッチング又はブラスト処理により前記金属層の前記支持体と接する面の反対面を粗化面とする請求項4記載の配線基板の製造方法。
- 前記第4工程では、前記支持体及び前記金属層を除去して前記位置合わせマークとなる配線層の一方の面を前記絶縁層から露出する露出面とした後、エッチング又はブラスト処理により前記露出面を粗化面とする請求項3記載の配線基板の製造方法。
- 前記支持体と前記金属層とは異なる材料で構成されており、
前記第4工程は、前記支持体を所定のエッチング液で除去した後、前記金属層を前記所定のエッチング液とは異なるエッチング液で除去する工程を含む請求項3乃至7の何れか一項記載の配線基板の製造方法。 - 前記第1工程では、支持体の一方の面に深さ調整層を形成後、更に前記深さ調整層に金属層を積層形成し、
前記第4工程は、前記支持体、前記深さ調整層、及び前記金属層を除去して前記位置合わせマークとなる配線層の一方の面を前記絶縁層から露出する露出面とする工程を含む請求項3乃至8の何れか一項記載の配線基板の製造方法。 - 請求項1又は2記載の配線基板と、
前記配線基板に搭載された半導体チップと、を有する半導体パッケージ。
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JP2010005017A JP5603600B2 (ja) | 2010-01-13 | 2010-01-13 | 配線基板及びその製造方法、並びに半導体パッケージ |
US12/968,405 US8525356B2 (en) | 2010-01-13 | 2010-12-15 | Wiring substrate, manufacturing method thereof, and semiconductor package |
TW099144418A TWI500373B (zh) | 2010-01-13 | 2010-12-17 | 配線基板、其製造方法、以及半導體封裝 |
KR1020110000067A KR101764686B1 (ko) | 2010-01-13 | 2011-01-03 | 배선 기판, 그 제조 방법, 및 반도체 패키지 |
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JP2016219559A (ja) * | 2015-05-19 | 2016-12-22 | 新光電気工業株式会社 | 配線基板及びその製造方法と電子部品装置 |
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JP2020202205A (ja) * | 2019-06-06 | 2020-12-17 | イビデン株式会社 | プリント配線板とプリント配線板の製造方法 |
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US20110169164A1 (en) | 2011-07-14 |
TWI500373B (zh) | 2015-09-11 |
JP5603600B2 (ja) | 2014-10-08 |
KR101764686B1 (ko) | 2017-08-03 |
US20130269185A1 (en) | 2013-10-17 |
TW201136481A (en) | 2011-10-16 |
KR20110083506A (ko) | 2011-07-20 |
US8525356B2 (en) | 2013-09-03 |
US8673744B2 (en) | 2014-03-18 |
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