CN101683004A - 多层印刷线路板的制造方法 - Google Patents
多层印刷线路板的制造方法 Download PDFInfo
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- CN101683004A CN101683004A CN200880001309A CN200880001309A CN101683004A CN 101683004 A CN101683004 A CN 101683004A CN 200880001309 A CN200880001309 A CN 200880001309A CN 200880001309 A CN200880001309 A CN 200880001309A CN 101683004 A CN101683004 A CN 101683004A
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Abstract
提出一种能够妥当地获取与内置电子部件之间的连接的多层印刷线路板的制造方法。在芯基板(30)上形成定位标记(31),以该定位标记(31)为基准在层间树脂绝缘层(50)上形成向IC芯片(20)的焊盘(24)的连接用通路孔(60)。因此,能够在IC芯片(20)的焊盘(24)上正确地形成通路孔(60),能够可靠地连接焊盘(24)与通路孔(60)。
Description
技术领域
本发明涉及一种积层多层印刷线路板的制造方法,特别涉及一种内置有IC芯片等有源元件、芯片电容器等无源元件等电子部件的多层印刷线路板的制造方法。
背景技术
相关技术的记述
IC芯片通过引线接合、TAB、倒装法等安装方法来获取与印刷线路板之间的电连接。另外,芯片电容器被表面安装在基板上。IC芯片的安装方法通过连接用导线部件(引线、导线、凸块)对IC芯片与印刷线路板之间进行电连接。这些各导线部件容易被切断、腐蚀,由此,有时与IC芯片之间的连接中断、或者成为误动作的原因。另外,当表面安装芯片电容器时,到IC芯片的配线长度变长。
因此,在日本特开2001-332863号、日本特开2002-246757号中公开有如下的印刷线路板的制造方法:在形成在芯基板上的凹部内收容IC芯片,通过在该芯基板上层叠层间树脂绝缘层和导体电路而将IC芯片内置在封装基板内。
专利文献1:日本特开2001-332863号公报
专利文献2:日本特开2002-246757号公报
然而,在日本特开2001-332863号的制造方法中,利用激光在基板上穿设成为定位标记的凹坑,因此树脂残渣容易残留在凹坑内部,由于残渣的凹凸而有时无法正确地进行利用图像识别进行的与定位标记之间的位置对准。因此,有可能产生该IC芯片的焊盘与通路孔(Via Hole)之间的位置偏差而无法取得电连接。
发明内容
发明要解决的问题。
本发明的目的在于提供一种能够妥当地获取与内置电子部件的端子之间的连接的多层印刷线路板的制造方法。
用于解决问题的方案
本发明是一种多层印刷线路板的制造方法,在具有第一面和与该第一面相反侧的第二面的基板上反复形成层间绝缘层和导体层,在该层间绝缘层上形成通路孔,通过该通路孔进行电连接,该多层印刷线路板的制造方法的技术特征在于,具备以下工序:
在上述基板上的第一面上形成导体电路和第一定位标记的工序;
在上述基板上形成贯通孔的工序;
配置密封构件的工序,该密封构件被设置在上述基板上的第二面上,堵塞上述贯通孔;
根据上述基板的第一定位标记将电子部件收容在上述贯通孔内的工序;
在上述基板的第一面上形成层间绝缘层的工序;以及
根据上述基板的第一定位标记在上述层间绝缘层上形成到达上述电子部件的端子的通路孔用开口的工序。
在权利要求1中,在基板上的第一面上形成导体电路和第一定位标记。然后,在基板上形成贯通孔,在基板上的第二面上配置堵塞贯通孔的密封构件。接着,根据基板的第一定位标记将电子部件收容在贯通孔内。然后,在基板的第一面上形成层间绝缘层,根据第一定位标记在层间绝缘层上形成到达电子部件的端子的通路孔用开口。因此,容易进行定位标记的图像识别,能够使电子部件与位置正确吻合地在基板上的层间绝缘层上形成通路孔。
另外,还能够根据第一定位标记进行加工。这种情况下的加工意味着作为电子部件的IC芯片或者形成在基板上的所有部分。例如,存在IC芯片焊盘上的过渡层、识别文字(字母、数字等)、定位标记等。
另外,这种情况下的形成意味着在施加到芯基板上的层间绝缘层(不包括玻璃布等增强材料)上形成的所有部分。例如,存在通路孔、配线、识别文字(字母、数字等)、定位标记等。
作为在本申请发明中使用的、内置有IC芯片等电子部件的树脂制基板,使用层压浸渍了树脂、环氧树脂的预浸料而得到的基板等,能够使用通常在印刷线路板中使用的基板,其中,上述预浸料是在环氧树脂、BT树脂、酚醛树脂等中浸渍玻璃环氧树脂等增强材料、芯材而得到的。除此以外还能够使用两面覆铜层叠板、单面板、不具有金属膜的树脂板、树脂薄膜。其中,当施加350℃以上的温度时树脂溶解、炭化。
作为在本申请发明中使用的IC芯片,可以是裸芯片,也可以是在芯片焊盘上形成了连接芯片焊盘与通路孔的中间层的芯片,也可以是在芯片焊盘上形成再配线层的芯片,并且也可以是在再配线层上连接了柱状电极的芯片。另外,再配线层也可以是两层以上。
附图说明
图1的(A)、(B)、(C)、(D)是本发明的第一实施方式所涉及的多层印刷线路板的制造工序图。
图2的(A)、(B)、(C)、(D)是第一实施方式所涉及的多层印刷线路板的制造工序图。
图3的(A)、(B)、(C)、(D)是第一实施方式所涉及的多层印刷线路板的制造工序图。
图4的(A)、(B)、(C)、(D)、(E)是第一实施方式所涉及的多层印刷线路板的制造工序图。
图5的(A)、(B)、(C)、(D)是第一实施方式所涉及的多层印刷线路板的制造工序图。
图6的(A)、(B)、(C)、(D)是第一实施方式所涉及的多层印刷线路板的制造工序图。
图7是本发明的第一实施方式所涉及的多层印刷线路板的截面图。
图8的(A)、(B)、(C)、(D)、(E)是第一实施方式的改变例所涉及的多层印刷线路板的制造工序图。
图9的(A)、(B)、(C)、(D)、(E)是本发明的第二实施方式所涉及的多层印刷线路板的制造工序图。
图10的(A)、(B)、(C)、(D)是第二实施方式所涉及的多层印刷线路板的制造工序图。
图11是本发明的第二实施方式所涉及的多层印刷线路板的截面图。
图12的(A)、(B)、(C)是本发明的第三实施方式所涉及的多层印刷线路板的制造工序图。
图13的(A)、(B)、(C)、(D)是第三实施方式所涉及的多层印刷线路板的制造工序图。
图14的(A)、(B)、(C)是第三实施方式所涉及的多层印刷线路板的制造工序图。
图15是本发明的第三实施方式所涉及的多层印刷线路板的截面图。
图16是本发明的第四实施方式所涉及的多层印刷线路板的截面图。
附图标记说明
20:IC芯片(电子部件);24:焊盘;25:胶带;27:铜箔;30:芯基板;32:贯通孔;38:过渡层;50:层间树脂绝缘层;58:导体电路;60:通路孔;70:阻焊层;76:焊锡凸块;120:芯片电容器(电子部件);140:IC芯片;150:层间树脂绝缘层;158:导体电路;160:通路孔。
具体实施方式
[第一实施方式]
下面,参照附图说明本发明的实施方式。首先,参照示出多层印刷线路板10的截面的图7来说明本发明的第一实施方式所涉及的多层印刷线路板的结构。
如图7所示,多层印刷线路板10由收容IC芯片20的芯基板30、层间树脂绝缘层50以及层间树脂绝缘层150构成。在层间树脂绝缘层50上形成有通路孔60和导体电路58,在层间树脂绝缘层150上形成有通路孔160和导体电路158。
在IC芯片20上覆盖有钝化膜22,在该钝化膜22的开口内配置有构成输入输出端子的芯片焊盘24以及定位标记23。在焊盘24上形成有主要由铜构成的过渡层38。
在层间树脂绝缘层150上配置有阻焊层70。在阻焊层70的开口部71下的导体电路158上设置有焊锡凸块76,该焊锡凸块76用于与未图示的子板、母板等外部基板连接。
在本实施方式的多层印刷线路板10中,预先在芯基板30中内置IC芯片20,在该IC芯片20的焊盘24上配置有过渡层38。因此,不使用导线部件、密封树脂就能够获取IC芯片与多层印刷线路板(封装基板)之间的电连接。
另外,通过在芯片焊盘24上设置铜制的过渡层38,能够防止在焊盘24上残留树脂,另外,在后面的工序时,即使浸渍在酸、氧化剂或蚀刻液中、或者经过各种退火工序,焊盘24也不会产生变色、溶解。由此提高IC芯片的焊盘与通路孔之间的连接性、可靠性。并且,在直径40μm的焊盘24上插入直径60μm以上的过渡层38,由此能够可靠地连接直径60μm的通路孔。
并且,在后述的制造工序中,以形成在芯基板30上的定位标记31为基准来对IC芯片20进行定位,对照该定位标记31来形成向IC芯片20的焊盘24的连接用通路孔60。因此,能够使通路孔60正确地位置对准在IC芯片20的焊盘24上,从而可靠地连接焊盘24与通路孔60。
接着,参照图1~图6说明参照图7所说明的上述多层印刷线路板的制造方法。首先,参照图1和图2说明向IC芯片的焊盘上形成中间层38的工序。
(1)在图1的(A)示出的硅晶圆20A上形成有焊盘24、定位标记23、配线(未图示),在芯片焊盘22、定位标记23以及配线(未图示)上覆盖有钝化膜22,在芯片焊盘22以及定位标记23上设置有钝化膜的开口22a。
(2)首先,对硅晶圆22A进行蒸镀、溅射等物理蒸镀,在整个面上形成导电性金属膜(薄膜层)33(图1的(B))。作为其金属由锡、铬、钛、镍、锌、钴、金、铜等金属的一种以上的金属形成。特别由镍、铬、钛形成为宜。这是由于这些金属不会从界面浸入湿气,金属密合性好。根据情况,也可以用不同的金属形成两层以上。作为厚度,优选的是形成在0.001~2.0μm之间。特别期望0.01~1.0μm。
(3)还可以在金属膜33上利用无电解镀来形成镀膜36(图1的(C))。所形成的镀膜的种类存在铜、镍、金、银等。考虑电特性、经济性、并且在后面工序中形成的积层即导体层主要为铜,因此优选使用铜。其厚度优选在0.01~5.0μm范围内。在不足0.01μm时,无法在整个面上形成镀膜,当超过5.0μm时,难以利用蚀刻进行去除,或者导致定位标记被埋而无法进行识别。期望范围是0.1~3.0μm。此外,期望第一薄膜层与第二薄膜层的组合为铬-铜、铬-镍、钛-铜、钛-镍。在与金属之间的接合性、电传导性这一点上优于其它组合。
(4)之后,施加抗蚀剂35α,载置描绘有与焊盘24对应的图案39a以及定位标记39b的掩模39(图1的(D))。从上方照射光,在利用照相机80拍摄来自定位标记23的反射光的同时进行该掩模35的定位,使得硅晶圆20A的定位标记23进入到定位标记39b内。在本实施方式中,在定位标记23上也形成有铜镀膜36,因此反射光容易透过抗蚀剂35α,能够容易地进行基板与掩模的位置对准。
(5)进行曝光、显影,在硅晶圆20A的焊盘24的上部设置开口地形成抗镀层35,实施电解镀来设置电解镀膜37(图2的(A))。在去除抗镀层35之后,去除抗镀层35下的无电解镀膜36、金属膜33,由此在IC芯片的焊盘24上形成中间层38(图2的(B))。在此,通过抗镀层来加工中间层,但是也可以在无电解镀膜36上形成电解镀膜之后形成抗蚀涂层,进行曝光、显影,使中间层以外的部分的金属曝光并进行蚀刻,从而在IC芯片的焊盘上形成中间层。电解镀膜能够以镍、铜、金、银、锌、铁形成。电解镀膜的厚度优选在1~20μm的范围内。这是因为如果厚度超过20μm,有时会导致在蚀刻时产生凹槽而在所形成的中间层与通路孔的界面上产生间隙。
(6)接着,用喷雾器对硅晶圆20A喷涂蚀刻液,对中间层38的表面进行蚀刻,由此形成粗化面38α(参照图2的(C))。也能够使用无电解镀、氧化还原处理来形成粗化面。
(7)最后,通过切割等将形成有中间层38的硅晶圆20A分割为个片从而形成IC芯片20(参照图2的(D))。之后,也可以根据需要对分割得到的IC芯片20进行动作确认、电检查。在IC芯片20上形成有大于焊盘24的中间层38,因此探针脚容易接触,检查精确度提高。
接着,说明IC芯片20向芯基板的收容工序。
(1)首先,将由单面覆铜层叠板构成的绝缘树脂基板(芯基板)30设为初始材料,其中,上述单面覆铜层叠板是层叠了预浸料并层压了铜箔26而得到的(参照图3的(A)),该预浸料是将玻璃布等芯材浸渍环氧等树脂而得到的。在铜箔26上形成规定图案的抗蚀涂层,去除没有形成抗蚀涂层的部分的铜箔,剥离抗蚀涂层,由此形成定位标记31以及导体电路28(参照图3的(B))。接着,在芯基板30上形成IC芯片收容用的贯通孔32,在贯通孔32的底部侧贴树脂制胶带25(参照图3的(C))。这种情况下的贯通孔32能够通过钻、激光、刳刨加工、模具加工中的任一种来进行开口。另外,这种情况下的树脂制胶带优选在常温下具有粘合性的胶带。此时,可以用比贯通孔稍大的尺寸局部地设置树脂制胶带,也可以在芯基板的整个面上设置树脂制胶带。在此,通过加工来设置贯通孔部,但是也能够通过粘合设置有开口的绝缘树脂基板来形成具备收容部的芯基板。其中,绝缘树脂基板在350℃以上的温度下会溶解、炭化。
(2)之后,以芯基板30的定位标记31为基准,使用IC芯片20上的定位标记23对IC芯片20进行位置对准,将IC芯片20载置在胶带25上(参照图3的(D))。然后,按压IC芯片20的上表面使其完全收容到贯通孔32内(参照图4的(A))。将这种情况下的贯通孔32的侧壁与收容在贯通孔内的IC芯片20之间的空隙C调整为30~200μm的范围内即可。更优选调整为30~100μm的范围内即可。
(3)在经过了上述工序的基板30的上表面如下地设置由环烯烃系树脂构成的层间树脂绝缘层50(参照图4的(B)):对厚度50μm的热固化型环烯烃系树脂板将温度升温到50~150℃的同时以压力5kg/cm2进行真空压接层压。真空压接时的真空度为10mmHg。此时,通过收容了IC芯片12后的贯通孔32内的空隙被从层间树脂绝缘层50浸出的树脂填充而被假固化,以此将IC芯片固定在贯通孔32内。作为这种情况下的层间树脂绝缘层50,能够使用使玻璃布等芯材浸渍环氧树脂而形成为半固化的板状的预浸料。
(4)剥离背面侧的树脂胶带25,在基板50的背面真空压接层压热固化型环烯烃系树脂板,以此设置层间树脂绝缘层50(参照图4的(C))。根据本实施方式中的IC芯片20向芯基板的收容工序,能够以定位标记31为基准进行高精确度的位置对准,因此能够将贯通孔32的侧壁与IC芯片20之间的空隙C调整为30~200μm的范围内。由此,能够利用从层间树脂层浸出的树脂没有气泡残留地可靠地填充收容了IC芯片后的贯通孔内的空隙,并且能够减少浸出树脂的量,因此能够确保贯通孔上部区域的层间树脂绝缘层与其以外的区域的层间树脂层之间的平坦性。另外,当使用预浸料作为层间树脂绝缘层时,通过玻璃布等芯材能够进一步确保平坦性。另外,通过使用具有粘合性的树脂制胶带,不需要另外使用芯片粘接用粘接剂就能够将IC芯片固定在贯通孔的规定位置。
(5)接着,利用照相机80透过层间树脂绝缘层50拍摄定位标记31来进行位置对准,利用波长10.4μm的CO2气体激光,在波束直径5mm、脉宽5.0μ秒钟、掩模孔直径0.5mm、发射一次的条件下,在层间树脂绝缘层50上设置直径80μm的通路孔用开口48(参照图4的(D))。也可以使用铬酸等去除开口48内的树脂残留。通过在芯片焊盘24上设置铜制的过渡层38,能够防止焊盘24上的树脂残留,由此提高焊盘24与后述的通路孔60之间的连接性、可靠性。并且,通过在直径40μm的焊盘24上插入直径60μm以上的过渡层38,能够可靠地连接直径60μm的通路孔用开口48。此外,在此使用铬酸除去树脂残留,但是也能够使用氧等离子进行表面沾污去除处理。
(6)接着,通过浸渍在铬酸、高锰酸盐等氧化剂等中来设置层间树脂绝缘层50的粗化面50α(参照图4的(E))。优选在0.1~5μm的范围内形成该粗化面50α。作为其一例,通过在高锰酸钠溶液50g/l、温度60℃中浸渍5~25分钟来设置2~3μm的粗化面50α。除了上述方法以外,也能够使用日本真空技术株式会社制的SV-4540进行等离子处理,在层间树脂绝缘层50的表面形成粗化面50α。此时,使用氩气作为惰性气体,在电力200W、气压0.6Pa、温度70℃的条件下,实施两分钟等离子处理。
(7)在形成了粗化面50α的层间树脂绝缘层50上设置金属层52(参照图5的(A))。通过无电解镀来形成金属层52。预先在层间树脂绝缘层50的表层上附加钯等催化剂,浸渍在无电解镀液中5~60分钟,由此在0.1~5μm的范围内设置镀膜即金属层52。作为其一例,在34℃的液温度下在以下无电解镀水溶液中浸渍40分钟。
[无电解镀水溶液]
NiSO4 0.003mol/l
酒石酸 0.200mol/l
硫酸铜 0.030mol/l
HCHO 0050mol/l
NaOH 0.100mol/l
α、α’-二吡啶基 100mg/l
聚乙二醇(PEG) 0.10g/l
除了上述方法以外,使用与上述的等离子处理相同的装置,在交换内部的氩气之后,在气压0.6Pa、温度80℃、电力200W、时间5分钟的条件下进行以Ni和Cu为对象的溅射,也能够在层间树脂绝缘层50的表面形成Ni/Cu金属层52。此时,所形成的Ni/Cu金属层52的厚度为0.2μm。
(8)在结束了上述处理的基板30上粘贴市场上出售的感光性干膜54α,载置描绘了与焊盘对应的图案53a以及定位标记53b的光掩模53。从上方照射光,在利用照相机80拍摄来自定位标记31的反射光的同时进行该掩模53的定位,使得芯基板30侧的定位标记31进入到环状定位标记53b内。此外,如上所述,还能够在定位标记31上设置铜镀膜来提高表面的反射率。
(9)之后,在以100mJ/cm2曝光之后,用0.8%的碳酸钠进行显影处理,设置厚度15μm的抗镀层54(图5的(C))。
(10)接着,在以下条件下实施电解镀,形成厚度15μm的电解镀膜56(参照图5的(D))。此外,电解镀水溶液中的添加剂是日本ATOTECH公司(アトテツクジヤパン社)制的KAPARASHIDO(カパラシド)HL。
[电解镀水溶液]
硫酸 2.24mol/l
硫酸铜 0.26mol/l
添加剂(日本ATOTECH公司制的KAPARASHIDO(カパラシド)HL) 19.5ml/l
[电解镀条件]
电流密度 1A/dm2
时间 65分钟
温度 22±2℃
(11)在利用5%的NaOH剥离去除抗镀层54之后,通过使用硝酸以及硫酸和过氧化氢的混合液的蚀刻来溶解去除该抗镀层下的Ni-Cu合金层52,形成由Ni-Cu合金层52和电解镀膜56构成的厚度16μm的导体电路58和通路孔60,利用含有二价铜络合物和有机酸的蚀刻液来形成粗化面58α、60α(参照图6的(A))。
(12)接着,通过反复进行上述(3)~(11)的工序,形成更上层的层间树脂绝缘层150和导体电路158(包括通路孔160)(参照图6的(B))。
(13)接着,在容器中放入低聚物(分子量4000)46.67重量部、溶解在甲乙酮中而得到的80重量%的双酚A型环氧树脂(壳牌石油公司,商品名称:EPON 1001)15重量部、咪唑固化剂(四国化成公司制,商品名称:2E4MZ-CN)1.6重量部、作为感光性单体的多官能丙烯酸单体(共荣化学公司制,商品名称:R604)3重量部、相同的多元丙烯酸单体(共荣化学公司制,商品名称:DPE6A)1.5重量部、分散系消泡剂(SAN NOPCO公司(サンノプコ社)制,商品名称:S-65)0.71重量部,搅拌、混合来调整混合组成物,对该混合组成物添加作为光重量引发剂的二苯甲酮(关东化学公司制)2.0重量部、作为光敏剂的米氏酮(关东化学公司制)0.2重量部,由此得到在25℃下将粘度调整为2.0Pa·s的阻焊剂组成物(有机树脂绝缘材料),其中,上述低聚物为将溶解在二乙二醇二甲醚(DMDG)中而成为60重量%浓度的甲酚酚醛清漆型环氧树脂(日本化药公司制)的环氧基50%丙烯酸化而得到的。
此外,利用B型粘度计(东京计器公司制的DVL-B型)进行粘度测量,在60rpm的情况下利用转子No.4,在6rpm的情况下利用转子No.3。
(14)接着,在基板30上以20μm的厚度涂敷上述阻焊剂组成物,以在70℃下20分钟、在70℃下30分钟的条件进行干燥处理之后,将描绘了阻焊剂开口部的图案的厚度5mm的光掩模密合在阻焊层70上并以1000mJ/cm2的紫外线进行曝光,利用DMTG溶液进行显影处理,从而形成直径200μm的开口71(参照图6的(C))。
(15)接着,将形成有阻焊层(有机树脂绝缘层)70的基板浸渍在pH=4.5的无电解镀镍液中20分钟,以此在开口部71上形成厚度为5μm的镀镍层72,其中,上述pH=4.5的无电解镀镍液包含氯化镍(2.3×10-1mol/l)、次磷酸钠(2.8×10-1mol/l)、柠檬酸钠(1.6×10-1mol/l)。进一步在80℃的条件下,将该基板浸渍在无电解镀液中7.5分钟,在镀镍层72上形成厚度0.03μm的镀金层74,由此在导体电路158上形成焊盘75,其中,上述无电解镀液包含氰化金钾(7.6×10-3mol/l)、氯化铵(1.9×10-1mol/l)、柠檬酸钠(1.2×10-1mol/l)、次磷酸钠(1.7×10-1mol/l)(参照图6的(D))。
(16)之后,在阻焊层70的开口部71上印刷焊锡膏,在200℃下进行回流焊,由此形成焊锡凸块76。由此能够得到内置有IC芯片20的、具有焊锡凸块76的多层印刷线路板10(参照图7)。
在上述实施方式中,在层间树脂绝缘层50、150中使用了热固化型环烯烃系树脂板。能够在层间树脂绝缘层50中使用环氧系树脂薄膜来代替热固化型环烯烃系树脂板。在该环氧系树脂薄膜中含有难容性树脂、可溶性粒子、固化剂、其他成分。
在使用于本发明的树脂薄膜中,希望上述可溶性粒子大致均匀地分布在上述难溶性树脂中。这是因为能够形成具有均匀粗化程度的凹凸的粗化面,即使在树脂薄膜上形成通路孔、通孔,也能够确保在其上形成的导体电路的金属层密合性。另外,也可以使用仅在形成粗化面的表层部含有可溶性粒子的树脂薄膜。由于这样,除了树脂薄膜的表层部以外不会接触酸或氧化剂,因此可靠地确保使层间树脂绝缘层介于中间的导体电路之间的绝缘性。
[第一实施方式的改变例]
参照图8说明第一实施方式的改变例所涉及的印刷线路板的制造方法。在第一实施方式中,在基板的贯通孔32的底部侧设置了树脂制胶带。在第一实施方式的改变例中设置铜箔来代替树脂制胶带。
形成贯通孔32,在底部侧配置与背面侧导体电路28相同厚度的铜箔27(图8的(A)、图8的(B)、图8的(C))。然后,在铜箔27上涂敷粘接剂29,收容IC芯片20(图8的(D)、图8的(E))。以后的工序与第一实施方式相同,因此省略说明。在第一实施方式的改变例中,通过使用与背面侧导体电路28相同厚度的铜箔27,能够比第一实施方式进一步提高IC芯片20对基板30的定位精确度。
[第二实施方式]
接着,参照图11说明本发明的第二实施方式所涉及的多层印刷线路板。
在上述的第一实施方式中,在多层印刷线路板内收容了IC芯片。与此相对,在第二实施方式中,在多层印刷线路板10内收容芯片电容器20,在表面安装IC芯片140。多层印刷线路板10被安装在子板90上。
IC芯片140的电源焊盘144P与芯片电容器120的端子124通过芯基板30上面侧的通路孔60-导体电路58-通路孔160-导体电路158-焊锡凸块76U相连接。芯片电容器120的端子124与子板90的电源焊盘94P通过芯基板30下面侧的通路孔60-导体电路58-通路孔160-导体电路158-焊锡凸块76D相连接。
另一方面,IC芯片140的信号用焊盘144S与子板90的信号用焊盘94S通过焊锡凸块76U-导体电路158-通路孔160-导体电路58-通路孔60-芯基板30的通孔136-通路孔60-导体电路58-通路孔160-导体电路158-焊锡凸块76D相连接。
在该第二实施方式中,以芯基板的定位标记31为基准来形成构成芯基板30的通孔136的贯通孔135。
在第二实施方式中,在IC芯片140的正下方配置芯片电容器120,因此IC芯片与芯片电容器之间的配线长度缩短,另外,在芯片电容器120的下面连接配线,因此芯片电容器120与子板90之间的配线长度缩短。由此,减少配线的压降,从而能够防止由压降引起的IC芯片140的误动作。
接着,参照图9和图10说明第二实施方式的多层印刷线路板10的制造方法。
(1)首先,将由两面覆铜层叠板构成的绝缘树脂基板(芯基板)30设为初始材料,其中,上述两面覆铜层叠板是层叠了将玻璃布等芯材浸渍环氧等树脂而得到的预浸料、在两面层压了铜箔26而得到的(参照图9的(A))。在两面的铜箔26上形成规定图案的抗蚀涂层,去除没有形成抗蚀涂层部分的铜箔,剥离抗蚀涂层,由此形成定位标记31和导体电路28(参照图9的(B))。接着,在芯基板30上形成芯片电容器收容用贯通孔32、通孔用贯通孔135,在背面侧粘贴树脂制胶带25(参照图9的(C))。
(2)之后,以芯基板30的定位标记31为基准,将芯片电容器120位置对准在贯通孔32内,以此载置在胶带25上(参照图9的(D))。然后,在贯通孔135中设置镀膜133来形成通孔136(参照图9的(E))。
(3)在经过了上述工序的基板50上面如下地设置由环烯烃系树脂构成的层间树脂绝缘层50:在将厚度50μm的热固化型环烯烃系树脂板升温到温度50~150℃的同时以压力5kg/cm2进行真空压接层压(参照图10的(A))。
(4)剥离背面侧的树脂制胶带25,在基板50的背面真空压接层压热固化型环烯烃系树脂板,从而设置层间树脂绝缘层50(参照图10的(B))。
(4)接着,利用照相机80透过层间树脂绝缘层50来拍摄定位标记31,由此进行位置对准,利用CO2气体激光在上面侧层间树脂绝缘层50以及下面侧层间树脂绝缘层50上设置直径80μm的通路孔用开口48(参照图10的(C))。
之后,与第一实施方式相同,在层间树脂绝缘层50上形成导体电路58,在通路孔用开口48上形成通路孔60(参照图10的(D))。与第一实施方式相同,还形成上层的层间树脂绝缘层150、导体电路158、通路孔160、阻焊层70以及焊盘76U、76D(参照图11)。
根据本申请发明的制造方法,即使在内置有作为电子部件的IC芯片、芯片电容器的基板上也能够可靠地连接IC芯片、芯片电容器与层间树脂绝缘层的通路孔,因此提高电连接性。
[第三实施方式]
接着,参照图15说明本发明的第三实施方式所涉及的多层印刷线路板。
第三实施方式的多层印刷线路板在收容于绝缘树脂基板(芯基板)30内的IC芯片20上形成有树脂层80和由通路孔82、导体电路84构成的再配线层。在构成该再配线层的导体电路84上形成有绝缘树脂层250和柱状电极260。并且,在柱状电极260的上层设置有树脂绝缘层150,该树脂绝缘层150形成有通路孔160和导体电路158。在树脂绝缘层150上的阻焊层70的开口71上设置有焊锡凸块76。
参照图12~图14说明第三实施方式的多层印刷线路板的制造方法。
(1)准备形成有树脂层80和由通路孔82、导体电路84构成的再配线层的IC芯片20(图12的(A))。在IC芯片20的上表面形成绝缘树脂层250。然后,以IC芯片20的定位标记23a为基准,利用激光在绝缘树脂层250上形成筒状的开口262(图12的(B))。
(2)在绝缘树脂层250表面和开口262内形成无电解铜镀膜252(图12的(C))。
(3)形成抗镀层254,在没有形成抗镀层254的部分和开口262内形成电解镀铜256(图13的(A))。
(4)剥离抗镀层并且去除抗镀层下的无电解铜镀膜252,在开口262内形成由无电解铜镀膜252和电解镀铜256构成的柱状电极260。然后,在柱状电极260从绝缘树脂层250露出部分上形成粗化层260α(图13的(B))。
(5)在芯基板30的贯通孔32的底部粘贴树脂制胶带25。接着,以芯基板30的定位标记31为基准,使用IC芯片20上的定位标记23对IC芯片20进行位置对准,按压IC芯片20上表面使其完全收容到贯通孔32内(图13的(C))。
(6)在绝缘树脂层250上设置由环烯烃系树脂构成的树脂绝缘层50之后,剥离背面的胶带25。在芯基板的背面侧设置树脂层50。然后,利用CO2气体激光在树脂绝缘层150上设置通路孔用开口150a。之后,通过浸渍在氧化剂等中来设置树脂绝缘层150的粗化面150α(图13的(C))。
(7)在层间树脂绝缘层150上设置无电解铜镀膜152(参照图14的(A))。
(8)在结束了上述处理的基板30上设置抗镀层54。然后,实施电解镀,形成电解镀膜156(图14的(B))。
(10)在剥离去除抗镀层154之后,通过蚀刻溶解去除该抗镀层下的无电解铜镀膜152,形成由无电解铜镀膜152和电解镀膜156构成的导体电路158以及通路孔160,利用含有二价铜络合物和有机酸的蚀刻液来形成粗化面158α(参照图14的(C))。
(11)接着,形成具备开口71的阻焊层70,在开口71内的导体电路上形成镀镍层72、镀金层74。然后,在阻焊层70的开口部71印刷焊锡膏,通过回流焊来形成焊锡凸块76。由此能够得到内置了形成有再配线层的IC芯片20的、具有焊锡凸块76的多层印刷线路板(参照图15)。
[第四实施方式]
接着,参照图16说明本发明的第四实施方式所涉及的多层印刷线路板。
在上述的第三实施方式中,在IC芯片的再配线层的导体电路上形成柱状电极,在该柱状电极上设置了具备通路孔160和导体电路158的树脂绝缘层150。与此相对,在第四实施方式中,在IC芯片20的再配线层的导体电路84上设置有具备通路孔160和导体电路158的树脂绝缘层150。
Claims (5)
1.一种多层印刷线路板的制造方法,在具有第一面和与该第一面相反侧的第二面的基板上反复形成层间绝缘层和导体层,在该层间绝缘层上形成通路孔,通过该通路孔进行电连接,该多层印刷线路板的制造方法的特征在于,具备以下工序:
在上述基板上的第一面上形成导体电路和第一定位标记的工序;
在上述基板上形成贯通孔的工序;
配置被设置于上述基板上的第二面而堵塞上述贯通孔的密封构件的工序;
根据上述基板的第一定位标记将电子部件收容在上述贯通孔内的工序;
在上述基板的第一面上形成层间绝缘层的工序;以及
根据上述基板的第一定位标记在上述层间绝缘层上形成到达上述电子部件的端子的通路孔用开口的工序。
2.一种多层印刷线路板的制造方法,其特征在于,还具备以下工序:
在上述基板上的第二面上形成导体电路和第二定位标记的工序;
从基板剥离上述密封构件的工序;
在上述基板的第二面上形成层间绝缘层的工序;以及
根据上述基板的第二定位标记在上述层间绝缘层上形成到达上述电子部件的端子的通路孔用开口的工序。
3.根据权利要求1或2所述的多层印刷线路板的制造方法,其特征在于,
使用金属箔作为上述密封构件。
4.根据权利要求1~3中的任一项所述的多层印刷线路板的制造方法,其特征在于,
在上述基板上的第一面上形成层间绝缘层的工序中,利用从该层间绝缘层渗出的树脂来填充上述贯通孔的壁面与上述电子部件之间。
5.根据权利要求1~4中的任一项所述的多层印刷线路板的制造方法,其特征在于,
在将上述电子部件收容在上述贯通孔内的工序中,以在上述贯通孔的壁面与上述电子部件之间形成的间隙为30~200μm的方式在上述贯通孔内收容上述电子部件。
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Cited By (9)
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---|---|---|---|---|
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Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8314343B2 (en) * | 2007-09-05 | 2012-11-20 | Taiyo Yuden Co., Ltd. | Multi-layer board incorporating electronic component and method for producing the same |
US7935893B2 (en) * | 2008-02-14 | 2011-05-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board with built-in electronic component |
JP2009239247A (ja) * | 2008-03-27 | 2009-10-15 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
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JP2012256675A (ja) * | 2011-06-08 | 2012-12-27 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及びその製造方法 |
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EP2615638A3 (en) * | 2012-01-16 | 2013-09-25 | Yu, Wan-Ling | Semiconductor Package Structure and Method for Manufacturing The Same |
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JP2014154594A (ja) * | 2013-02-05 | 2014-08-25 | Ibiden Co Ltd | 電子部品内蔵配線板 |
US8803310B1 (en) * | 2013-02-08 | 2014-08-12 | Unimicron Technology Corp. | Embedded electronic device package structure |
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JP2016086004A (ja) * | 2014-10-23 | 2016-05-19 | イビデン株式会社 | プリント配線板 |
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US9929100B2 (en) | 2015-04-17 | 2018-03-27 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and method of manufacturing the same |
US10109588B2 (en) * | 2015-05-15 | 2018-10-23 | Samsung Electro-Mechanics Co., Ltd. | Electronic component package and package-on-package structure including the same |
US10090241B2 (en) | 2015-05-29 | 2018-10-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device, package structure and method of forming the same |
KR102015335B1 (ko) | 2016-03-15 | 2019-08-28 | 삼성전자주식회사 | 전자부품 패키지 및 그 제조방법 |
US10276467B2 (en) | 2016-03-25 | 2019-04-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
US10204889B2 (en) | 2016-11-28 | 2019-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
JP6822192B2 (ja) * | 2017-02-13 | 2021-01-27 | Tdk株式会社 | 電子部品内蔵基板 |
JP6384647B1 (ja) * | 2017-02-23 | 2018-09-05 | 株式会社村田製作所 | 電子部品、電子機器および電子部品の実装方法 |
US10636757B2 (en) * | 2017-08-29 | 2020-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit component package and method of fabricating the same |
WO2019073801A1 (ja) * | 2017-10-11 | 2019-04-18 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置およびその製造方法 |
KR101892876B1 (ko) * | 2017-12-01 | 2018-08-28 | 삼성전기주식회사 | 팬-아웃 반도체 패키지 |
KR102004243B1 (ko) * | 2017-12-14 | 2019-07-26 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
JP7046639B2 (ja) * | 2018-02-21 | 2022-04-04 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US11114407B2 (en) * | 2018-06-15 | 2021-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out package and manufacturing method thereof |
US11600590B2 (en) * | 2019-03-22 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
EP3833164A1 (en) * | 2019-12-05 | 2021-06-09 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Compensating misalignment of component carrier feature by modifying target design concerning correlated component carrier feature |
CN111430313A (zh) * | 2020-05-11 | 2020-07-17 | 上海天马微电子有限公司 | 半导体封装及其制作方法 |
US11424191B2 (en) * | 2020-06-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices and methods of manufacture |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11195745A (ja) * | 1998-01-06 | 1999-07-21 | Mitsubishi Gas Chem Co Inc | マルチチッププラスチックパッケージ |
JP4854846B2 (ja) | 2000-02-25 | 2012-01-18 | イビデン株式会社 | 多層プリント配線板の製造方法 |
JP4270769B2 (ja) | 2000-12-15 | 2009-06-03 | イビデン株式会社 | 多層プリント配線板の製造方法 |
JP4141115B2 (ja) * | 2001-06-26 | 2008-08-27 | イビデン株式会社 | 多層プリント配線板の製造方法 |
JP3671886B2 (ja) | 2001-09-13 | 2005-07-13 | セイコーエプソン株式会社 | 基板、電気光学装置、電子機器、部品の実装方法及び電気光学装置の製造方法 |
JP4497548B2 (ja) * | 2006-03-28 | 2010-07-07 | 日本特殊陶業株式会社 | 配線基板 |
FI119714B (fi) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Piirilevyrakenne ja menetelmä piirilevyrakenteen valmistamiseksi |
JP5160052B2 (ja) * | 2006-06-16 | 2013-03-13 | 日本特殊陶業株式会社 | 配線基板、キャパシタ |
JP2007189202A (ja) * | 2005-12-12 | 2007-07-26 | Shinko Electric Ind Co Ltd | 回路基板の製造方法 |
JPWO2009147936A1 (ja) * | 2008-06-02 | 2011-10-27 | イビデン株式会社 | 多層プリント配線板の製造方法 |
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2008
- 2008-11-20 WO PCT/JP2008/071116 patent/WO2009118950A1/ja active Application Filing
- 2008-11-20 JP JP2009515371A patent/JPWO2009118950A1/ja active Pending
- 2008-11-20 EP EP08873661A patent/EP2259668A4/en not_active Withdrawn
- 2008-11-20 CN CN2008800013095A patent/CN101683004B/zh active Active
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2009
- 2009-03-24 US US12/409,826 patent/US8237060B2/en active Active
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US9516746B2 (en) | 2011-11-22 | 2016-12-06 | Panasonic Intellectual Property Management Co., Ltd. | Metal-clad laminate and printed wiring board |
CN104125706A (zh) * | 2013-04-23 | 2014-10-29 | 揖斐电株式会社 | 电子部件及其制造方法和多层印刷布线板的制造方法 |
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CN107785333A (zh) * | 2016-08-31 | 2018-03-09 | 三星电机株式会社 | 扇出型半导体封装件 |
CN107785333B (zh) * | 2016-08-31 | 2020-08-04 | 三星电子株式会社 | 扇出型半导体封装件 |
CN108962843A (zh) * | 2017-05-19 | 2018-12-07 | Tdk株式会社 | 半导体ic内置基板及其制造方法 |
CN109509726A (zh) * | 2017-09-15 | 2019-03-22 | 三星电机株式会社 | 扇出型半导体封装件 |
CN109509726B (zh) * | 2017-09-15 | 2022-04-05 | 三星电子株式会社 | 扇出型半导体封装件 |
Also Published As
Publication number | Publication date |
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WO2009118950A1 (ja) | 2009-10-01 |
EP2259668A4 (en) | 2011-12-14 |
US20090244865A1 (en) | 2009-10-01 |
CN101683004B (zh) | 2012-10-17 |
US8237060B2 (en) | 2012-08-07 |
EP2259668A1 (en) | 2010-12-08 |
JPWO2009118950A1 (ja) | 2011-07-21 |
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