KR20030007438A - 다층프린트배선판 및 다층프린트배선판의 제조방법 - Google Patents
다층프린트배선판 및 다층프린트배선판의 제조방법 Download PDFInfo
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- KR20030007438A KR20030007438A KR1020027011073A KR20027011073A KR20030007438A KR 20030007438 A KR20030007438 A KR 20030007438A KR 1020027011073 A KR1020027011073 A KR 1020027011073A KR 20027011073 A KR20027011073 A KR 20027011073A KR 20030007438 A KR20030007438 A KR 20030007438A
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- South Korea
- Prior art keywords
- layer
- substrate
- multilayer printed
- insulating layer
- circuit board
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- 150000003003 phosphines Chemical class 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 229920002312 polyamide-imide Polymers 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 150000003112 potassium compounds Chemical class 0.000 description 1
- NNFCIKHAZHQZJG-UHFFFAOYSA-N potassium cyanide Chemical compound [K+].N#[C-] NNFCIKHAZHQZJG-UHFFFAOYSA-N 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000012779 reinforcing material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000012798 spherical particle Substances 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
- 239000010457 zeolite Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
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- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (20)
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되며, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,상기 기판에는, 전자부품이 내장되고 있는 것을 특징으로 하는 다층프린트배선판.
- 제 1 항에 있어서, 표면에 전자부품이 실장되어 있는 것을 특징으로 하는 다층프린트배선판
- 제 1 항 또는 2 항에 있어서, 상기 기판에는, 외부기판과 접속하는 단자가 배설되어 있는 것을 특징으로 하는 다층프린트배선판.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되고, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,상기 기판에는, 전자부품이 내장되고,상기 전자부품의 패드부분에는, 최하층의 층간절연층의 바이어홀과 접속하기 위한 트랜지션층이 형성되어 있는 것을 특징으로 하는 다층프린트배선판.
- 제 1 항 내지 4 항 기재의 어느 한 항에 있어서, 상기 기판은, 패키지기판인 것을 특징으로 하는 다층프린트배선판.
- 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,상기 전자부품의 패드부분에는, 최하층의 층간수지절연층의 바이어홀과 접속하기 위한 트랜지션층이 적어도 2층으로 형성되고 있는 것을 특징으로 하는 다층프린트배선판.
- 제 6 항에 있어서, 상기 트랜지션층의 폭은, 패드의 폭의 1.0 ~ 30 배인 것을 특징으로 하는 다층프린트배선판.
- 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,상기 전자부품의 패드부분에는, 최하층의 층간수지절연층의 바이어홀과 접속하기 위한 트랜지션층이 적어도 제 1 박막층, 제 2 박막층, 후부층으로 형성되어 있는 것을 특징으로 하는 다층프린트배선판.
- 제 8 항에 있어서, 상기 제 1 박막층은, 주석, 크롬, 티탄, 니켈, 아연, 코발트, 금, 동 가운데서 선택되어지는 1 종류 이상인 것을 특징으로 하는 다층프린트배선판.
- 제 8 항에 있어서, 상기 제 2 박막층은, 니켈, 동, 금, 은 가운데서 선택되어지는 1 종류 이상인 것을 특징으로 하는다층프린트배선판.
- 전자부품이 내장된 기판 상에 층간수지절연층과 도체층이 반복하여 형성된 다층프린트배선판에 있어서,(a) 상기 전자부품이 매입된 기판의 전체면에 제 1 박막층, 제 2 박막층을 형성하는 공정,(b) 상기 박막층 상에 레지스트를 실시하고, 레지스트의 비형성부에 후부층을 형성하는 공정.(c) 에칭에 의해 박막층을 제거하는 공정.을 적어도 경유하여 전자부품 상에 트랜지션층을 형성시키는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 제 11 항에 있어서, 상기 제 1 박막층은, 스패터, 증착의 어느 하나로 행하여지는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 제 11 항에 있어서, 상기 제 2 박막층은, 스패터, 증착, 무전해도금의 어느하나로 행하여지는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되며, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,(a) 상기 기판에 전자부품을 수용하는 공정 ;(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(c) 상기 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행하는 공정을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,(a) 상기 기판에 전자부품을 수용하는 공정 ;(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정 ;(d) 상기 기판의 위치결정마크에 기초하여 가공 혹은 형성을 행하는 공정을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법 :.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,(a) 상기 기판에 전자부품을 수용하는 공정 ;(b) 상기 전자부품의 위치결정마크에 기초하여, 상기 기판에 위치결정마크를 레이저로 형성하는 공정 ;(c) 상기 기판의 위치결정마크에 금속막을 형성하는 공정;(d) 상기 기판에 층간절연층을 형성하는 공정 ;(e) 상기 기판의 위치결정마크에 기초하여 상기 층간절연층에 바이어홀용 개구를 가공 혹은 형성을 행하는 공정;을 적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀을 형성하고, 상기 바이어홀을 개재하여 전기적 접속시키는 다층프린트배선판의 제조방법에 있어서,(a) 상기 기판에 전자부품을 수용하는 공정 ;(b) 상기 전자부품의 다이패드의 표면의 피막을 제거하는 공정 ;(c) 상기 다이패드 상의, 최하층의 층간절연층의 바이어홀과 접속시키기 위한 트랜지션층을 형성하는 공정.(d) 상기 기판 상에, 층간절연층을 형성하는 공정 ;(e) 상기 층간절연층에, 도체회로 및 트랜지션층에 접속하는 바이어홀을 형성하는 공정;적어도 구비하는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 제 17 항에 있어서, 상기 산화피막제거를 역스패터, 플래즈마처리의 어느 하나로 행하는 것을 특징으로 하는 다층프린트배선판의 제조방법.
- 제 18 항에 있어서, 상기 피막제거와, 트랜지션층의 최하층의 형성을, 비산소분위기 중에서 행하는 것을 특징으로 하는다층프린트배선판의 제조방법.
- 기판 상에 층간절연층과 도체층이 반복하여 형성되고, 상기 층간절연층에는, 바이어홀이 형성되고, 상기 바이어홀을 개재하여 전기적 접속되는 다층프린트배선판에 있어서,상기 기판에는, 전자부품이 내장되고,상기 전자부품의 패드부분에는, 최하층의 층간절연층의 바이어홀과 접속하기 위한 트랜지션층이 형성되고,상기 다이패드의 표면의 피복이 제거되어 있는 것을 특징으로 하는 다층프린트배선판.
Applications Claiming Priority (11)
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JP2000049121 | 2000-02-25 | ||
JPJP-P-2000-00049121 | 2000-02-25 | ||
JPJP-P-2000-00073558 | 2000-03-16 | ||
JP2000073558 | 2000-03-16 | ||
JPJP-P-2000-00078206 | 2000-03-21 | ||
JP2000078206 | 2000-03-21 | ||
JP2000105212 | 2000-04-06 | ||
JPJP-P-2000-00105212 | 2000-04-06 | ||
JP2000152973 | 2000-05-24 | ||
JPJP-P-2000-00152973 | 2000-05-24 | ||
PCT/JP2001/000177 WO2001063991A1 (fr) | 2000-02-25 | 2001-01-12 | Carte a circuits imprimes multicouche et procede de production d'une carte a circuits imprimes multicouche |
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KR1020027011073A KR100890534B1 (ko) | 2000-02-25 | 2001-01-12 | 다층프린트배선판 및 다층프린트배선판의 제조방법 |
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US (11) | US6909054B2 (ko) |
EP (6) | EP1814154A1 (ko) |
KR (2) | KR20080031522A (ko) |
CN (1) | CN100336426C (ko) |
DE (1) | DE60128656T2 (ko) |
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- 2001-01-12 EP EP07108462A patent/EP1818975A3/en not_active Withdrawn
- 2001-01-12 US US10/181,682 patent/US6909054B2/en not_active Expired - Lifetime
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100697998B1 (ko) * | 2004-05-12 | 2007-03-23 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 및 그 제조 방법, 전기 광학 장치 및 그 제조 방법, 그리고 전자기기 |
US7449411B2 (en) | 2004-05-12 | 2008-11-11 | Seiko Epson Corporation | Semiconductor device and manufacturing method thereof, electro-optical device and manufacturing method thereof, and electronic apparatus |
KR101109287B1 (ko) * | 2008-08-18 | 2012-01-31 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
US9992555B2 (en) | 2010-06-29 | 2018-06-05 | Qualcomm Incorporated | Signaling random access points for streaming video data |
KR101443959B1 (ko) * | 2012-01-05 | 2014-09-29 | 완-링 유 | 반도체 패키지 구조 및 그 제작방법 |
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