CN107785333B - 扇出型半导体封装件 - Google Patents
扇出型半导体封装件 Download PDFInfo
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- CN107785333B CN107785333B CN201710059796.1A CN201710059796A CN107785333B CN 107785333 B CN107785333 B CN 107785333B CN 201710059796 A CN201710059796 A CN 201710059796A CN 107785333 B CN107785333 B CN 107785333B
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- layer
- connection member
- redistribution layer
- fan
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Abstract
本发明提供一种扇出型半导体封装件,所述扇出型半导体封装件包括:第一连接构件,具有通孔;半导体芯片,设置在通孔中,并具有有效表面和无效表面,所述有效表面上设置有连接焊盘,所述无效表面与有效表面背对;包封件,包封第一连接构件和半导体芯片的无效表面的至少一部分;第二连接构件,设置在第一连接构件和半导体芯片的有效表面上;树脂层,设置在包封件上;背重新分布层,嵌在包封件中,使得背重新分布层的一个表面通过包封件暴露,其中,树脂层覆盖背重新分布层的所述暴露的一个表面的至少一部分,且背重新分布层通过形成在贯穿树脂层和包封件的第一开口中的连接构件电连接到第一连接构件的重新分布层。
Description
本申请要求于2016年8月31日在韩国知识产权局提交的第10-2016-0111749号韩国专利申请的优先权的权益,所述韩国专利申请的全部公开内容通过引用包含于此。
技术领域
本公开涉及一种半导体封装件,更具体地,涉及一种连接端子可从设置有半导体芯片的区域向外延伸的扇出型半导体封装件。
背景技术
近来,与半导体芯片相关的技术发展的显著的近期趋势是减小半导体芯片的尺寸。因此,在半导体封装技术的领域中,随着对小尺寸的半导体芯片等的需求的快速增加,已经需要实现在具有紧凑尺寸的同时包括多个引脚(pin)的半导体封装件。
为满足如上所述的技术需求而提出的一种类型的封装技术为扇出型半导体封装。这样的扇出型半导体封装件具有紧凑的尺寸,并可通过使连接端子重新分布到设置有半导体芯片的区域的外部而实现多个引脚。
发明内容
本公开的一方面可提供一种解决了半导体芯片的产量降低的问题的扇出型半导体封装件。
根据本公开的一方面,可提供一种可在设置半导体芯片之前引入背重新分布层的扇出型半导体封装件。
根据本公开的一方面,一种扇出型半导体封装件可包括:第一连接构件,具有通孔;半导体芯片,设置在第一连接构件的通孔中,并具有有效表面和无效表面,所述有效表面上设置有连接焊盘,所述无效表面与有效表面背对设置;包封件,包封第一连接构件和半导体芯片的无效表面的至少一部分;第二连接构件,设置在第一连接构件和半导体芯片的有效表面上;树脂层,设置在包封件上;背重新分布层,嵌在包封件中,使得背重新分布层的一个表面暴露,其中,第一连接构件和第二连接构件分别包括电连接到半导体芯片的连接焊盘的重新分布层,树脂层覆盖背重新分布层的所述暴露的一个表面的至少一部分,且背重新分布层通过形成在贯穿树脂层和包封件的第一开口中的连接构件电连接到第一连接构件的重新分布层。
根据本公开的另一方面,一种扇出型半导体封装件可包括:第一连接构件,具有通孔;半导体芯片,设置在第一连接构件的通孔中,并具有有效表面和无效表面,所述有效表面上设置有连接焊盘,所述无效表面与有效表面背对;第二连接构件,设置在第一连接构件和半导体芯片的有效表面上;树脂层,背重新分布层从树脂层朝向第二连接构件突出;包封件,将树脂层连接到第一连接构件和半导体芯片,其中,背重新分布层以及第一连接构件和第二连接构件的重新分布层电连接到半导体芯片的连接焊盘。
附图说明
通过下面结合附图进行的详细描述,将更加清楚地理解本公开的以上和其它方面、特征和优点,在附图中:
图1是示出电子装置系统的示例的示意性框图;
图2是示出电子装置的示例的示意性透视图;
图3A和图3B是示出扇入型半导体封装件在被封装之前和之后的状态的示意性截面图;
图4是示出扇入型半导体封装件的封装工艺的示意性截面图;
图5是示出扇入型半导体封装件安装在插入基板上并最终安装在电子装置的主板上的情况的示意性截面图;
图6是示出扇入型半导体封装件嵌在插入基板中并最终安装在电子装置的主板上的情况的示意性截面图;
图7是示出扇出型半导体封装件的示意性截面图;
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图;
图9是示出扇出型半导体封装件的示例的示意性截面图;
图10是沿着图9的扇出型半导体封装件的I-I’线截取的示意性平面图;
图11A至图11D是示出形成在图9的扇出型半导体封装件的第一连接构件中的各种形式的过孔的示意性截面图;
图12A至图12D是示出制造图9的扇出型半导体封装件的工艺的示例的示图;
图13是示出扇出型半导体封装件的另一示例的示意性截面图;
图14是示出扇出型半导体封装件的另一示例的示意性截面图;
图15是示出扇出型半导体封装件的另一示例的示意性截面图。
具体实施方式
在下文中,将参照附图描述本公开中的示例性实施例。在附图中,为了清楚起见,可夸大或缩小附图中的组件的形状和尺寸等。
在说明书中,组件与另一组件的“连接”的意义包括通过粘结层的非直接连接以及两个组件之间的直接连接。此外,“电连接”是指包括物理地连接和物理地断开的概念。可以理解的是,当元件被称为“第一”和“第二”时,所述元件不受其限制。它们仅可用于区分一个元件和其它元件的目的,并不会限制元件的顺序或重要性。在某些情况下,在不脱离在此阐述的权利要求的范围的情况下,第一元件可被称为第二元件。同样地,第二元件也可被称为第一元件。
在此使用的术语“示例性实施例”不指相同的示例性实施例,而是用来强调与另一示例性实施例的特定特征或特性不同的特定特征或特性。然而,在此提供的示例性实施例被视为能够通过将一个示例性实施例与另一个示例性实施例进行整体组合或部分组合来实现。例如,除非在其中提供相反或矛盾的描述,否则特定示例性实施例中描述的一个元件即使在未在另一示例性实施例中进行描述,也可理解为与另一示例性实施例相关的描述。
在此使用的术语仅为了描述示例性实施例,而不限制本公开。在这种情况下,除非在上下文中另外的解释,否则单数形式包括复数形式。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1,电子装置1000中可容纳有主板1010。主板1010可包括物理连接到其或电连接到其的芯片相关组件1020、网络相关组件1030和其它组件1040等。这些组件可连接到下面将要描述的其它组件,以形成各种信号线1090。
芯片相关组件1020可包括存储芯片、应用处理芯片或逻辑芯片等,其中,存储芯片可为诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))或闪存等,应用处理器芯片可为诸如中央处理器(例如,中央处理单元(CPU))、图形处理器(例如,图形处理单元(GPU))、数字信号处理器、加密处理器、微处理器或微控制器等,逻辑芯片可为诸如模拟数字转换器(ADC)或专用集成电路(ASIC)等。然而,芯片相关组件1020不限于此,而是还可包括其它类型的芯片相关组件。此外,芯片相关组件1020可彼此组合。
网络相关组件1030可包括诸如无线保真(Wi-Fi)(电工电子工程协会(IEEE)802.11家族等)、全球微波接入互操作性(WiMAX)(IEEE 802.16家族等)、IEEE 802.20、长期演进(LTE)、仅演进数据(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G、4G和5G协议的协议以及在上述协议之后指定的任何其它无线和有线协议。然而,网络相关组件1030不限于此,而是还可包括各种其它无线或有线标准或协议。此外,网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其它组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器或多层陶瓷电容器(MLCC)等。然而,其它组件1040不限于此,而是还可包括用于各种其它目的的无源组件等。此外,其它组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型,电子装置1000可包括可以物理连接或电连接到主板1010或可以不物理连接或电连接到主板1010的其它组件。其它组件可包括例如相机模块1050、天线1060、显示装置1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、罗盘(未示出)、加速计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)或数字通用光盘(DVD)驱动器(未示出)等。然而,其它组件不限于此,而是还可根据电子装置1000的类型而包括用于各种目的的另外的组件等。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字视频摄影机,数字静照相机、网络系统、计算机、监视器、平板PC、膝上型PC、上网本PC、电视机、视频游戏机、智能手表或机动车组件等。然而,电子装置1000不限于此,并且可以是能够处理数据的任何其它电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2,可在如上所述的各种电子装置1000中使用用于各种目的的半导体封装件。例如,主板1110可被容纳在智能电话1100的主体1101中,各种电子组件1120可物理连接或电连接到主板1110。此外,可以物理连接或电连接到主板1110或可以不物理连接或电连接到主板1110的其它组件(诸如相机模块1130)可被容纳在主体1101中。电子组件1120的一些可以是芯片相关组件,半导体封装件100可以是例如芯片相关组件中的应用处理器,但不限于此。电子装置并不一定限制于智能手机1100,并且可以是如上所述的其它电子装置。
半导体封装件
通常,可在半导体芯片中集成多个精细电路。然而,半导体芯片本身不能用作成品半导体产品,并且会由于外部的物理冲击或化学冲击而损坏。因此,不使用半导体芯片本身,而是将其封装并以封装状态用于电子装置等中。
这里,在电连接方面,由于在半导体芯片和电子装置的主板之间存在电路宽度的差异,因此需要进行半导体封装。具体地,虽然半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间隔非常精细,但是在电子装置中使用的主板的组件安装焊盘的尺寸和主板的组件安装焊盘之间的间隔显著地大于半导体芯片的连接焊盘的尺寸和半导体芯片的连接焊盘之间的间隔。因此,会难以将半导体芯片直接安装在主板上,并且需要用于缓冲半导体芯片和主板之间的电路宽度差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的被分为扇入型半导体封装件或扇出型半导体封装件。
在下文中,将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和之后的状态的示意性截面图。
图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照附图,半导体芯片2220可以是例如处于裸露状态下的集成电路(IC),包括:主体2221,包含硅(Si)、锗(Ge)或砷化镓(GaAs)等;连接焊盘2222,形成在主体2221的一个表面上,并包括诸如铝(Al)等的导电材料;诸如氧化膜或氮化物膜等的钝化层2223,形成在主体2221的一个表面上,并包覆连接焊盘2222的至少一部分。在这种情况下,由于连接焊盘2222非常小,因此可能难以将集成电路(IC)安装在中间级(intermediate level)印刷电路板(PCB)以及电子装置的主板等上。
因此,可根据半导体芯片2220的尺寸在半导体芯片2220上形成连接构件2240,以将连接焊盘2222重新分布。连接构件2240可通过如下步骤形成:在半导体芯片2220上使用诸如感光介质(PID)树脂的绝缘材料形成绝缘层2241,形成使连接焊盘2222暴露的导通孔(via holes)2243h,随后形成布线图案2242和过孔2243。然后,可形成保护连接构件2240的钝化层2250,可形成开口2251,并可形成凸块下金属层(underbump metal layer)2260等。也就是说,可通过一系列的工艺来制造包括例如半导体芯片2220、连接构件2240、钝化层2250以及凸块下金属层2260的扇入型半导体封装件2200。
如上所述,扇入型半导体封装件可具有使半导体芯片的例如输入/输出(I/O)端子的所有连接焊盘设置在半导体芯片的内部的封装形式,可具有优异的电特性并能够以低成本进行生产。因此,已经以扇入型半导体封装的形式来制造安装在智能手机里的许多元件。具体地,已经将安装在智能手机里的许多元件开发为在具有紧凑尺寸的同时实现快速的信号传输。
然而,由于在扇入型半导体封装件中需要将所有I/O端子设置在半导体芯片的内部,因此扇入型半导体封装件具有大的空间限制。因此,难以将这种结构应用于具有大量I/O端子的半导体芯片或具有紧凑尺寸的半导体芯片。此外,由于上述缺点,可能无法在电子装置的主板上直接安装并使用扇入型半导体封装件。就这点而言,即使在通过重新分布工艺来增加半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间隔的情况下,半导体芯片的I/O端子的尺寸和半导体芯片的I/O端子之间的间隔也不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在插入基板上并最终安装在电子装置的主板上的情况的示意性截面图。
图6是示出扇入型半导体封装件嵌在插入基板中并最终安装在电子装置的主板上的情况的示意性截面图。
参照附图,在扇入型半导体封装件2200中,可通过插入基板(interposersubstrate)2301将半导体芯片2220的连接焊盘2222(也就是I/O端子)再次重新分布,并可最终将处于安装在插入基板2301上的状态下的扇入型半导体封装件2200安装在电子装置的主板2500上。在这种情况下,可通过底部填充树脂2280等来固定焊球2270等,并且半导体芯片2220的外侧可包覆有成型材料(molding material)2290等。可选地,扇入型半导体封装件2200可嵌在单独的插入基板2302中,在扇入型半导体封装件2200嵌在插入基板2302中的状态下,插入基板2302可通过插入基板2302再次重新分布半导体芯片2220的连接焊盘2222(也就是I/O端子),从而使扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述,可能难以在电子装置的主板上直接安装并使用扇入型半导体封装件。因此,可将扇入型半导体封装件安装在单独的插入基板上,并随后通过封装工艺将其安装在电子装置的主板上,或者,可在电子装置的主板上安装并使用处于嵌在插入基板中的状态下的扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照附图,在扇出型半导体封装件2100中,例如,半导体芯片2120的外侧可由包封件2130保护,且连接焊盘2122可通过连接构件2140而被重新分布到半导体芯片2120的外部。在这种情况下,钝化层2150可形成在连接构件2140上,凸块下金属层2160可形成在钝化层2150的开口中。焊球2170可形成在凸块下金属层2160上。半导体芯片2120可以是包括主体2121、连接焊盘2122和钝化层(未示出)等的集成电路(IC)。连接构件2140可包括绝缘层2141、形成在绝缘层2141上的重新分布层2142以及将连接焊盘2122和重新分布层2142彼此电连接的过孔2143。
如上所述,扇出型半导体封装件可具有使半导体芯片的I/O端子通过形成在半导体芯片上的连接构件而被重新分布并被设置到半导体芯片的外部的形式。如上所述,在扇入型半导体封装件中,半导体芯片的所有的I/O端子需要设置在半导体芯片的内部。因此,当半导体芯片的尺寸减小时,需要减小球的尺寸和间距,使得在扇入型半导体封装件中不能使用标准化的球布局。在另一方面,扇出型半导体封装件具有使半导体芯片的I/O端子通过如上所述形成在半导体芯片上的连接构件被重新分布并被设置在半导体芯片的外部的形式。因此,即使半导体芯片的尺寸减小,仍可以在扇出型半导体封装件中使用标准化的球布局,使得扇出型半导体封装件可在不使用单独的插入基板的情况下安装在电子装置的主板上(如下所述)。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8,扇出型半导体封装件2100可通过焊球2170等安装在电子装置的主板2500上。也就是说,如上所述,扇出型半导体封装件2100包括形成在半导体芯片2120上并能够将连接焊盘2122重新分布到半导体芯片2120的尺寸范围之外的扇出区域的连接构件2140,使得标准化的球布局仍可按原样用于扇出型半导体封装件2100中。结果,扇出型半导体封装件2100可在不使用单独的插入基板等的情况下安装在电子装置的主板2500上。
如上所述,由于扇出型半导体封装件可在不使用单独的插入基板的情况下安装在电子装置的主板上,因此扇出型半导体封装件可实现为厚度小于使用插入基板的扇入型半导体封装件的厚度。因此,扇出型半导体封装件可小型化和薄型化。此外,扇出型半导体封装件具有优异的热性能和电性能,使得其特别适合移动产品。因此,扇出型半导体封装件可实现为比使用印刷电路板(PCB)的通常的封装堆叠(POP)类型更紧凑的形式,并可解决由于发生翘曲现象而导致的问题。
同时,扇出型半导体封装件指的是如上所述的用于在电子装置等的主板上安装半导体芯片并保护半导体芯片免受外部冲击的封装技术,是与具有与扇出型半导体封装件的比例、目的等不同的比例、目的等并具有嵌在其中的扇入型半导体封装件的诸如插入基板等的印刷电路板(PCB)的概念不同的概念。
在下文中,将参照附图描述可显著地减小半导体芯片的产率降低问题的扇出型半导体封装件。
图9是示出扇出型半导体封装件的示例的示意性截面图。
图10是沿着图9的扇出型半导体封装件的I-I’线截取的示意性平面图。
图11A至图11D是示出形成在图9的扇出型半导体封装件的第一连接构件中的各种形式的过孔的示意性截面图。
参照附图,根据本公开的示例性实施例的扇出型半导体封装件100A可包括:第一连接构件110,具有通孔(through-hole)110H;半导体芯片120,设置在第一连接构件110的通孔110H中,并具有使连接焊盘122设置在其上的有效表面(active surface)以及与有效表面背对设置的无效表面(inactive surface);包封件130,包封第一连接构件110和半导体芯片120的无效表面的至少一部分;第二连接构件140,设置在第一连接构件110和半导体芯片120的有效表面上;树脂层180,设置在包封件130上。第一连接构件110可包括电连接到半导体芯片120的连接焊盘122的重新分布层112a和112b,第二连接构件140可包括电连接到半导体芯片120的连接焊盘122的重新分布层142。接触树脂层180的背重新分布层182(rear redistribution layer)可嵌在包封件130中。背重新分布层182可通过形成在贯穿树脂层180和包封件130的第一开口181a中的连接构件191电连接到第一连接构件110的重新分布层112a和112b。
近来,为了增加存储器容量或改善半导体的操作性能,已经对其中在半导体封装件中形成垂直地传递信号的图案结构并在半导体封装件上垂直地堆叠同类封装件(homogeneous package)或异类封装件(heterogeneous package)的封装堆叠结构进行了各种开发。例如,可使用如下所述的封装堆叠结构:使其上安装有存储器芯片的插入基板堆叠在基于晶圆制造的半导体封装件上,并使用焊球等使其电连接到半导体封装件。
然而,在这种情况下,由于插入基板的厚度导致难以使封装堆叠结构变薄。因此,可考虑在半导体封装件的设置于其下部的包封件上形成背重新分布层,以省略插入基板。然而,在这种情况下,背重新分布层应当在设置半导体芯片后另外地形成。因此,在形成背重新分布层的工艺中会发生缺陷时,也应将半导体芯片丢弃,因此会降低半导体芯片的产率。
另一方面,在根据示例性实施例的扇出型半导体封装件100A的结构中,背重新分布层182可通过与使用包封件130包封半导体芯片120的工艺分开的工艺形成在树脂层180上,在背重新分布层182形成在树脂层180上的产品中,可仅选择地获取好的产品而不是坏的产品,并且所述好的产品可包括包封半导体芯片120的包封件130,以将背重新分布层182引入到包封件130。因此,可显著地减小以上所述的半导体芯片120的产量降低问题。因此,可显著地减小用于制造扇出型半导体封装件100A所需的成本,并且还可显著地减小用于制造扇出型半导体封装件100A所需的时间。
同时,根据示例性实施例的扇出型半导体封装件100A的背重新分布层182可通过形成在贯穿树脂层180和包封件130的第一开口181a中的连接构件191电连接到第一连接构件110的重新分布层112a和112b。在这种情况下,第一开口181a可暴露背重新分布层182的侧表面的至少一部分,连接构件191可接触背重新分布层182的暴露的侧表面。此外,第一开口181a可暴露第一连接构件110的第二重新分布层112b的表面的至少一部分,连接构件191可接触第一连接构件110的第二重新分布层112b暴露的表面。背重新分布层182和第一连接构件110的第二重新分布层112b可通过连接构件191彼此连接,使得可在界面处牢固地紧密粘结。因此,可进一步提高扇出型半导体封装件100A的可靠性。
此外,在根据示例性实施例的扇出型半导体封装件100A中,可通过第一开口181a使背重新分布层182和第一连接构件110的第二重新分布层112b彼此连接的位置暴露,使得可显著地提高使半导体芯片120等中产生的热消散的散热效果。此外,背重新分布层182可形成在层叠在具有如下所述的平坦的结构的可拆卸膜210上的树脂层180上,使得可显著地减小绝缘距离的偏差。因此,可在封装堆叠结构中均匀地保持扇出型半导体封装件100A与存储器封装件等结合的间隔。
在下文中,下面将更详细地描述根据示例性实施例的扇出型半导体封装件100A中包括的各个组件。
第一连接构件110可包括将半导体芯片120的连接焊盘122重新分布的重新分布层112a和112b,从而减少第二连接构件140的层的数量。如果需要,第一连接构件110可根据特定材料保持扇出型半导体封装件100A的刚度,并可用来确保包封件130的厚度的均匀性。此外,根据示例性实施例的扇出型半导体封装件100A可由于第一连接构件110而用作封装堆叠的一部分。第一连接构件110可具有通孔110H。半导体芯片120可设置在通孔110H中以与第一连接构件110分开预定距离。第一连接构件110可包围半导体芯片120的侧表面。然而,这种设置仅仅是示例性的,可以进行各种修改以具有其它设置,并且扇出型半导体封装件100A可根据这样的形式执行另一功能。
第一连接构件110可包括:绝缘层111,接触第二连接构件140;第一重新分布层112a,接触第二连接构件140并嵌在绝缘层111中;第二重新分布层112b,设置在绝缘层111的与绝缘层111的嵌入有第一重新分布层112a的一个表面背对的另一表面上。第一连接构件110可包括贯穿绝缘层111并将第一重新分布层112a和第二重新分布层112b彼此电连接的过孔113。第一重新分布层112a和第二重新分布层112b可电连接到连接焊盘122。当第一重新分布层112a嵌在绝缘层111中时,可显著地减小由于第一重新分布层112a的厚度而产生的台阶部,并因此可将第二连接构件140的绝缘距离变为常量。也就是说,从第二连接构件140的重新分布层142到绝缘层111的下表面的距离与从第二连接构件140的重新分布层142到连接焊盘122的距离的差可小于第一重新分布层112a的厚度。因此,可容易的进行第二连接构件140的高密度布线设计。
绝缘层111的材料没有具体限制。例如,绝缘材料可用作绝缘层111的材料。在这种情况下,绝缘材料可以是:诸如环氧树脂的热固性树脂;诸如聚酰亚胺树脂的热塑性树脂;例如半固化片、ABF(Ajinomoto Build up Film)、FR-4或双马来酰亚胺三嗪(BT)等的绝缘材料,其中,在该绝缘材料中,热固性树脂或热塑性树脂与无机填料一起浸有诸如玻璃布(或玻璃织物)的芯材料。可选地,还可将感光介质(PID)树脂用作绝缘层111的材料。
重新分布层112a和112b可用来将半导体芯片120的连接焊盘122重新分布。重新分布层112a和112b中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。重新分布层112a和112b可根据其对应的层的设计而执行各种功能。例如,重新分布层112a和112b中的每个可包括接地(GND)图案、功率(PWR)图案和信号(S)图案等。这里,信号(S)图案可包括除了接地(GND)图案和功率(PWR)图案等之外的各种信号,诸如数据信号等。此外,重新分布层112a和112b中的每个可包括过孔焊盘和连接端子焊盘等。
同时,如果需要,可在通过第一开口181a从第二重新分布层112b暴露的一些焊盘图案等的表面上形成表面处理层(未示出)。表面处理层(未示出)不受具体限制,只要它们是现有技术领域中已知的即可,并且可通过例如电镀金、非电镀金、有机可焊性保护剂(OSP)或非电镀锡、非电镀银、非电镀镍/置换镀金(substituted gold plating)、直接浸镀金(DIG)或热空气焊料均涂法(HASL)等形成。在形成有表面处理层(未示出)的情况下,所述第二重新分布层112b可被视为包括本公开中的表面处理层的概念。
过孔113可使形成在不同的层上的重新分布层112a和112b彼此电连接,从而在第一连接构件110中形成电路径。过孔113中的每个还可由导电材料形成。过孔113中的每个可完全填充有导电材料,如图11A和图11C中所述,或者也可沿着过孔113中的每个的壁形成导电材料,如图11B和图11D中所示。另外,过孔113中的每个可具有现有技术领域中已知的诸如锥形形状和圆柱形形状等的所有形状。同时,当形成用于过孔113的孔时,第一重新分布层112a的一些焊盘可用作阻挡件(stopper),因此在工艺中,过孔113中的每个具有其上表面的宽度大于下表面的宽度的锥形形状可以是有利的。在这种情况下,过孔113可与第二重新分布层112b的部分形成整体。
半导体芯片120可以是以数百至数百万个元件或更多个元件的数量设置且集成在单个芯片中的集成电路(IC)。所述IC可以是例如应用处理器芯片,诸如中央处理器(例如,CPU)、图形处理器(例如,GPU)、数字信号处理器、加密处理器、微处理器或微控制器等,但不限于此。半导体芯片120可基于活性晶圆(active wafer)形成。在这种情况下,主体121的基体材料可以是硅(Si)、锗(Ge)或砷化镓(GaAs)等。可在主体121上形成各种电路。连接焊盘122可将半导体芯片120与其它组件电连接。连接焊盘122的材料可以是诸如铝(Al)等的导电材料。使连接焊盘122暴露的钝化层123可形成在主体121上,并可以是氧化膜或氮化物膜等或者氧化物层和氮化物层的双层。连接焊盘122的下表面可通过钝化层123具有相对于包封件130的下表面的台阶部。因此,可在一定程度上防止包封件130流到连接焊盘122的下表面的现象。绝缘层(未示出)等还可进一步设置在其它所需位置。
半导体芯片120的无效表面可设置在位于第一连接构件110的第二重新分布层112b的上表面的下方的水平面上。例如,半导体芯片120的无效表面可设置在位于第一连接构件110的绝缘层111的上表面的下方水平面上。半导体芯片120的无效表面与第一连接构件110的第二重新分布层112b的上表面之间的高度差可以是2μm或更大,例如,5μm或更大。在这种情况下,可有效地防止半导体芯片120的无效表面的角落产生裂纹。此外,可显著地减小在使用包封件130的情况下半导体芯片120的无效表面上的绝缘距离的偏差。
包封件130可保护第一连接构件110和/或半导体芯片120。包封件130的封装形式不受具体限制,而可以是使包封件130包围第一连接构件110和/或半导体芯片120的至少一部分的形式。例如,包封件130可覆盖第一连接构件110和半导体芯片120的无效表面,并填充通孔110H的壁和半导体芯片120的侧表面之间的空间。此外,包封件130还可填充半导体芯片120的钝化层123和第二连接构件140之间的空间的至少一部分。同时,包封件130可填充通孔110H从而用作粘结剂,并根据特定材料减小半导体芯片120的翘曲。
包封件130的材料不受具体限制。例如,可使用绝缘材料作为包封件130的材料。在这种情况下,绝缘材料可以是包含无机填料和绝缘树脂的材料,例如,诸如环氧树脂的热固性树脂,诸如聚酰亚胺树脂的热塑性树脂,使诸如无机填料的增强材料浸在热固性树脂和热塑性树脂中的树脂(诸如ABF、FR-4或PID树脂等)。此外,还可以使用诸如EMC等的已知的成型材料。可选地,使热固性树脂或热塑性树脂与无机填料一起浸在诸如玻璃布(或玻璃织物)的芯材料中的材料也可用作绝缘材料。
同时,如果需要,包封件130可包括导电颗粒以阻挡电磁波。例如,导电颗粒可以是可阻挡电磁波的任何材料,例如,铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或焊料等。然而,这仅仅是示例,导电颗粒不具体限制于此。
第二连接构件140可被构造为将半导体芯片120的连接焊盘122重新分布。具有各种功能的几十到几百个连接焊盘122可通过第二连接构件140进行重新分布,并可根据功能通过将在下面进行描述的连接端子170物理连接或电连接到外部源(external source)。第二连接构件140可包括绝缘层141、设置在绝缘层141上的重新分布层142以及贯穿绝缘层141并将重新分布层142彼此连接的过孔143。在根据示例性实施例的扇出型半导体封装件100A中,第二连接构件140可包括单个层,但是还可包括多个层。
绝缘材料可用作绝缘层141的材料。在这种情况下,诸如感光介质(PID)树脂的光敏绝缘材料也可用作绝缘材料。也就是说,绝缘层141可以是光敏绝缘层。在绝缘层141具有光敏性质的情况下,绝缘层141可以形成为具有更小的厚度,并且可更容易地实现过孔143的精细间距。绝缘层141可以是包括绝缘树脂和无机填料的光敏绝缘层。当绝缘层141为多层时,绝缘层141的材料可彼此相同,如果需要,也可彼此不同。当绝缘层141为多层时,绝缘层141可根据工艺彼此成一体,使得它们之间的边界也可不明显。
重新分布层142可基本上用来重新分布连接焊盘122。重新分布层142中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料。重新分布层142可根据其对应的层的设计而执行各种功能。例如,重新分布层142中的每个可包括接地(GND)图案、功率(PWR)图案和信号(S)图案等。这里,信号(S)图案可包括除了接地(GND)图案和功率(PWR)图案等之外的诸如数据信号等的各种信号。此外,重新分布层142中的每个可包括过孔焊盘和连接端子焊盘等。
同时,如果需要,可在通过形成在下面将要描述的钝化层150中的开口151而暴露的第二连接构件140的重新分布层142的一些焊盘图案等的表面上形成表面处理层(未示出)。表面处理层(未示出)不受具体限制,只要它们是现有技术领域中已知的即可,并且可通过例如电镀金、非电镀金、OSP或非电镀锡、非电镀银、非电镀镍/置换镀金、DIG镀覆或HASL等形成。在形成表面处理层(未示出)的情况下,第二连接构件140的重新分布层142可视为概念地包括本公开的表面处理层。
过孔143可使形成在不同的层上的重新分布层142、连接焊盘122等彼此电连接,从而在扇出型半导体封装件100A中形成电路径。过孔143中的每个的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。过孔143可完全填充有导电材料,或也可沿着所述过孔的壁形成导电材料。此外,过孔143可具有现有技术领域中已知的诸如锥形和圆柱形等的任何形状。
第一连接构件110的重新分布层112a和112b的厚度可大于第二连接构件140的重新分布层142的厚度。由于第一连接构件110的厚度可大于或等于半导体芯片120的厚度,因此形成在第一连接构件110中的重新分布层112a和112b可根据第一连接构件110的比例形成为具有大的尺寸。另一方面,为了使第二连接构件140薄,第二连接构件140的重新分布层142的尺寸可相对小于第一连接构件110的重新分布层112a和112b的尺寸。同样地,第一连接构件110的过孔113的尺寸可大于第二连接构件140的重新分布层142的尺寸。
钝化层150可另外地被构造为保护第二连接构件140免受外部的物理损坏或化学损坏。钝化层150可具有由使第二连接构件140的重新分布层142的至少一部分暴露的多个孔形成的开口151。形成在钝化层150中的开口151的数量可设置为数十个至数千个。
具有比第二连接构件140的绝缘层141的弹性模量大的弹性模量的材料可用作钝化层150的材料。例如,不包括玻璃布(或玻璃织物)但包括无机填料和绝缘树脂的ABF等可用作钝化层150的材料。当ABF等用作钝化层150的材料时,钝化层150中包括的无机填料的重量百分比可大于第二连接构件140的绝缘层141中包括的无机填料的重量百分比。在这种条件下,可提高可靠性。当ABF等用作钝化层150的材料时,钝化层150可以是包括无机填料的非光敏绝缘层,并可有效地提高可靠性,但不限于此。
凸块下金属层160可另外地被构造为提高连接端子170的连接可靠性并提高扇出型半导体封装件100A的板级可靠性(board level reliability)。凸块下金属层160可连接到通过钝化层150的开口151暴露的第二连接构件140的重新分布层142。凸块下金属层160可使用诸如金属的已知导电金属通过已知的金属化方法形成在钝化层150的开口151中,但不限于此。
连接端子170可另外地被构造为在外部物理连接或电连接扇出型半导体封装件100A。例如,扇出型半导体封装件100A可通过连接端子170安装在电子装置的主板上。连接端子170中的每个可由例如焊料等的导电材料形成。然而,这仅仅是示例,连接端子170中的每个的材料并不具体受限于此。连接端子170中的每个可以是焊垫(land)、球或引脚等。连接端子170可由多层或单层形成。当连接端子170由多层形成时,连接端子170可包括铜柱和焊料。当连接端子170由单层形成时,连接端子170可包括锡-银焊料或铜。然而,这仅仅是示例,连接端子170不限于此。
连接端子170的数量、间隔、设置等不受具体限制,并且本领域的技术人员可根据设计细节进行充分地修改。例如,可根据半导体芯片120的连接焊盘122的数量将连接端子170的数量设置为数十个至数千个,但不限于此,还可以将连接端子170的数量设置为数十个至数千个或更多个。当连接端子170为焊球时,连接端子170可覆盖凸块下金属层160的延伸到钝化层150的一个表面上的侧表面,并且连接可靠性可更加优异。
连接端子170中的至少一个可设置在扇出区域。扇出区域是除了设置有半导体芯片120区域之外的区域。也就是说,根据示例性实施例的扇出型半导体封装件100A可以是扇出型封装件。与扇入型封装件相比,扇出型封装件可具有优异的可靠性,可实现多个输入/输出(I/O)端子,并可促进3D互连。此外,相比于球栅阵列(BGA)封装件或焊垫栅格阵列(land grid array,LGA)封装件等,扇出型封装件可在不需要单独的板的情况下安装在电子装置上。因此,扇出型封装件可制造为具有小的厚度,并可具有价格竞争力。
树脂层180可用于单独地制造背重新分布层182,并仅将包括单独地制造的背重新分布层182的产品中的好的产品引入到扇出型半导体封装件100A中。诸如包括无机填料和绝缘树脂的ABF或包括玻璃布(或玻璃织物)的半固化片等的已知的绝缘材料可用作树脂层180的材料。树脂层180中包括的无机填料的重量百分比可大于包封件130中包括的无机填料的重量百分比。在这种条件下,可在不导致诸如包封件130的脱层的缺陷的情况下,显著地减小扇出型半导体封装件100A由于树脂层180和包封件130之间的热膨胀系数(CTE)的差异而产生的翘曲。同时,在树脂层180包括与钝化层150的材料相同或相似的材料的情况下,例如,在树脂层180和钝化层150都包括包含无机填料和绝缘树脂的ABF的情况下,可更有效地控制扇出型半导体封装件100A的翘曲。
第一开口181a可贯穿树脂层180和包封件130。第一开口181a可使背重新分布层182的侧表面的至少一部分暴露。此外,第一开口181a可使第一连接构件110的第二重新分布层112b的表面的至少一部分暴露。连接构件191可形成在第一开口181a中。因此,连接构件191可接触背重新分布层182的暴露的侧表面和第一连接构件110的第二重新分布层112b的暴露的表面。结果,背重新分布层182和第一连接构件110的第二重新分布层112b可通过连接构件191彼此连接。在这样的形式中,界面紧密粘结可以是牢固的。因此,可进一步提高扇出型半导体封装件100A的可靠性。此外,背重新分布层182和第一连接构件110的第二重新分布层112b彼此连接的部分可通过第一开口181a敞开,使得可显著地增加使半导体芯片120等中产生的热消散的散热效果。
第二开口181b可贯穿树脂层180。第二开口181b可以不贯穿背重新分布层182,并可使背重新分布层182的表面的至少一部分暴露。背重新分布层182的暴露的表面可用作标记、用于焊球、表面安装组件等的焊盘或用于封装堆叠结构的焊盘等。可通过电镀金、非电镀金、OSP或非电镀锡、非电镀银、非电镀镍/置换镀金、DIG镀覆或HASL等在背重新分布层182的暴露的表面上形成表面处理层(未示出)。
在将根据示例性实施例的扇出型半导体封装件100A用于封装堆叠结构中的情况下,背重新分布层182可用来将半导体芯片120的连接焊盘122重新分布,并且还可用来分布安装在树脂层180上而不是插入基板上的存储器芯片等。背重新分布层182的材料可以是诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金的导电材料。背重新分布层182可根据其对应的层的设计而执行各种功能。例如,背重新分布层182可包括接地(GND)图案、功率(PWR)图案和信号(S)图案等。这里,信号(S)图案可包括除了接地(GND)图案和功率(PWR)图案之外的诸如数据信号等的各种信号。此外,背重新分布层182可包括过孔焊盘和连接端子焊盘等。
背重新分布层182可包括形成在树脂层180上的种子层182a和形成种子层182a上的导电层182b(如下所述)。种子层182a和导电层182b中的每个可包括诸如铜(Cu)的已知的导电材料。种子层182a可接触树脂层180。导电层182b可接触包封件130,并可与树脂层180分开。种子层180a可用作种子,因此种子层182a的厚度可比导电层182b的厚度薄。在一些情况下,构成树脂层180的绝缘树脂中包含的化学反应基团中的至少一个可自结合到形成在树脂层180的表面上的种子层182a的金属。在这种情况下,种子层182a和树脂层180之间可具有更优异的紧密粘结。
背重新分布层182可形成在层压于具有如下所述的平坦的结构的可拆卸膜210上的树脂层180上,使得可显著地减小绝缘距离的偏差。因此,当在封装堆叠结构中使用扇出型半导体封装件100A时,可均匀地保持扇出型半导体封装件100A与诸如存储器封装件的上封装件粘合的间隔。
连接构件191可将背重新分布层182和第一连接构件110的第二重新分布层112b彼此电连接。结果,可在扇出型半导体封装件100A中形成电路经。如果需要,当在封装堆叠结构中使用扇出型半导体封装件100A时,连接构件191还可用作连接到单独的封装件的端子。连接构件191可包括焊料等。连接构件191可以是例如焊球,但不限于此。
虽然未在附图中示出,但如果需要,还可在第一连接构件110的通孔110H的内壁上设置金属层。也就是说,金属层还可包围半导体芯片120的侧表面。可通过金属层沿着扇出型半导体封装件100A的向上或向下的方向有效地辐射从半导体芯片120产生的热,并可通过金属层有效地阻挡电磁波。此外,如果需要,可在第一连接构件110的通孔110H中设置多个半导体芯片,第一连接构件110的通孔110H的数量可以是多个,且半导体芯片可分别设置在通孔中。此外,诸如电容器(condenser)和电感器等的单独的无源组件可与半导体芯片一起设置在通孔100H中。此外,还可在钝化层150上安装表面安装组件,表面安装组件设置在与连接构件170的水平面基本相同的水平面上。
图12A至图12D是示出了制造图9的扇出型半导体封装件的工艺的示例的示图。
参照图12A,可通过分离工艺在可拆卸膜210上形成树脂层180和背重新分布层182。例如,可在已知的可拆卸膜210上层压树脂层180,可通过已知的镀覆方法在树脂层180上形成种子层182a。可在种子层182a上形成图案化的导电层182b,且可通过蚀刻等移除种子层182a的除了图案之外的部分。可使用诸如电镀、非电镀、化学气相沉积(CVD),物理气相沉积(PVD)、溅射、减成工艺、加成工艺、半加成工艺(SAP)或改性半加成工艺(MSAP)等已知的方法执行镀覆。可仅选择已制造的产品中的好的产品中的背重新分布层182。
参照图12B,可使用诸如粘结膜等的临时膜(temporary film)220通过独立于以上所述的图12A中示出的工艺的分离工艺将半导体芯片120设置在第一连接构件110的通孔110H中。例如,可形成第一连接构件110,第一连接构件110可附着到临时膜220上,并且半导体芯片120可以以正面朝下的形式附着到并设置在通过通孔110H暴露的临时膜220上。可在设置半导体芯片120之前仅选择第一连接构件110中的好的产品,因此还可在这种工艺中进一步提高半导体芯片120的产量。同时,可通过如下步骤形成第一连接构件110:在载体膜上形成第一重新分布层112a;形成将第一重新分布层112a埋于其中的绝缘层111;形成贯穿绝缘层111的过孔113;在绝缘层111上形成第二重新分布层112b,并将它们与载体膜分离。
参照图12C,可使用包封件130包封半导体芯片120。包封件130可至少包封第一连接构件110和半导体芯片120的无效表面,并可填充通孔110H内的空间。可通过已知方法形成包封件130。例如,可通过层压包封件130的前驱体并随后使前驱体硬化的方法形成包封件130。可选地,可通过将预包封件施加到临时膜220上以便包封半导体芯片120并随后使预包封件硬化的方法形成包封件130。作为层压前驱体的方法,例如,可使用如下方法:在高温下执行压制前驱体预定时间的热压工艺并对前驱体减压,然后将前驱体冷却至室温,使用冷压工艺冷却前驱体,然后分离作业工具(work tool)等。作为施加预包封件的方法,例如,可使用利用刮刀(squeegee)施加墨的丝网印刷方法或以雾的形态施加墨的喷墨印刷方法等。可通过硬化来固定半导体芯片120。然后,可在包封件130上层压其上单独地形成有背重新分布层182和树脂层180的可拆卸膜210,使得背重新分布层182嵌在包封件130中。然后,可移除可拆卸膜210。此外,可移除临时膜220。可使用精细的半导体工艺等在移除临时膜220的区域中形成第二连接构件140。可通过形成绝缘层141然后形成重新分布层142和过孔143来形成第二连接构件140。如果需要,可通过层压方法等在第二连接构件140上形成钝化层150,并且可在钝化层150中形成开口151。
参照图12D,可形成第一开口181a和第二开口181b。可使用机械钻孔或激光钻孔等来形成第一开口181a和第二开口181b。还可根据树脂层180和包封件130的绝缘材料通过光刻法形成第一开口181a和第二开口181b。然后,可在第一开口181a中形成连接构件191。连接构件191可以是焊球,但不限于此。如果需要,可通过已知方法来形成凸块下金属层160和连接端子170等。
图13是示出扇出型半导体封装件的另一示例的示意性截面图。
参照附图,根据本公开的另一示例性实施例的扇出型半导体封装件100B可包括由金属膏形成的连接构件192。例如,连接构件192可以是通过将金属膏施加到第一开口181a并烧结所述施加的金属膏而形成的金属柱,但不限于此。除了上述构造之外的其它构造以及制造方法的描述与以上描述的构造和制造方法重复,因此省略其描述。
图14是示出扇出型半导体封装件的另一示例的示意性截面图。
参照附图,在根据本公开的另一示例性实施例的扇出型半导体封装件100C中,第一连接构件110可包括:第一绝缘层111a,接触第二连接构件140;第一重新分布层112a,接触第二连接构件140并嵌在第一绝缘层111a中;第二重新分布层112b,设置在第一绝缘层111a的与第一绝缘层111a的嵌有第一重新分布层112a的一个表面背对的另一表面上;第二绝缘层111b,设置在第一绝缘层111a上并覆盖第二重新分布层112b;第三重新分布层112c,设置在第二绝缘层111b上。第一重新分布层112a、第二重新分布层112b以及第三重新分布层112c可电连接到连接焊盘122。同时,第一重新分布层112a和第二重新分布层112b以及第二重新分布层112b和第三重新分布层112c可分别通过贯穿第一绝缘层111a和第二绝缘层111b的第一过孔(未示出)和第二过孔(未示出)彼此电连接。
如上所述,由于嵌入了第一重新分布层112a,因此第二连接构件140的绝缘层141的绝缘距离可基本上恒定。由于第一连接构件110可包括大量的重新分布层112a、112b和112c,因此可进一步简化第二连接构件140。因此,可改善由于在形成第二连接构件140的工艺中产生的缺陷而导致的产量降低问题。第一重新分布层112a可凹入第一绝缘层111a中,使得第一绝缘层111a的下表面和第一重新分布层112a的下表面之间具有台阶部。结果,当形成包封件130时,可防止包封件130的材料流出而污染第一重新分布层112a的现象。
第一连接构件110的第一重新分布层112a的下表面可设置在位于半导体芯片120的连接焊盘122的下表面的上方的水平面上。此外,第二连接构件140的重新分布层142和第一连接构件110的第一重新分布层112a之间的距离可大于第二连接构件140的重新分布层142和半导体芯片120的连接焊盘122之间的距离。就这一点而言,第一重新分布层112a可凹入第一绝缘层111a中。第一连接构件110的第二重新分布层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。第一连接构件110可形成为具有与半导体芯片120的厚度对应的厚度。因此,形成在第一连接构件110中的第二重新分布层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。
第一连接构件110的重新分布层112a、112b和112c的厚度可大于第二连接构件140的重新分布层142的厚度。由于第一连接构件110的厚度可大于或等于半导体芯片120的厚度,因此重新分布层112a、112b和112c可根据第一连接构件110的比例形成为具有大的尺寸。另一方面,第二连接构件140的重新分布层142可形成为具有相对小的尺寸以减小厚度。
将在下文中提供除了以上所述的构造之外的构造以及制造方法的描述。同时,以上所述的扇出型半导体封装件100B的描述还可应用到扇出型半导体封装件100C。
图15是示出扇出型半导体封装件的另一示例的示意性截面图。
参照附图,在根据本公开的另一示例性实施例的扇出型半导体封装件100D中,第一连接构件110可包括:第一绝缘层111a;第一重新配层112a和第二重新分布层112b,分别设置在第一绝缘层111a的两个表面上;第二绝缘层111b,设置在第一绝缘层111a上并覆盖第一重新分布层112a;第三重新分布层112c,设置在第二绝缘层111b上;第三绝缘层111c,设置在第一绝缘层111a上并覆盖第二重新分布层112b;第四重新分布层112d,设置在第三绝缘层111c上。第一重新分布层112a、第二重新分布层112b、第三重新分布层112c以及第四重新分布层112d可电连接到连接焊盘122。由于第一连接构件110可包括大量的重新分布层112a、112b、112c和112d,因此可进一步简化第二连接构件140。因此,可改善由于在形成第二连接构件140的工艺中产生的缺陷而导致的产量降低问题。同时,第一重新分布层112a、第二重新分布层112b、第三重新分布层112c、第四重新分布层112d可通过贯穿第一绝缘层111a、第二绝缘层111b和第三绝缘层111c的第一过孔(未示出)、第二过孔(未示出)和第三过孔(未示出)彼此连接。
第一绝缘层111a的厚度可大于第二绝缘层111b和第三绝缘层111c的厚度。第一绝缘层111a可基本上是相对厚的,以保持刚度,并且可引入第二绝缘层111b和第三绝缘层111c以形成大量的重新分布层112c和112d。第一绝缘层111a可包含与第二绝缘层111b和第三绝缘层111c的绝缘材料不同的绝缘材料。例如,第一绝缘层111a可以是例如包含芯材料、无机填料和绝缘树脂的半固化片,第二绝缘层111b和第三绝缘层111c可以是包含无机填料和绝缘树脂的ABF或光敏绝缘膜。然而,第一绝缘层111a、第二绝缘树脂111b以及第三绝缘树脂111c的材料不限于此。
第一连接构件110的第三重新分布层112c的下表面可设置在半导体芯片120的连接焊盘122的下表面的下方的水平面上。此外,第二连接构件140的重新分布层142和第一连接构件110的第三重新分布层112c之间的距离可小于第二连接构件140的重新分布层142和半导体芯片120的连接焊盘122之间的距离。就这一点而言,第三重新分布层112c可以以突出的形式设置在第二绝缘层111b上,从而接触第二连接构件140。第一连接构件110的第一重新分布层112a和第二重新分布层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。第一连接构件110可形成为具有与半导体芯片120的厚度对应的厚度。因此,形成在第一连接构件110中的第一重新分布层112a和第二重新分布层112b可设置在半导体芯片120的有效表面和无效表面之间的水平面上。
第一连接构件110的重新分布层112a、112b、112c和112d的厚度可大于第二连接构件140的重新分布层142的厚度。由于第一连接构件110的厚度可大于或等于半导体芯片120的厚度,因此重新分布层112a、112b、112c和112d还可形成为具有大的尺寸。另一方面,第二连接构件140的重新分布层142可形成为具有相对小的尺寸,以减小厚度。
由于除了以上所述的构造之外的构造和制造方法的描述与以上所述的构造和制造方法重复,因此省略其描述。同时,以上所述的扇出型半导体封装件100B的描述还可应用到扇出型半导体封装件100D。
如上所述,根据本公开的示例性实施例,可提供一种可显著地减小半导体芯片的产量降低问题的扇出型半导体封装件。
虽然上面已示出并描述了示例性实施例,但对于本领域的技术人员将显而易见的是,在不脱离由权利要求所限定的本发明的范围的情况下,可以对这些实施例进行改变。
Claims (19)
1.一种扇出型半导体封装件,包括:
第一连接构件,具有通孔;
半导体芯片,设置在第一连接构件的通孔中,并具有有效表面和无效表面,所述有效表面上设置有连接焊盘,所述无效表面与有效表面背对;
包封件,包封第一连接构件和半导体芯片的无效表面的至少一部分;
第二连接构件,设置在第一连接构件和半导体芯片的有效表面上;
背重新分布层,包括导电层和种子层,导电层嵌在包封件中,种子层设置在导电层上并且具有比导电层的厚度薄的厚度;
树脂层,设置在包封件上,并且与背重新分布层的种子层和包封件接触,以及
连接构件,穿过背重新分布层和包封件,
其中,第一连接构件和第二连接构件分别包括电连接到半导体芯片的连接焊盘的重新分布层,并且
背重新分布层通过连接构件电连接到第一连接构件的重新分布层,并通过第一连接构件的重新分布层和第二连接构件的重新分布层电连接到半导体芯片的连接焊盘。
2.根据权利要求1所述的扇出型半导体封装件,其中,连接构件接触背重新分布层的暴露的侧表面。
3.根据权利要求1所述的扇出型半导体封装件,其中,所述连接构件从所述包封件突出。
4.根据权利要求1所述的扇出型半导体封装件,其中,树脂层包括使背重新分布层的种子层的表面的至少一部分暴露的开口。
5.根据权利要求1所述的扇出型半导体封装件,其中,连接构件包括焊料或金属膏。
6.根据权利要求1所述的扇出型半导体封装件,其中,第一连接构件包括第一绝缘层、第一重新分布层以及第二重新分布层,所述第一重新分布层接触第二连接构件并嵌在第一绝缘层中,所述第二重新分布层设置在第一绝缘层的与第一绝缘层的嵌入有第一重新分布层的一个表面背对的另一表面上,
第一重新分布层和第二重新分布层电连接到连接焊盘。
7.根据权利要求6所述的扇出型半导体封装件,其中,第一连接构件还包括第二绝缘层和第三重新分布层,所述第二绝缘层设置在第一绝缘层上并覆盖第二重新分布层,所述第三重新分布层设置在第二绝缘层上,且
第三重新分布层电连接到连接焊盘。
8.根据权利要求6所述的扇出型半导体封装件,其中,第二连接构件的重新分布层和第一重新分布层之间的距离大于第二连接构件的重新分布层和连接焊盘之间的距离。
9.根据权利要求6所述的扇出型半导体封装件,其中,第一重新分布层的厚度大于第二连接构件的重新分布层的厚度。
10.根据权利要求6所述的扇出型半导体封装件,其中,第一重新分布层的下表面设置在连接焊盘的下表面的上方的水平面上。
11.根据权利要求1所述的扇出型半导体封装件,其中,第一连接构件包括第一绝缘层以及第一重新分布层和第二重新分布层、所述第一重新分布层和所述第二重新分布层分别设置在第一绝缘层的背对的表面上,
第一重新分布层和第二重新分布层电连接到连接焊盘。
12.根据权利要求11所述的扇出型半导体封装件,其中,第一连接构件还包括第二绝缘层以及第三重新分布层,所述第二绝缘层设置在第一绝缘层上并覆盖第一重新分布层,所述第三重新分布层设置在第二绝缘层上,并且
第三重新分布层电连接到连接焊盘。
13.根据权利要求12所述的扇出型半导体封装件,其中,第一连接构件还包括第三绝缘层和第四重新分布层,所述第三绝缘层设置在第一绝缘层上并覆盖第二重新分布层,所述第四重新分布层设置在第三绝缘层上,
第四重新分布层电连接到连接焊盘。
14.根据权利要求13所述的扇出型半导体封装件,其中,第一绝缘层的厚度大于第二绝缘层的厚度。
15.根据权利要求11所述的扇出型半导体封装件,其中,第一重新分布层的厚度大于第二连接构件的重新分布层的厚度。
16.根据权利要求13所述的扇出型半导体封装件,其中,第四重新分布层的下表面设置在连接焊盘的下表面的下方的水平面上。
17.一种扇出型半导体封装件,包括:
第一连接构件,具有通孔;
半导体芯片,设置在第一连接构件的通孔中,并具有有效表面和无效表面,所述有效表面上设置有连接焊盘,所述无效表面与有效表面背对;
第二连接构件,设置在第一连接构件和半导体芯片的有效表面上;
树脂层,背重新分布层从树脂层朝向第二连接构件突出;
包封件,将树脂层连接到第一连接构件和半导体芯片,
其中,背重新分布层以及第一连接构件和第二连接构件的重新分布层电连接到半导体芯片的连接焊盘,并且
背重新分布层通过形成在贯穿树脂层和包封件的第一开口中的连接构件电连接到第一连接构件的重新分布层,连接构件接触树脂层的暴露的侧表面和背重新分布层的暴露的侧表面。
18.根据权利要求17所述的扇出型半导体封装件,其中,从树脂层突出的背重新分布层嵌在包封件中。
19.根据权利要求17所述的扇出型半导体封装件,其中,背重新分布层包括种子层和导电层,所述导电层的厚度大于种子层的厚度,所述种子层设置在树脂层和导电层之间。
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