CN111223835A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN111223835A
CN111223835A CN201911153469.8A CN201911153469A CN111223835A CN 111223835 A CN111223835 A CN 111223835A CN 201911153469 A CN201911153469 A CN 201911153469A CN 111223835 A CN111223835 A CN 111223835A
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redistribution
semiconductor package
layer
semiconductor chip
encapsulant
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CN201911153469.8A
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CN111223835B (zh
Inventor
李荣官
许荣植
韩泰熙
金容勋
李润泰
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供一种半导体封装件，所述半导体封装件包括：框架，具有腔并且包括布线结构，所述布线结构使所述框架的第一表面和第二表面连接；第一连接结构，位于所述框架的所述第一表面上并且包括连接到所述布线结构的第一重新分布层；第一半导体芯片，在所述腔内位于所述第一连接结构上；包封剂，包封所述第一半导体芯片并且覆盖所述框架的所述第二表面；第二连接结构，包括第二重新分布层，所述第二重新分布层包括第一重新分布图案和第一连接过孔；以及第二半导体芯片，设置在所述第二连接结构上并且具有第二连接垫，所述第二连接垫连接到所述第二重新分布层。

Description

半导体封装件
本申请要求于2018年11月27日在韩国知识产权局提交的第10-2018-0148324号韩国专利申请的优先权的权益，所述韩国专利申请的公开内容通过引用被全部包含于此。
技术领域
本公开涉及一种半导体封装件。
背景技术
近来，与半导体芯片有关的技术发展中的重要趋势是半导体芯片尺寸的减小。因此，在封装技术领域中，根据对小型半导体芯片等的需求的快速增加，已经要求在包括多个引脚的同时实现具有紧凑的尺寸的半导体封装件。
为满足上述技术需求而提出的一种封装件技术可以是扇出型半导体封装件。这样的扇出型半导体封装件具有紧凑的尺寸，并且可通过将连接端子重新分布到与半导体芯片重叠的区域之外的区域来实现多个引脚。可能需要背侧重新分布层(RDL)，以实现具有层叠封装(POP)结构的半导体封装件。
发明内容
本公开的一方面可提供一种具有可用于层叠封装(POP)结构的重新分布层的半导体封装件。
根据本公开的一方面，一种半导体封装件可包括：框架，具有腔并且包括布线结构，所述布线结构使所述框架的第一表面和第二表面彼此连接，所述第一表面和所述第二表面彼此相对；第一连接结构，设置在所述框架的所述第一表面上并且包括连接到所述布线结构的第一重新分布层；第一半导体芯片，在所述腔内设置在所述第一连接结构上，并且具有第一连接垫，所述第一连接垫连接到所述第一重新分布层；包封剂，包封所述第一半导体芯片并且覆盖所述框架的所述第二表面；第二连接结构，包括第二重新分布层，所述第二重新分布层包括第一重新分布图案和第一连接过孔，所述第一重新分布图案嵌在所述包封剂中并且具有从所述包封剂暴露的一个表面，并且所述第一连接过孔贯穿所述包封剂并且使所述布线结构和所述第一重新分布图案彼此连接；以及第二半导体芯片，设置在所述第二连接结构上并且具有第二连接垫，所述第二连接垫连接到所述第二重新分布层。
根据本公开的另一方面，一种半导体封装件可包括：第一半导体芯片，具有有效表面和无效表面，所述有效表面上设置有第一连接垫，所述无效表面与所述有效表面相对；第一连接结构，设置在所述第一半导体芯片的所述有效表面上并且包括连接到所述第一连接垫的第一重新分布层；包封剂，设置在所述第一连接结构上并且包封所述第一半导体芯片；布线结构，连接到所述第一重新分布层；第二连接结构，包括第二重新分布层，所述第二重新分布层具有重新分布图案和连接过孔，所述重新分布图案嵌在所述包封剂中并且具有从所述包封剂暴露的一个表面，并且所述连接过孔贯穿所述包封剂并且使所述布线结构和所述重新分布图案彼此连接；以及第二半导体芯片，设置在所述第二连接结构上并且具有连接到所述第二重新分布层的第二连接垫。
附图说明
通过下面结合附图进行的详细描述，本公开的以上和其他方面、特征和优点将被更清楚地理解，在附图中：
图1是示出电子装置系统的示例的示意性框图；
图2是示出电子装置的示例的示意性透视图；
图3A和图3B是示出扇入型半导体封装件在被封装之前和被封装之后的状态的示意性截面图；
图4是示出扇入型半导体封装件的封装工艺的示意性截面图；
图5是示出扇入型半导体封装件安装在中介基板上并且最终安装在电子装置的主板上的情况的示意性截面图；
图6是示出扇入型半导体封装件嵌在中介基板中并且最终安装在电子装置的主板上的情况的示意性截面图；
图7是示出扇出型半导体封装件的示意性截面图；
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图；
图9是示出根据本公开中的示例性实施例的半导体封装件的侧截面图；
图10是沿线I-I′截取的图9中所示的半导体封装件的平面图；
图11A和图11B分别是示出图9中所示的半导体封装件的局部区域(A部分)的放大的侧截面图和平面图；
图12是示出根据本公开中的示例性实施例的半导体封装件的局部区域的放大的侧截面图；
图13A至图13F是用于描述制造图9中所示的半导体封装件的方法的主要工艺(形成布线层的工艺和层压工艺)的截面图；
图14是示出面板级的图13D的工艺的示意图；
图15A至图15C是用于描述制造图9中所示的半导体封装件的方法的主要工艺(形成连接过孔的工艺)的截面图；
图16A至图16C是用于描述制造图9中所示的半导体封装件的方法的主要工艺(安装第二半导体芯片的工艺)的截面图；以及
图17和图18是示出根据本公开中的各种示例性实施例的半导体封装件的侧截面图。
具体实施方式
在下文中，将参照附图描述本公开中的示例性实施例。在附图中，为了清楚起见，可夸大或缩小组件的形状、尺寸等。
这里，为了方便起见，下侧、下部、下表面等用于表示与附图的截面相关的向下的方向，而上侧、上部、上表面等用于表示与向下的方向相反的方向。然而，定义这些方向是为了方便说明，并且权利要求不受如上所述定义的方向的具体限制，并且上部和下部的概念可彼此交换。
在描述中组件与另一组件的“连接”的含义在概念上包括通过粘合层的间接连接以及两个组件之间的直接连接。此外，“电连接”在概念上包括物理连接和物理断开。可以理解的是，当元件利用诸如“第一”和“第二”的术语提及时，元件不由此受限。这些术语仅可用于将元件与其他元件区分开的目的，并且可不限制元件的顺序或重要性。在一些情况下，在不脱离这里阐述的权利要求的范围的情况下，第一元件可被称为第二元件。类似地，第二元件也可被称为第一元件。
这里使用的术语“示例性实施例”不表示同一示例性实施例，而是被提供以强调与另一示例性实施例的特征或特性不同的特定的特征或特性。然而，这里提供的示例性实施例被认为能够通过整体或部分地彼此组合来实现。例如，除非其中提供相反或矛盾的描述，否则在特定示例性实施例中描述的一个元件，即使其在另一示例性实施例中未描述，也可理解为与另一示例实施例有关的描述。
这里使用的术语仅为了描述示例性实施例而非限制本公开。在这种情况下，除非上下文另有解释，否则单数形式也包括复数形式。
电子装置
图1是示出电子装置系统的示例的示意性框图。
参照图1，电子装置1000可将主板1010容纳在其中。主板1010可包括物理连接或者电连接到其的芯片相关组件1020、网络相关组件1030、其他组件1040等。这些组件可通过各种信号线1090连接到以下将描述的其他组件。
芯片相关组件1020可包括：存储器芯片，诸如易失性存储器(例如，动态随机存取存储器(DRAM))、非易失性存储器(例如，只读存储器(ROM))、闪存等；应用处理器芯片，诸如中央处理器(例如，中央处理单元(CPU))、图形处理器(例如，图形处理单元(GPU))、数字信号处理器、密码处理器、微处理器、微控制器等；以及逻辑芯片，诸如模拟数字转换器(ADC)、专用集成电路(ASIC)等。然而，芯片相关组件1020不限于此，而是也可包括其他类型的芯片相关组件。此外，芯片相关组件1020可彼此组合。
网络相关组件1030可包括根据诸如以下的协议操作的组件：无线保真(Wi-Fi)(电气与电子工程师协会(IEEE)802.11族等)、全球微波接入互操作性(WiMAX)(IEEE 802.16族等)、IEEE 802.20、长期演进(LTE)、演进仅数据(Ev-DO)、高速分组接入+(HSPA+)、高速下行链路分组接入+(HSDPA+)、高速上行链路分组接入+(HSUPA+)、增强型数据GSM环境(EDGE)、全球移动通信系统(GSM)、全球定位系统(GPS)、通用分组无线业务(GPRS)、码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、蓝牙、3G协议、4G协议和5G协议以及在上述协议之后指定的任意其他无线协议和有线协议。然而，网络相关组件1030不限于此，而是还可包括根据各种其他无线标准或协议或者有线标准或协议操作的组件。此外，网络相关组件1030可与上述芯片相关组件1020一起彼此组合。
其他组件1040可包括高频电感器、铁氧体电感器、功率电感器、铁氧体磁珠、低温共烧陶瓷(LTCC)、电磁干扰(EMI)滤波器、多层陶瓷电容器(MLCC)等。然而，其他组件1040不限于此，而是还可包括用于各种其他目的的无源组件等。此外，其他组件1040可与上述芯片相关组件1020或网络相关组件1030一起彼此组合。
根据电子装置1000的类型，电子装置1000可包括可物理连接或电连接到主板1010或者可不物理连接或不电连接到主板1010的其他组件。这些其他组件可包括例如相机1050、天线1060、显示器1070、电池1080、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器(未示出)、指南针(未示出)、加速度计(未示出)、陀螺仪(未示出)、扬声器(未示出)、大容量存储单元(例如，硬盘驱动器)(未示出)、光盘(CD)驱动器(未示出)、数字通用光盘(DVD)驱动器(未示出)等。然而，这些其他组件不限于此，而是还可根据电子装置1000的类型等而包括用于各种目的的其他组件。
电子装置1000可以是智能电话、个人数字助理(PDA)、数字摄像机、数码相机、网络系统、计算机、监视器、平板PC、膝上型PC、笔记本PC、电视机、视频游戏机、智能手表、汽车组件等。然而，电子装置1000不限于此，并且可以是处理数据的任意其他电子装置。
图2是示出电子装置的示例的示意性透视图。
参照图2，半导体封装件可在如上所述的各种电子装置1000中用于各种目的。例如，母板1110可容纳在智能电话1100的主体1101中，并且各种电子组件1120可物理连接或者电连接到母板1110。此外，可物理连接或电连接到母板1110或者可不物理连接或不电连接到母板1110的其他组件(诸如，相机模块1130)可容纳在主体1101中。电子组件1120中的一些可以是芯片相关组件，并且半导体封装件100可以是例如，芯片相关组件中的应用处理器，但不限于此。电子装置不必然地限于智能电话1100，而可以是如上所述的其他电子装置。
半导体封装件
通常，半导体芯片中集成了大量的微电子电路。然而，半导体芯片本身可能无法用作成品的半导体产品，并且可能由于外部的物理冲击或者化学冲击而损坏。因此，半导体芯片本身不被使用，而是被封装并且在封装状态下用在电子装置等中。
需要半导体封装的原因在于：就电连接而言，半导体芯片和电子装置的主板之间的电路宽度存在差异。详细地，半导体芯片的连接垫(pad，或者称为“焊盘”)的尺寸以及半导体芯片的连接垫之间的间距非常细小，而用在电子装置中的主板的组件安装垫的尺寸以及主板的组件安装垫之间的间距显著大于半导体芯片的连接垫的尺寸以及半导体芯片的连接垫之间的间距。因此，可能难以将半导体芯片直接安装在主板上，并且需要用于缓解半导体芯片和主板之间的电路宽度的差异的封装技术。
通过封装技术制造的半导体封装件可根据其结构和目的而分为扇入型半导体封装件和扇出型半导体封装件。
在下文中，将参照附图更详细地描述扇入型半导体封装件和扇出型半导体封装件。
扇入型半导体封装件
图3A和图3B是示出扇入型半导体封装件在被封装之前和被封装之后的状态的示意性截面图，并且图4是示出扇入型半导体封装件的封装工艺的示意性截面图。
参照图3A至图4，半导体芯片2220可以是例如处于裸态的集成电路(IC)，半导体芯片2220包括：主体2221，包括硅(Si)、锗(Ge)、砷化镓(GaAs)等；连接垫2222，形成在主体2221的一个表面上并且包括诸如铝(Al)等的导电材料；以及钝化层2223(诸如，氧化物层、氮化物层等)，形成在主体2221的一个表面上并且覆盖连接垫2222的至少部分。由于连接垫2222可能非常小，因此可能难以将集成电路(IC)安装在中等尺寸等级的印刷电路板(PCB)上以及电子装置的主板等上。
因此，根据半导体芯片2220的尺寸，可在半导体芯片2220上形成连接结构2240，以使连接垫2222重新分布。连接结构2240可通过如下步骤形成：使用诸如感光介电(PID)树脂的绝缘材料在半导体芯片2220上形成绝缘层2241，形成使连接垫2222敞开的通路孔2243h，然后形成布线图案2242和过孔2243。然后，可形成保护连接结构2240的钝化层2250，可形成开口2251，并且可形成凸块下金属层2260等。也就是说，可通过一系列工艺制造包括例如半导体芯片2220、连接结构2240、钝化层2250和凸块下金属层2260的扇入型半导体封装件2200。
如上所述，扇入型半导体封装件可具有半导体芯片的所有的连接垫(例如，输入/输出(I/O)端子)设置在半导体芯片内部的封装件形式，并且可具有优异的电特性，并且可按照低成本生产。因此，安装在智能电话中的许多元件已经按照扇入型半导体封装件形式来制造。详细地，安装在智能电话中的许多元件已经被开发为在具有紧凑尺寸的同时实现快速的信号传输。
然而，在扇入型半导体封装件中，由于所有的I/O端子需要设置在半导体芯片内部，因此扇入型半导体封装件具有显著的空间局限性。因此，难以将这种结构应用于具有大量的I/O端子的半导体芯片或者具有小尺寸的半导体芯片。此外，由于上述缺点，可能无法在电子装置的主板上直接安装和使用扇入型半导体封装件。原因在于：即使在半导体芯片的I/O端子的尺寸以及半导体芯片的I/O端子之间的间距通过重新分布工艺被增大的情况下，半导体芯片的I/O端子的尺寸以及半导体芯片的I/O端子之间的间距可能仍不足以将扇入型半导体封装件直接安装在电子装置的主板上。
图5是示出扇入型半导体封装件安装在中介基板上并且最终安装在电子装置的主板上的情况的示意性截面图，并且图6是示出扇入型半导体封装件嵌在中介基板中并且最终安装在电子装置的主板上的情况的示意性截面图。
参照图5，在扇入型半导体封装件2200中，半导体芯片2220的连接垫2222(即，I/O端子)可通过中介基板2301再次重新分布，并且在扇入型半导体封装件2200安装在中介基板2301上的状态下，扇入型半导体封装件2200可最终安装在电子装置的主板2500上。在这种情况下，低熔点金属或合金球2270等可通过底部填充树脂2280等固定，并且半导体芯片2220的外侧可利用包封剂2290等覆盖。可选地，参照图6，扇入型半导体封装件2200可嵌在单独的中介基板2302中，在扇入型半导体封装件2200嵌在中介基板2302中的状态下，半导体芯片2220的连接垫2222(即，I/O端子)可通过中介基板2302再次重新分布，并且扇入型半导体封装件2200可最终安装在电子装置的主板2500上。
如上所述，可能难以在电子装置的主板上直接安装和使用扇入型半导体封装件。因此，扇入型半导体封装件可安装在单独的中介基板上然后通过封装工艺安装在电子装置的主板上，或者可在扇入型半导体封装件嵌在中介基板中的状态下在电子装置的主板上安装和使用扇入型半导体封装件。
扇出型半导体封装件
图7是示出扇出型半导体封装件的示意性截面图。
参照图7，在扇出型半导体封装件2100中，例如，半导体芯片2120的外侧可通过包封剂2130保护，并且半导体芯片2120的连接垫2122可通过连接结构2140重新分布到半导体芯片2120外部。在这种情况下，可在连接结构2140上进一步形成钝化层2150，并且可在钝化层2150的开口中进一步形成凸块下金属层2160。可在凸块下金属层2160上进一步形成低熔点金属或合金球2170。半导体芯片2120可以是包括主体2121、连接垫2122、钝化层(未示出)等的集成电路(IC)。连接结构2140可包括：绝缘层2141；重新分布层2142，形成在绝缘层2141上；以及过孔2143，使连接垫2122和重新分布层2142彼此电连接。
在本制造工艺中，可在半导体芯片2120的外侧形成包封剂2130之后形成连接结构2140。在这种情况下，可在包封半导体芯片2120之后形成连接结构2140，因此连接到重新分布层的过孔2143可具有随着它们靠近半导体芯片而变小的宽度(参见放大区域)。
如上所述，扇出型半导体封装件可具有半导体芯片的I/O端子通过形成在半导体芯片上的连接结构重新分布并且设置在半导体芯片之外的形式。如上所述，在扇入型半导体封装件中，半导体芯片的所有的I/O端子需要设置在半导体芯片内部。因此，当半导体芯片的尺寸减小时，球的尺寸和节距需要减小，使得在扇入型半导体封装件中可能无法使用标准化的球布局。另一方面，如上所述，扇出型半导体封装件具有半导体芯片的I/O端子通过形成在半导体芯片上的连接结构重新分布并且设置在半导体芯片之外的形式。因此，即使在半导体芯片的尺寸减小的情况下，在扇出型半导体封装件中仍可按照原样使用标准化的球布局，使得扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上(如下所述)。
图8是示出扇出型半导体封装件安装在电子装置的主板上的情况的示意性截面图。
参照图8，扇出型半导体封装件2100可通过低熔点金属或合金球2170等安装在电子装置的主板2500上。也就是说，如上所述，扇出型半导体封装件2100包括连接结构2140，连接结构2140形成在半导体芯片2120上并且能够使连接垫2122重新分布到半导体芯片2120的尺寸之外的扇出区域，使得可在扇出型半导体封装件2100中按照原样使用标准化的球布局。结果，扇出型半导体封装件2100可在不使用单独的中介基板等的情况下安装在电子装置的主板2500上。
如上所述，由于扇出型半导体封装件可在不使用单独的中介基板的情况下安装在电子装置的主板上，因此扇出型半导体封装件可按照比使用中介基板的扇入型半导体封装件的厚度小的厚度实现。因此，扇出型半导体封装件可被小型化和纤薄化。此外，扇出型半导体封装件具有优异的热特性和电特性，使得其特别适合于移动产品。因此，扇出型半导体封装件可按照比使用印刷电路板(PCB)的普通的层叠封装(POP)类型的形式更紧凑的形式实现，并且可解决由于翘曲现象的发生而引起的问题。
另外，扇出型半导体封装是指如上所述的用于将半导体芯片安装在电子装置的主板等上并且保护半导体芯片免受外部冲击的封装技术，并且是与诸如中介基板的印刷电路板(PCB)等(具有与扇出型半导体封装件的规格、用途等不同的规格、用途等，并且具有嵌在其中的扇入型半导体封装件)的概念不同的概念。
图9是示出根据本公开中的示例性实施例的半导体封装件的侧截面图，并且图10是沿线I-I′截取的图9中示出的半导体封装件的平面图。
参照图9和图10，根据本示例性实施例的半导体封装件300可具有层叠封装(POP)结构，该层叠封装(POP)结构包括：下封装件100，包括第一半导体芯片120；以及上封装件200，设置在下封装件100上并且包括第二半导体芯片220。
下封装件100可包括：框架110，具有腔110X并且具有彼此相对的第一表面110A和第二表面110B；第一半导体芯片120，设置在腔110X中；第一连接结构140，设置在框架110的第一表面110A上并且位于第一半导体芯片120下方；以及第一包封剂130，包封设置在腔110X中的第一半导体芯片120并覆盖框架110的第二表面110B。
上封装件200可包括：第二连接结构160，设置在第一包封剂130上；第二半导体芯片220，设置在第二连接结构160上；以及第二包封剂230，设置在第二连接结构160上并且覆盖第二半导体芯片220。
在根据本示例性实施例的半导体封装件300的下封装件100中，框架110可包括绝缘构件111和布线结构，布线结构使第一表面110A和第二表面110B彼此连接。在本示例性实施例中，布线结构可包括：第一布线图案112a和第二布线图案112b，分别设置在框架110的第一表面110A和第二表面110B上；以及贯穿过孔113，使第一布线图案112a和第二布线图案112b彼此连接。
第一连接结构140可包括绝缘层141和形成在绝缘层141上的第一重新分布层145。第一重新分布层145可包括：重新分布图案142，设置在绝缘层上；以及重新分布过孔143，贯穿绝缘层141并连接到重新分布图案142。第一重新分布层145可通过重新分布过孔143连接到框架110的布线结构(具体地，第一布线图案112a)和第一半导体芯片120的连接垫120P。例示了本示例性实施例中使用的第一重新分布层145具有两层结构(它们分别设置在两个绝缘层141上)的情况，但第一重新分布层145不限于此，并且可具有一层结构或者三层或更多层的结构。
在本示例性实施例中使用的第二连接结构160可包括第二重新分布层165(其为背侧重新分布层)。由于第二连接结构160形成为不包括绝缘层的单层结构，因此第二重新分布层165本身可构成第二连接结构160，但在另一示例性实施例中(参见图17)，第二连接结构可包括额外使用的单独绝缘层和具有两层或更多层的结构的第二重新分布层。
在本示例性实施例中，第二重新分布层165可包括重新分布图案162(也可称为“第一重新分布图案”)和连接过孔163(也可称为“第一连接过孔”)。重新分布图案162可嵌在第一包封剂130中，使得其一个表面从第一包封剂130的上表面暴露，并且连接过孔163可贯穿第一包封剂130并将重新分布图案162连接到框架110的布线结构(具体地，第二布线图案112b)。如上所述，重新分布图案162可通过连接过孔163连接到第二布线图案112b，并且可通过框架110的布线结构连接到第一重新分布层145和第一半导体芯片120。
在本示例性实施例中，第一包封剂130可包括：包封绝缘层130a，包封第一半导体芯片120并且覆盖框架110的第二表面110B；以及结合绝缘层130b，设置在包封绝缘层130a上并且将重新分布图案162嵌在其中，使得重新分布图案162的一个表面暴露。
即使在使包封绝缘层130a硬化之后，结合绝缘层130b也可提供用于层压重新分布图案162的B阶段基底(B-stage base)。此外，可引入结合绝缘层130b作为用于提高平坦度的层，从而精确地实现层压工艺。例如，结合绝缘层130b可包括诸如ABF(Ajinomoto Build-up Film)的绝缘材料。在一些示例性实施例中，包封绝缘层130a可利用与结合绝缘层130b的绝缘材料相同的绝缘材料形成。即使包封绝缘层130a和结合绝缘层130b利用相同的材料形成，包封绝缘层130a和结合绝缘层130b的硬化时间点也彼此不同，因此可观察到包封绝缘层130a和结合绝缘层130b之间的界面。在另一示例性实施例中，包封绝缘层130a和结合绝缘层130b可利用不同的材料形成。
如图9中所示，第二钝化层172可形成在第一包封剂130的其上形成有第二重新分布层165的表面上。第二钝化层172可具有第二开口O2，第二开口O2使重新分布图案162的垫区域162P敞开。设置在第二连接结构上的第二半导体芯片可设置在第二开口O2之上的高度上。第二半导体芯片220的连接垫220P可通过利用铜形成的凸块CB分别连接到垫区域162P。底部填充材料210可填充在第二半导体芯片220和第二连接结构160之间。第二半导体芯片220可通过垫区域162P连接到第二重新分布层165，并且也可通过布线结构和第一重新分布层145电连接到第一半导体芯片120。
如上所述，在本示例性实施例中使用的第二重新分布层165可按照其嵌在第一包封剂130(具体地，结合绝缘层130b)中的形式实现，并且将参照图11A和图11B详细描述第二重新分布层165的结构。
图11A和图11B分别是示出图9中所示的半导体封装件300的区域A的放大截面图和局部平面图。图11A是沿图11B的线II-II′截取的侧截面图。
参照图11A和图11B，重新分布图案162可嵌在第一包封剂130(具体地，结合绝缘层130b)中使得其一个表面暴露，并且重新分布图案162的暴露的表面可与第一包封剂130的表面基本共面，但不限于此。例如，重新分布图案162的暴露的表面可设置在比第一包封剂130的表面略高或略低的高度上。
连接过孔163可设置为使重新分布图案162和布线结构的第二布线图案112b彼此连接的竖直路径。如图11B中所示，重新分布图案162可具有焊盘L，在焊盘L中形成有具有环形形状的开口R。开口不限于具有环形形状，并且可具有各种其他形状或其一部分敞开而非闭合的环形形状的类似环形形状。可在层压重新分布图案162之后设置连接过孔163。详细地，连接过孔163可通过镀覆工艺通过填充孔而形成(参见图15A和15B)，其中，所述孔通过重新分布图案的焊盘的开口R而连接到第二布线图案112b。由于本示例性实施例中使用的连接过孔163通过与形成重新分布图案162的工艺不同的工艺(镀覆工艺)形成，因此可观察到连接过孔163和重新分布图案162之间界面(诸如，晶界)。
连接过孔163与重新分布图案162接触的区域的宽度可大于连接过孔163与布线结构接触的区域的宽度。连接过孔163的上表面163T可在其中央部分处具有凹入区域。在本示例性实施例中，构成第二重新分布层165的其他重新分布图案162和其他连接过孔163也可具有与上述结构类似的结构。在一些示例性实施例中，通过用于连接过孔163的镀覆工艺和平坦化工艺可使连接过孔163的上表面与重新分布图案162的表面基本共面。
连接过孔163不限于上述示例性实施例(其中使用具有环形形状的开口R)，并且可连接到重新分布图案的一端。如图12中所示，连接过孔163可连接到重新分布图案162的一端同时连接到布线结构的第二布线图案112b。连接过孔163可包括设置在与第一包封剂130的界面上的种子层163S以及形成在种子层163S上的镀层163P，并且种子层163S可设置在连接过孔163的包括重新分布图案162的界面的表面上。图11A中所示的连接过孔163也可通过镀覆工艺形成，因此可具有如本示例性实施例中的包括种子层和镀层的结构。
根据本示例性实施例，在下封装件100中，可在形成第一连接结构140之前安装第一半导体芯片120，而在上封装件200中，可在形成第二连接结构160之后安装第二半导体芯片220(参见图16A至图16C)。
此外，下封装件100和上封装件200可不以根据现有技术的焊接方式彼此结合，而是可通过倒装芯片结合第二半导体芯片220的连接垫220P而彼此结合，从而可减小结合间隙并且可减小信号和电力的传输损耗。此外，可在层压工艺之前通过薄膜工艺(溅射或PID绝缘层)预先制造第二重新分布层165或重新分布图案162，因此可以以更精细的节距形成。
下文将更详细地描述包括在根据本示例性实施例的半导体封装件300中的各个组件。
框架110可保持半导体封装件300的刚性。第一半导体芯片120可设置在框架110的腔110X中，并且可通过第一包封剂130固定。框架110可为半导体封装件300提供延伸的路径区域，并且提高半导体封装件300在设计方面的自由度。在本示例性实施例中使用的框架110的布线结构仅仅是示例，并且可进行各种修改。例如，布线结构还可包括设置在框架110的中间高度上的一个或更多个图案。这些图案除了包括重新分布图案之外还可包括例如接地(GND)图案、电力(PWR)图案和信号图案。可在设置第一半导体芯片120之前形成这样的布线结构，从而抑制因第一半导体芯片120导致的良率的降低。
框架110的绝缘构件111可包括诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂或者其中浸有增强材料(诸如，玻璃纤维和/或无机填料)的树脂(例如，半固化片、ABF、RF-4、双马来酰亚胺三嗪(BT)等)。可选地，诸如感光介电(PID)树脂的感光绝缘材料可用作绝缘构件111的材料。作为另一示例，可使用具有优异刚性和导热性的金属。在这种情况下，可使用Fe-Ni基合金作为所述金属。在这种情况下，也可在Fe-Ni基合金的表面上形成Cu镀层以确保Fe-Ni基合金与第一包封剂130、另一层间绝缘材料等之间的粘合性。绝缘构件111不限于此，而是还可利用玻璃、陶瓷、塑料等形成。另外，布线结构可包括导电材料(诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)或它们的合金)，但不限于此。
第一连接结构140可被构造成使第一半导体芯片120的连接垫120P基本上重新分布。具有各种功能的数十至数百个连接垫120P可通过第一连接结构140重新分布，并且可通过电连接金属件190物理连接和/或电连接到外部设备。第一连接结构140可连接到第一半导体芯片120的连接垫120P，并且可支撑第一半导体芯片120。第一连接结构140可直接连接到第一半导体芯片120，并且电连接到框架110的布线结构和第二重新分布层165，第二半导体芯片220可连接到第二重新分布层165，并且第一半导体芯片120和第二半导体芯片220可通过第一重新分布层145、第二重新分布层165和布线结构以旁路的方式彼此电连接。
如上所述，第一连接结构140可包括绝缘层141和形成在绝缘层141上的第一重新分布层145，与上述绝缘构件类似，绝缘层141可包括诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂或者其中热固性树脂或热塑性树脂浸在诸如无机填料的增强材料中的树脂。诸如PID树脂的感光绝缘材料可用作绝缘层141中的每个的材料。如上所述，当将绝缘层引入第二连接结构160中并且在第二连接结构160中形成两个或更多个第二重新分布层165时，第二连接结构160的绝缘层也可利用与第一连接结构140的绝缘层141的材料相同或相似材料形成。
第一重新分布层145和第二重新分布层165可包括，例如，诸如(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)或它们的合金的导电材料。如果需要，还可在第二重新分布层162的暴露的垫区域162P上形成表面处理层。
第一包封剂130可被构造成保护框架110和第一半导体芯片120。在本示例性实施例中，第一包封剂130可包封框架110的第二表面110B以及第一半导体芯片120。第一包封剂130的包封形式没有特别限制，而可以是第一包封剂130围绕第一半导体芯片120的形式。例如，第一包封剂130可覆盖第一半导体芯片120，并且可填充框架110的腔110X内的剩余空间。第一包封剂130可填充腔110X，从而用作粘合剂并减小第一半导体芯片120的屈曲。第一包封剂130可覆盖第一半导体芯片120的除了第一半导体芯片120的下表面之外的所有表面。然而，第一包封剂130不限于此，根据第一半导体芯片120的连接垫120P的位置和形状，第一包封剂130可仅覆盖第一半导体芯片120的下表面的一部分。在一些示例性实施例中，第一包封剂130可包括多个层，所述多个层可利用相同材料形成，也可利用不同材料形成。详细地，在本示例性实施例中，第一包封剂130可包括：包封绝缘层130a，包封第一半导体芯片120并且覆盖框架110的第二表面110B；以及结合绝缘层130b，设置在包封绝缘层130a上并且将重新分布图案162嵌在其中，使得重新分布图案162的一个表面暴露。结合绝缘层130b可提供用于层压重新分布图案162的B阶段基底。在一些示例性实施例中，包封绝缘层130a可利用与结合绝缘层130b的绝缘材料相同的绝缘材料形成。在另一示例性实施例中，包封绝缘层130a和结合绝缘层130b可利用不同的材料形成。
第一包封剂130的材料没有特别限制，而可以是诸如环氧树脂的热固性树脂、诸如聚酰亚胺树脂的热塑性树脂、其中热固性树脂或热塑性树脂浸在增强材料(诸如，玻璃纤维和/或无机填料)中的树脂(例如，半固化片、ABF等)。此外，可使用任何已知的模制材料(诸如，环氧塑封料(EMC)等)。在一些示例性实施例中，包括玻璃纤维和/或无机填料以及绝缘树脂的材料可用作第一包封剂130的材料，以有效地抑制半导体封装件的翘曲。
在一些示例性实施例中，第一包封剂130可包括导电颗粒，以阻挡电磁波。例如，导电颗粒可包括(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、焊料等，但不限于此。
第二包封剂230可设置在第二钝化层172上并且可包封第二半导体芯片220。第二包封剂230可包括与第一包封剂130的绝缘材料相同或相似的绝缘材料。
根据本示例性实施例的半导体封装件300还可包括设置在第一连接结构140下方的第一钝化层171，第一钝化层171与第二钝化层172类似，第二钝化层172设置在其上形成有第二重新分布层165的第一包封剂130上。
第一钝化层171和第二钝化层172可被构造成分别保护第一连接结构140和第二重新分布层165免受外部物理损坏或化学损坏等。与上述第二钝化层172类似，第一钝化层171可具有第一开口O1，第一开口O1使第一连接结构140的重新分布图案142的至少部分暴露。第一钝化层171和第二钝化层172中的每个的材料没有特别限制，并且可以是，例如，阻焊剂。在一些示例性实施例中，与用于框架110和/或第一连接结构140的绝缘材料相同或相似的材料(例如，PID树脂、ABF等)可用作第一钝化层171和第二钝化层172中的每个的材料。
根据本示例性实施例的半导体封装件300还可包括电连接金属件190，电连接金属件190设置在第一钝化层171的第一开口O1中并且暴露到外部。电连接金属件190可被构造成将半导体封装件300物理连接和/或电连接到外部。例如，半导体封装件300可通过电连接金属件190安装在电子装置的母板上。电连接金属件190可连接到通过第一开口O1暴露的重新分布图案142。在一些示例性实施例中，可在重新分布图案142上形成额外的凸块下金属(UBM)层180，并且可形成电连接金属件190。
例如，电连接金属件190中的每个可利用诸如锡(Sn)或含锡(Sn)的合金的低熔点金属形成。电连接金属件190可具有诸如焊盘、焊球、引脚等的各种结构，但不限于此。
电连接金属件190中的一些可设置在扇出区域中。与扇入型封装件相比，扇出型封装件可具有优异的可靠性，可实现多个输入/输出(I/O)端子，并且可促进3D互连。电连接金属件190的阵列(数量、间隔等)没有特别限制，而可根据其上将安装半导体封装件的外部设备的状况进行各种修改。本示例性实施例中示出了电连接金属件190仅设置在第一连接结构140的下表面上的情况，但在一些示例性实施例中，与电连接金属件190类似的外部连接端子也可设置在第二重新分布层165的垫区域162P上。
图13A至图13F是用于描述制造图9中所示的半导体封装件的方法的主要工艺的截面图。在下文中将省略或简要描述在用于制造半导体封装件300的方法的描述中的与上面描述的内容重复的内容。
参照图13A，可通过在绝缘构件111中和绝缘构件111上形成布线结构来制备框架110。
绝缘构件111可以是具有薄的金属层(例如，铜箔(未示出))的覆铜层压板(CCL)，薄的金属层形成在覆铜层压板(CCL)的上表面和下表面上。铜箔可用作用于形成图案的种子层。可在绝缘构件111上形成第一布线图案112a和第二布线图案112b并且在绝缘构件111中形成使第一布线图案112a和第二布线图案112b彼此连接的贯穿过孔113。可使用机械钻和/或激光钻(例如，CO2激光钻或钇铝石榴石(YAG)激光钻)形成用于贯穿过孔113的孔。可执行去钻污工艺以去除孔(未示出)中的树脂钻污。可通过电镀铜、无电镀铜等使用干膜图案形成贯穿过孔113以及第一布线图案112a和第二布线图案112b。更详细地，可通过诸如减成工艺、加成工艺、半加成工艺(SAP)、改进的半加成工艺(MSAP)等的方法形成贯穿过孔113以及第一布线图案112a和第二布线图案112b，但不限于此。也就是说，如果需要，也可通过诸如化学气相沉积(CVD)、物理气相沉积(PVD)或溅射的方法形成贯穿过孔133以及第一布线图案112a和第二布线图案112b。
然后，参照图13B，可形成贯穿框架110的第一表面110A和第二表面110B的腔110X。
形成腔110X的方法也没有特别限制。例如，可通过机械钻和/或激光钻、使用用于研磨的颗粒的喷砂法、使用等离子体的干蚀刻法等形成腔110X。当使用机械钻和/或激光钻形成腔110X时，可执行去钻污工艺以去除腔110X中的树脂钻污。可根据将要安装在腔110X中的第一半导体芯片120(参见图13C)的尺寸、形状、数量等来设计腔110X的尺寸和形状。
接着，参照图13C，可将粘合支撑件310附连到框架110的第一表面110A，可将第一半导体芯片120设置在腔110X中，然后可形成用于包封第一半导体芯片120的第一包封剂130。
粘合支撑件310可以是具有可固定框架110的粘合表面的各种支撑构件。例如，各种类型的粘合带(诸如，粘合力会由于热处理而减弱的热固性粘合带、粘合力会由于紫外线照射而减弱的紫外线固化粘合带等)可用作粘合支撑件310。
可将第一半导体芯片120附连到腔110X中的粘合支撑件310并设置在腔110X中的粘合支撑件310上。可将第一半导体芯片120的连接垫120P附连到粘合支撑件310(面朝下)。当第一半导体芯片120的连接垫120P具有嵌入形式时，框架110的第二表面110B和第一半导体芯片120的上表面可彼此基本共面。相反，当第一半导体芯片120的连接垫120P具有突出形式时，框架110的下表面和连接垫120P的下表面可彼此基本共面。
第一包封剂130可覆盖框架110和第一半导体芯片120，并且可填充腔110X内的空间。第一包封剂130可通过任何已知的方法形成。例如，可使用利用刮板涂覆油墨的丝网印刷法、以雾的形式涂覆油墨的喷雾印刷法等作为涂覆方法。在一些示例性实施例中，可通过对第一包封剂130的前体进行层压然后进行硬化来形成第一包封剂130。
在本示例性实施例中，第一包封剂130可包括包封第一半导体芯片120的包封绝缘层130a和设置在包封绝缘层130a上的结合绝缘层130b。即使在使包封绝缘层130a硬化之后，结合绝缘层130b也可提供用于层压重新分布图案162的B阶段基底。例如，结合绝缘层130b可包括诸如ABF的绝缘材料。
然而，在另一示例性实施例中，在涂覆用于形成第一包封剂130的材料之后且在其完全硬化之前(例如，B阶段)，可转印设置在临时支撑件320下方的重新分布图案162以嵌在第一包封剂130的表面中(参见图13D和图13E)。
参照图13D，可将设置在临时支撑件320下方的重新分布图案162层压在没有硬化的或处于B阶段的第一包封剂130的表面(即，结合绝缘层130b)上。
可使用薄膜工艺(例如，溅射工艺)在临时支撑件320下方形成具有精细节距的重新分布图案162，但不限于此。在另一示例性实施例中，可通过使用种子层的镀覆工艺来形成重新分布图案162。在一些示例性实施例中，当形成具有两层或更多层的结构的重新分布层时(参见图17)，可引入诸如PID的绝缘层以通过光刻工艺形成精细图案。这样的精细图案可提供与第二半导体芯片的连接垫相对应的精细的垫区域。
在本工艺中，如图14中所示，可在不使用单独的配合器件的情况下按照铆销配合的方式形成面板级的中间产物。面板可包括多个(例如，六个)单元封装件(UP)。例如，可通过铆销P以及将铆销P容纳在其中的孔h来固定粘合支撑件310和临时支撑件320，以使重新分布图案162在期望的位置处精确地对准。即使使用上述铆销来执行对准，也可能发生不可避免的配合误差。
接着，参照图13E，可将重新分布图案162嵌入第一包封剂130的表面(即，结合绝缘层130b)中。
由于结合绝缘层130b处于未硬化状态(例如，处于B阶段)，因此可通过层压工艺将与临时支撑件320的表面相比形成为凸出的重新分布图案162嵌在结合绝缘层130b的表面中。当使用层压工艺时，可按照如下方式执行：执行在高温下对重新分布图案加压预定时间的热压工艺，对重新分布图案进行解压，并且将重新分布图案冷却至室温，然后在冷压机中对重新分布图案进行额外地冷却。
接着，参照图13F，可从框架110和第一半导体芯片120去除粘合支撑件310，然后可形成第一连接结构140。
本去除工艺没有特别限制，并且可通过各种方法执行。例如，当热固性粘合带(其粘合力由于热处理而减弱)、紫外线固化粘合带(其粘合力由于紫外线照射而减弱)等用作粘合支撑件310时，可在通过对粘合支撑件310进行热处理而使粘合支撑件310的粘合力减弱之后去除粘合支撑件310，或者可在通过利用紫外线照射粘合支撑件310而使粘合支撑件310的粘合力减弱之后去除粘合支撑件310。如上所述，在形成第一重新分布层145的工艺中，临时支撑件320可用作支撑件。
可在框架110下方和第一半导体芯片120的下表面上形成包括第一重新分布层145的第一连接结构140，并且可在第一连接结构140下方形成第一钝化层171。
在执行上述工艺之后，可执行形成设置在框架110的第二表面110B上的第二重新分布层165的工艺。详细地，可执行形成将嵌入的第二重新分布图案连接到布线结构(具体地，第二布线图案112b)的连接过孔的工艺。图15A至图15C是用于描述在制造图9中所示的半导体封装件的方法中的连接第二重新分布层的主要工艺(形成连接过孔的工艺)的截面图。
首先，参照图15A，可从第一包封剂130的表面去除临时支撑件320，然后可在重新分布图案162的具有环形形状的开口R中形成使第二布线图案112b暴露的孔H。
可去除临时支撑件320使得嵌入的重新分布图案162保留在第一包封剂130的表面中。可使用分离构件(诸如，释放层等)容易地去除临时支撑件320。可在根据临时支撑件或释放层的特性使用热处理、紫外线等使临时支撑件320的粘合力减弱之后容易地执行去除临时支撑件320的工艺。
重新分布图案162的开口R中的孔H可使第二布线图案112b暴露。例如，可使用机械钻和/或激光钻执行形成孔H的工艺。在执行钻孔工艺之后，可通过高锰酸盐法等执行去钻工艺，以去除树脂钻污。
然后，参照图15B，可在第一包封剂130上形成镀层163'，以填充孔H的内部。
可通过以下步骤获得本工艺：在第一包封剂130的表面以及孔H的内表面上形成种子层(未示出)，然后通过使用种子层的镀覆工艺形成镀层163'。如上所述形成的镀层163'可填充孔H的内部空间。
然后，参照图15C，可去除镀层的设置在第一包封剂130和重新分布图案162上的部分，从而形成连接过孔163。
可通过平坦化工艺(诸如，回蚀工艺或磨削工艺)执行这样的去除工艺。镀层的保留在孔H中的部分可设置为连接过孔163。连接过孔163可使布线结构的第二布线图案112b与重新分布图案162彼此连接。连接过孔163可与重新分布图案162一起形成期望的第二重新分布层165。重新分布图案162的暴露的表面可通过本工艺而与第一包封剂130的表面基本共面。在本示例性实施例中，连接过孔163的上表面可与重新分布图案162的暴露的表面基本共面，或者即使在平坦化工艺之后，连接过孔163也可具有如图11A中所示的凹入的上表面163T。
当在框架110下方和第一半导体芯片120的下表面上形成包括第一重新分布层145的第一连接结构140之后，可在第一连接结构140下方形成第一钝化层171，并且可形成使重新分布图案142暴露的第一开口O1。第一钝化层171的材料没有特别限制，并且可以是例如阻焊剂。在一些示例性实施例中，可使用与用于框架110和/或第一连接结构140的绝缘层141的绝缘材料相同或相似的材料(例如，PID树脂、ABF等)作为第一钝化层171的材料。
图16A至图16C是用于描述制造图9中所示的半导体封装件的方法的主要工艺(安装第二半导体芯片的工艺)的截面图。
参照图16A，可在第一包封剂130上形成第二钝化层172，并且可形成使垫区域162P暴露的第二开口O2。
第二钝化层172可被构造成保护第二重新分布层165免受外部物理损坏或化学损坏，并且可利用绝缘材料形成。可使用与上述第一钝化层的绝缘材料类似的绝缘材料来涂覆第二钝化层172，然后可形成使重新分布图案162的一部分(即，垫区域162P)暴露的第二开口O2。
参照图16B，可将第二半导体芯片220安装在第二连接结构160上，并且可将第二半导体芯片220的连接垫220P和垫区域162P彼此连接。
在本示例性实施例中，例示了第二半导体芯片220以面朝下的方式倒装芯片结合的形式。第二半导体芯片220可设置在第二开口O2之上的高度上。可在第二半导体芯片220和第二连接结构160之间填充底部填充材料210。可通过利用铜形成的凸块CB将第二半导体芯片220的连接垫220P分别连接到垫区域162P。第二半导体芯片220可通过垫区域162P连接到第二重新分布层165。
参照图16C，可形成包封第二半导体芯片的第二包封剂230，并且可在第一钝化层171的第一开口O1中形成电连接金属件190。
第二包封剂230可设置在第二钝化层172上并且可包封第二半导体芯片220。第二包封剂230可包括与第一包封剂130的绝缘材料相同或相似的材料。电连接金属件190可连接到通过第一开口O1暴露的重新分布图案142，可在重新分布图案142上形成额外的凸块下金属层180，并且可形成电连接金属件190。
图17是根据本公开中的示例性实施例的半导体封装件的侧截面图。
参照图17，可理解的是，除了第二连接结构160包括绝缘层161和具有两层结构的第二重新分布层165之外以及除了第二半导体芯片的类型和连接结构之外，根据本示例性实施例的半导体封装件300A与图9至图12中所示的半导体封装件300类似。除非另有明确描述，否则可参照图9至图12中所示的半导体封装件300的相同或类似的组件的描述来理解根据本示例性实施例的组件。
在本示例性实施例中使用的第二连接结构160可包括：第一重新分布图案162a，嵌在第一包封剂130中并且使第一重新分布图案162a的一个表面暴露；绝缘层161，具有与第一重新分布图案162a的暴露的表面和第一包封剂130的上表面接触的第一表面；以及第二重新分布图案162b，嵌在绝缘层161的第二表面中并且使第二重新分布图案162b的一个表面暴露。
第二重新分布层165可包括：第一连接过孔163a和第二连接过孔163b，贯穿绝缘层161和第一包封剂130；以及层间过孔164，贯穿绝缘层161并且使第一重新分布图案162a和第二重新分布图案162b彼此连接。
连接过孔可根据它们所连接到的重新分布图案而划分成数种类型的连接过孔163a和163b。与图15A和图15C中所示的工艺类似，可在层压工艺之后通过形成连接到期望的重新分布图案的孔并且执行镀覆和平坦化工艺来形成连接过孔。
第二连接过孔163b可使第一重新分布图案162a和第二布线图案112b彼此连接，并且可贯穿绝缘层161，但可不连接到第二重新分布图案162b(即，
第二连接过孔163b可与第二重新分布图案162b间隔开)。第一连接过孔163a可使第一重新分布图案162a和第二重新分布图案162b二者与第二布线图案112b连接。此外，第二重新分布层165还可包括第三连接过孔(未示出)，
第三连接过孔(未示出)连接到第二重新分布图案162b和第二布线图案112b并且不连接到第一重新分布图案162a(即，第三连接过孔可与所述第一重新分布图案162a间隔开)。
与第一连接过孔163a和第二连接过孔163b不同，层间过孔164可不延伸到第一包封剂130，并且可被构造成贯穿绝缘层161。层间过孔164可与第一重新分布图案162a具有一体化结构。在本说明书中，术语“一体化结构”并非意味着两个组件彼此简单地接触，而是表示两个组件通过相同工艺使用相同材料彼此一体地形成的结构。也就是说，层间过孔164和第一重新分布图案162a可被认为具有它们通过相同的镀覆工艺同时形成的“一体化结构”。
第一连接过孔163a和第二连接过孔163b与层间过孔164可在彼此相反的方向上形成，例如，第一连接过孔163a和第二连接过孔163b与层间过孔164可在相反的方向上渐缩。可在层压工艺之前在将第二连接结构形成在另一临时支撑件320(参见图13D)上的工艺中预先形成层间过孔164。详细地，可在临时支撑件上形成第二重新分布图案162b，可形成绝缘层161以覆盖第二重新分布图案162b，并且可将层间过孔164与第一重新分布图案162a一起形成以贯穿绝缘层161并连接到第二重新分布图案162b。因此，层间过孔164在其与第一重新分布图案162a接触的部分的宽度可大于其与第二重新分布图案162b接触的部分的宽度。
相反，第一连接过孔163a和第二连接过孔163b在其与第二钝化层172接触的部分的宽度可大于其与第二布线图案112b接触的部分的宽度。
可在本示例性实施例中使用的第二重新分布层不限于具有二层结构的重新分布层，并且可通过包括两个或更多个绝缘层实现为三层或更多层的结构。
在本示例性实施例中使用的第二半导体芯片可包括堆叠的两个或更多个半导体芯片220A和220B。堆叠的半导体芯片220A和220B可通过线W连接到垫区域162P。堆叠的半导体芯片220A和220B可彼此结合，同时通过粘合层AL结合到下封装件100'。例如，堆叠的半导体芯片220A和220B可包括诸如DRAM的存储器芯片。
第一半导体芯片220A和第二半导体芯片220B可包括存储器芯片和/或逻辑芯片的各种组合。例如，存储器芯片可以是易失性存储器芯片(诸如，DRAM或静态随机存取存储器(SRAM))或非易失性存储器芯片(诸如，相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)、铁电随机存取存储器(FeRAM)或电阻式随机存取存储器(RRAM))。此外，逻辑芯片可以是例如微处理器、模拟元件或数字信号处理器。
图18是示出根据本公开中的示例性实施例的半导体封装件的侧截面图。
参照图18，可理解的是，除了根据本示例性实施例的半导体封装件300B包括另一功能基板(例如，天线基板)以替代包括第二半导体芯片的上封装件并且除了下封装件100包括第一半导体芯片120A和第二半导体芯片120B以及无源组件115而不是仅包括半导体芯片120之外，根据本示例性实施例的半导体封装件300B与图9至图12中所示的半导体封装件300类似。除非另有明确描述，否则可参照图9至图12中所示的半导体封装件300的相同或类似的组件的描述来理解根据本示例性实施例的组件。
根据本示例性实施例的半导体封装件300B可包括替代上封装件结构的天线基板200B。天线基板200B(能够实现毫米波/5G天线的区域)可包括具有天线图案和接地图案的基板布线层212。详细地，天线基板200B可包括基板绝缘层211、基板布线层212、连接过孔层213以及基板钝化层222和224。
下封装件100可包括：多个无源组件115，设置在框架110的第一腔110X1中；以及第一半导体芯片120A和第二半导体芯片120B，分别设置在框架110的第二腔110X2和第三腔110X3中。例如，第一半导体芯片120A和第二半导体芯片120B可分别包括射频集成电路(RFIC)和电源管理集成电路(PMIC)，并且多个无源组件115可包括电容器、电感器等。
在本示例性实施例中，下封装件100和天线基板200B可通过电连接金属件270彼此物理连接和/或彼此电连接。电连接金属件270中的每个可利用低熔点金属(例如，锡(Sn)或含锡(Sn)的合金，更具体地，焊料)形成。然而，这仅仅是示例，并且电连接金属件270中的每个的材料不具体限于此。
如上所述，除了具有典型的PoP结构的半导体封装件之外，根据本示例性实施例的半导体封装件还可通过结合到另一功能基板(诸如，天线基板)而设置为具有与PoP结构类似的结构的各种模块。
如上所阐述的，根据本公开中的示例性实施例，可按照单独制造背侧重新分布结构然后在下封装件结构上层压上封装件结构的方式设置具有层叠封装结构的半导体封装件，从而可减小半导体封装件的厚度，并且可显著改善半导体封装件的电可靠性(例如，传输效率)和/或散热性能。
虽然以上已经示出和描述了示例性实施例，但是对本领域技术人员将明显的是，在不脱离由所附权利要求限定的本发明的范围的情况下，可以进行修改和变型。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
框架，具有腔并且包括布线结构，所述布线结构使所述框架的第一表面和第二表面连接，所述第一表面和所述第二表面彼此相对；
第一连接结构，设置在所述框架的所述第一表面上并且包括连接到所述布线结构的第一重新分布层；
第一半导体芯片，在所述腔内设置在所述第一连接结构上，并且具有第一连接垫，所述第一连接垫连接到所述第一重新分布层；
第一包封剂，包封所述第一半导体芯片并且覆盖所述框架的所述第二表面；
第二连接结构，包括第二重新分布层，所述第二重新分布层包括第一重新分布图案和第一连接过孔，所述第一重新分布图案嵌在所述第一包封剂中并且具有从所述第一包封剂暴露的一个表面，并且所述第一连接过孔贯穿所述第一包封剂并且使所述布线结构和所述第一重新分布图案彼此连接；以及
第二半导体芯片，设置在所述第二连接结构上并且具有第二连接垫，所述第二连接垫连接到所述第二重新分布层。
2.根据权利要求1所述的半导体封装件，所述半导体封装件还包括钝化层，所述钝化层设置在所述第二连接结构上并且具有开口，所述开口使所述第二重新分布层的部分区域暴露，
其中，所述第二半导体芯片的所述第二连接垫通过所述开口连接到所述第二重新分布层的所述部分区域。
3.根据权利要求2所述的半导体封装件，其中，所述第二重新分布层的所述部分区域包括多个垫，并且
所述第二半导体芯片设置在所述开口上，并且所述第二半导体芯片的所述第二连接垫分别连接到所述多个垫。
4.根据权利要求2所述的半导体封装件，其中，所述第二半导体芯片设置在所述钝化层上，并且所述第二半导体芯片的所述第二连接垫通过布线连接到所述第二重新分布层的所述部分区域。
5.根据权利要求2所述的半导体封装件，所述半导体封装件还包括第二包封剂，所述第二包封剂设置在所述钝化层上并且包封所述第二半导体芯片。
6.根据权利要求1所述的半导体封装件，其中，所述第一包封剂包括：包封绝缘层，包封所述第一半导体芯片并且覆盖所述框架的所述第二表面；以及结合绝缘层，设置在所述包封绝缘层上，并且使所述第一重新分布图案嵌在所述结合绝缘层中，使得所述第一重新分布图案的所述一个表面从所述结合绝缘层暴露。
7.根据权利要求1所述的半导体封装件，其中，所述第一重新分布图案包括具有开口的焊盘，并且
所述第一连接过孔贯穿所述第一重新分布图案的所述开口。
8.根据权利要求1所述的半导体封装件，其中，所述第一连接过孔连接到所述第一重新分布图案的一端并且贯穿所述第一包封剂。
9.根据权利要求1所述的半导体封装件，其中，所述第一连接过孔在所述第一连接过孔的与所述第一重新分布图案接触的部分的宽度大于在所述第一连接过孔的与所述布线结构接触的部分的宽度。
10.根据权利要求1所述的半导体封装件，其中，所述第一包封剂的上表面与所述第一重新分布图案的被暴露的所述一个表面基本共面。
11.根据权利要求1所述的半导体封装件，其中，所述第二连接结构还包括绝缘层，所述绝缘层具有：第一表面，与所述第一重新分布图案的被暴露的所述一个表面和所述第一包封剂的上表面接触；以及第二表面，与所述绝缘层的所述第一表面相对，并且
所述第二重新分布层还包括：第二重新分布图案，嵌在所述绝缘层的所述第二表面中并且具有从所述绝缘层的所述第二表面暴露的一个表面；以及层间过孔，贯穿所述绝缘层并且使所述第一重新分布图案和所述第二重新分布图案彼此连接，并且所述第一连接过孔延伸以贯穿所述绝缘层。
12.根据权利要求11所述的半导体封装件，其中，所述层间过孔具有与所述第一重新分布图案的一体化结构。
13.根据权利要求11所述的半导体封装件，其中，所述层间过孔在所述层间过孔的与所述第一重新分布图案接触的部分的宽度大于在所述层间过孔的与所述第二重新分布图案接触的部分的宽度。
14.根据权利要求11所述的半导体封装件，其中，所述第一连接过孔连接到所述第二重新分布图案。
15.根据权利要求14所述的半导体封装件，所述半导体封装件还包括第二连接过孔，所述第二连接过孔贯穿所述第一包封剂和所述绝缘层，并且使所述布线结构和所述第一重新分布图案彼此连接，
其中，所述第二连接过孔与所述第二重新分布图案间隔开。
16.根据权利要求11所述的半导体封装件，所述半导体封装件还包括第三连接过孔，所述第三连接过孔贯穿所述绝缘层和所述第一包封剂，并且连接到所述第二重新分布图案和所述布线结构，并且
所述第三连接过孔与所述第一重新分布图案间隔开。
17.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，具有有效表面和无效表面，所述有效表面上设置有第一连接垫，所述无效表面与所述有效表面相对；
第一连接结构，设置在所述第一半导体芯片的所述有效表面上并且包括连接到所述第一连接垫的第一重新分布层；
包封剂，设置在所述第一连接结构上并且包封所述第一半导体芯片；
布线结构，连接到所述第一重新分布层；
第二连接结构，包括第二重新分布层，所述第二重新分布层具有第一重新分布图案和连接过孔，所述第一重新分布图案嵌在所述包封剂中并且具有从所述包封剂暴露的一个表面，并且所述连接过孔贯穿所述包封剂并且使所述布线结构和所述第一重新分布图案彼此连接；以及
第二半导体芯片，设置在所述第二连接结构上并且具有连接到所述第二重新分布层的第二连接垫。
18.根据权利要求17所述的半导体封装件，其中，所述连接过孔在所述连接过孔的与所述第一重新分布图案接触的部分的宽度大于在所述连接过孔的与所述布线结构接触的部分的宽度。
19.根据权利要求17所述的半导体封装件，其中，所述第二连接结构还包括绝缘层，所述绝缘层具有第一表面和第二表面，所述第一表面与所述第一重新分布图案的被暴露的所述一个表面和所述包封剂的上表面接触，所述第二表面与所述绝缘层的所述第一表面相对，并且
所述第二重新分布层还包括：第二重新分布图案，嵌在所述绝缘层的所述第二表面中并且具有从所述绝缘层的所述第二表面暴露的一个表面；以及层间过孔，贯穿所述绝缘层并且使所述第一重新分布图案和所述第二重新分布图案彼此连接。
20.根据权利要求19所述的半导体封装件，其中，所述连接过孔延伸以贯穿所述绝缘层，并且
所述连接过孔和所述层间过孔在相反的方向上渐缩。
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