TW200529722A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board Download PDF

Info

Publication number
TW200529722A
TW200529722A TW094103371A TW94103371A TW200529722A TW 200529722 A TW200529722 A TW 200529722A TW 094103371 A TW094103371 A TW 094103371A TW 94103371 A TW94103371 A TW 94103371A TW 200529722 A TW200529722 A TW 200529722A
Authority
TW
Taiwan
Prior art keywords
layer
conductor
holes
thickness
power supply
Prior art date
Application number
TW094103371A
Other languages
Chinese (zh)
Other versions
TWI341704B (en
Inventor
Yasushi Inagaki
Katsuyuki Sano
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Publication of TW200529722A publication Critical patent/TW200529722A/en
Application granted granted Critical
Publication of TWI341704B publication Critical patent/TWI341704B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H01L2223/6622—Coaxial feed-throughs in active or passive substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01084—Polonium [Po]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0352—Differences between the conductors of different layers of a multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores

Abstract

Disclosed is a package board wherein a malfunction or error is prevented from occurring even when a high-frequency IC chip, in particular an IC chip of more than 3 GHz is used. A conductor layer (34P) having a thickness of 30 mum is formed on a core substrate (30), and a conductor circuit (58) having a thickness of 15 mum is formed on a interlayer resin insulating layer (50). By forming the conductor layer (34P) thick, the volume of the conductor itself is increased, thereby reducing the resistance. In addition, by using the conductor layer (34) as a power supply layer, there can be improved the supply capacity of the power source to the IC chip.

Description

200529722 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種多層印刷電路板；提議一種關於高頻之ic晶 片、特別即使是構裝在3GHz以上之高頻區域之1C晶片也不發生錯誤 動作或錯誤等而能夠提高電氣特性或可靠性之多層印刷電路板。 【先前技術】 在構成1C晶片用之封裝之增層（build_up)式之多層印刷電路 板，在形成通孔之芯基板之兩面或單面，形成層間絕緣樹脂，藉由雷 射或光蝕刻而對於層間導通用之導通孔，來進行開口，形成層間樹脂 春絕緣層。在該導通孔内壁和層間樹脂絕緣層上，藉由電鍍等而形成導 體層，經過蝕刻等，形成圖案，作出導體電路。此外，藉由重複地形 成層間絕緣層和導體層而得到增層多層印刷電路板。配合於需要，藉 由在表層，形成錫鉛凸塊、外部端子（PGA/BGA等），而成為能夠構裝 1C晶片之基板或封裝基板。ic晶片係藉由進行C4(覆晶）構裝而進行 1C晶片和基板間之電氣連接。 作為增層式多層印刷電路板之先前技術係有日本特開平6 一 260756號公報、日本特開平6_ 275959號公報等。同時，在藉由填充 樹脂來填充通孔之芯基板上，形成接端面（land)，施行在兩面具有導 鲁通孔之層間絕緣層，藉由加成法而施行導體層，藉由連接於接端面而 得到形成高密度化、微細配線之多層印刷電路板。 【發明内容】 【發明所欲解決的課題】 -IC晶片成為高頻而使得錯誤動作或錯誤之發生頻与 冋。特別疋在頻率超過3GHz日寺，因此，其程度變古 $生頻^ 也完全無法動作。因此，在具備該IC晶片來;^p。在超過驗 進打應該發揮功能之動作、例 厂、之電腦，不' 外部之傳達等之要求之功能或、_之切換、資料袭 在分別對於這些1c晶片、基板來進行非破壞檢查或分解時’ 2160-6825-pp;Ahddub 200529722 / IC晶片、基板本身，不發生短路或開放等之問題，在構裝頻率小（特 別是未滿1GHz)之1C晶片之狀態下，並無發生錯誤動作或錯誤。 本發明人們係為了解決前述課題，因此，正如日本特願2 〇 〇 2 — 233775號中之所記載的，提議使得芯基板上之導體厚度之厚度更加厚 於層間絕緣層上之導體層之厚度。但是，在前述發明，在企&製彳=具 有微細之配線圖案之芯基板時，使得配線圖案間之絕緣間隔變窄，^ 為絕緣可靠性變差之印刷電路板。 成為第1發明之目的係提議一種可以構成高頻區域之Ic晶片、特 別即使是超過3GHz也不發生錯誤動作或錯誤而具有高絕緣靠性之 印刷基板或封裝基板之多層印刷電路板。 • 在第2發明，作為在高頻之錯誤動作之對策係本發明人就使用多 層芯基板來成為芯基板而在多層芯基板内設置厚度變厚之導體層，來 進行檢討。 就該多層印刷電路板而言，參考圖35，來進行說明。在多層印刷 電路板10，使用多層芯基板30。在多層芯基板3〇表面之訊號電路 34S、電源電路34P、地線電路34E之上面，配置：形成導通孔6〇和 導體電路58之層間絕緣層50以及形成導通孔16〇和導體電路158之 層間絕緣層150。在該導通孔160和導體電路158之上層，形成銲錫 阻劑層70，透過該銲錫阻劑層70之開口部71，而在導通孔16〇和導 體電路158，形成凸塊76U、76D。200529722 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a multilayer printed circuit board; it is proposed that a high-frequency IC chip, especially a 1C chip configured in a high-frequency region above 3GHz does not occur. A multilayer printed circuit board that can improve electrical characteristics or reliability by malfunction or error. [Previous technology] In a build-up type multilayer printed circuit board constituting a package for a 1C chip, an interlayer insulating resin is formed on both sides or one side of a core substrate forming a through hole, and is formed by laser or photolithography. The interlayer conductive vias are opened to form an interlayer resin spring insulating layer. A conductive layer is formed on the inner wall of the via hole and the interlayer resin insulating layer by electroplating or the like, and a pattern is formed by etching to form a conductor circuit. In addition, an increased multilayer printed circuit board is obtained by repeatedly forming the interlayer insulating layer and the conductor layer. According to needs, by forming tin-lead bumps and external terminals (PGA / BGA, etc.) on the surface layer, it becomes a substrate or package substrate capable of constructing a 1C chip. The IC chip is electrically connected between the 1C chip and the substrate by performing a C4 (Flip-Chip) structure. The prior art as the build-up multilayer printed circuit board includes Japanese Patent Laid-Open No. 6-260756, Japanese Patent Laid-Open No. 6-275959, and the like. At the same time, a land is formed on the core substrate through which the through holes are filled with a filling resin, and an interlayer insulating layer having a via hole on both sides is implemented. A conductor layer is implemented by an addition method, and is connected to By connecting the end faces, a multilayer printed wiring board having high density and fine wiring can be obtained. [Summary of the Invention] [Problems to be Solved by the Invention]-The IC chip becomes a high frequency and causes a malfunction or occurrence frequency of the malfunction. In particular, the temple is at a frequency higher than 3GHz, so its degree has become ancient. Therefore, the IC chip comes; ^ p. In the case of exceeding the inspection, the functions that should be performed, such as the factory, the computer, the function that does not require external communication, or the switching of _, data, etc., are non-destructive inspection or decomposition of these 1c chips and substrates, respectively. 2160-6825-pp; Ahddub 200529722 / IC chip, substrate itself, no problems such as short circuit or open, and no error action occurred when the 1C chip with low frequency (especially less than 1GHz) was installed. Or wrong. In order to solve the aforementioned problems, the present inventors propose to make the thickness of the conductor thickness on the core substrate thicker than that of the conductor layer on the interlayer insulation layer, as described in Japanese Patent Application No. 2000-233775. thickness. However, in the aforementioned invention, when a core board having a fine wiring pattern is manufactured, the insulation interval between the wiring patterns is narrowed, and the printed circuit board has poor insulation reliability. The object of the first invention is to propose a multilayer printed circuit board capable of constituting an Ic chip in a high frequency region, and particularly a printed circuit board or a package substrate having high insulation reliability without erroneous operation or error even at a frequency exceeding 3 GHz. • In the second invention, as a countermeasure against malfunctions at high frequencies, the present inventors conducted a review by using a multi-layered core substrate as a core substrate and providing a thicker conductive layer in the multi-layered core substrate. This multilayer printed wiring board will be described with reference to FIG. 35. In the multilayer printed wiring board 10, a multilayer core substrate 30 is used. On the signal circuit 34S, power supply circuit 34P, and ground circuit 34E on the surface of the multilayer core substrate 30, an interlayer insulating layer 50 forming a via 60 and a conductor circuit 58 and forming a via 16 and a conductor circuit 158 are arranged. Interlayer insulation layer 150. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and through the opening 71 of the solder resist layer 70, bumps 76U and 76D are formed in the via hole 160 and the conductor circuit 158.

• 多層芯基板30上側之電源電路34P係形成為電源用平面層，下側 之地線電路34E係形成為地線用平面層。此外，在多層芯基板川内部 之表面側，形成内層之地線電路16E和由電源用通孔36THp開始延出 之假接鈿面16D，在背面，形成電源電路Bp和由地線用通孔36THE 開始延出之假接端面16D。所謂假接端面係由通孔開始延出之導體電 路，係表示不導通於同一層内之其他配線之配線圖案或者是呈電氣地 連接相同電位之配線圖案（圖36(A)中之16DI)。上侧之地線電路ι6Ε 係形成為地線用平面層，下側之電源電路16p係形成為電源用平面 層。圖36(A)係顯示圖35中之X4-X4橫剖面，圖36(B)係顯示χ5_ Χ5橫剖面。設置多層芯基板30表背面之連接用通孔36。假接端面16D 2160-6825-PF；Ahddub 6 200529722 / 係設置在不連接於地線電路16E、電源電路16P之通孔36之周圍。在 假接端面之周圍，用以確保假接端面和其他配線圖案間之絕緣（非導體 形成部分（非導體形成部分拉拔部35))。此外，正如圖36(A)所示，在 鄰接之位置位處有相同電位之通孔之狀態下，也有形成在這些通孔周 邊之總刮地形成之假接端面16DI之狀態發生。 得知：在此種構造之多層印刷電路板，藉由使得多層芯基板30 之地線電路16E、16P變厚，而在開關成為0N(導通）後，在發生複數 次之1C之電壓下降中，主要改善第3次之電壓下降。但是，得知：關 於第1次、第2次之電壓下降而言，並無大幅度地改善。 第2發明係為了解決前述課題而完成的，其目的係提議一種可以 鲁構成高頻區域之1C晶片、特別是即使超過3GHz也不發生錯誤動作或 錯誤之印刷基板或封裝基板之多層印刷電路板。特別是改善在開關成 為0N(導通）後之所發生之電壓下降中之第1次和第2次之電壓下降。 【用以解決課題的手段】 [第1發明]• The power supply circuit 34P on the upper side of the multilayer core substrate 30 is formed as a plane layer for power supply, and the ground circuit 34E on the lower side is formed as a plane layer for ground line. In addition, an inner layer ground circuit 16E and a dummy connection surface 16D extending from a power supply through hole 36THp are formed on the surface side inside the multilayer core substrate, and a power supply circuit Bp and a ground through hole are formed on the back surface. 36THE began to extend the splice end 16D. The so-called dummy end surface is a conductor circuit extending from a through hole, which means a wiring pattern that does not conduct other wiring in the same layer or a wiring pattern that is electrically connected to the same potential (16DI in Figure 36 (A)) . The upper ground circuit ι6Ε is formed as a ground plane layer, and the lower power circuit 16p is formed as a power plane layer. Fig. 36 (A) shows a cross section X4-X4 in Fig. 35, and Fig. 36 (B) shows a cross section χ5_χ5. Connection holes 36 for the front and back surfaces of the multilayer core substrate 30 are provided. The dummy end face 16D 2160-6825-PF; Ahddub 6 200529722 / is installed around the through hole 36 which is not connected to the ground circuit 16E and the power circuit 16P. Around the dummy end surface, it is used to ensure insulation between the dummy end surface and other wiring patterns (non-conductor forming portion (non-conductor forming portion drawing portion 35)). In addition, as shown in FIG. 36 (A), in a state where there are through holes of the same potential at adjacent positions, there is also a state where the dummy end faces 16DI formed on the periphery of these through holes are scraped. It is learned that in the multilayer printed circuit board of this structure, by making the ground circuit 16E, 16P of the multilayer core substrate 30 thicker, after the switch becomes 0N (on), a voltage drop of 1C occurs several times. It mainly improves the third voltage drop. However, it was found that there was no significant improvement in the first and second voltage drops. The second invention was completed in order to solve the aforementioned problems, and its object is to propose a multilayer printed circuit board capable of forming a 1C chip constituting a high-frequency region, particularly a printed circuit board or a package substrate that does not cause an erroneous operation or error even if it exceeds 3 GHz. . In particular, the first and second voltage drops among the voltage drops that occur after the switch becomes ON (on) are improved. [Means to Solve the Problem] [First Invention]

本發明人們係朝向前述目的之實現而全心地進行研究，結果，想 到至以下所示之内容成為要旨構造之第1發明。也就是說，第1發明 係一種多層印刷電路板，在芯基板上形成層間絕緣層和導體層而透過 導通孔來進行電氣連接’其特徵在於：怎基板之電源用或地線用導體 層之厚度和之至少一種係更加厚於層間絕緣層上之導體層之厚度。 也就是說，以芯基板作為多層芯基板，並非僅使得芯基板表背面 之導體層之厚度變厚，即使得各個導體層之厚度和變厚。在多層芯基 板之狀態下’分別足夠於芯基板之表背面之導體層和内層之導體層之 厚度係成為有助在對於1C之電源供應或其穩定化之厚度。在該狀態 下，表背面之導體層和内層之導體層係有電氣之連接，並且，適用在 2個部位以上之電氣連接時。也就是說，可以藉由進行多層化，使得 多層芯基板之各個導體層之厚度和變厚，使用芯之導體層，來作為電 源用導體層’而提南電源對於I c晶片之供應能力。此外，可以藉由使 用芯之導體層，來作為地線層，而減低對於1C晶片之訊號及重疊於電 2160-6825-PF;Ahddub 7 200529722 ·.源之雜訊’或者是在κ：穩定地供應電源。因此，在該多層印刷上 構裝1C晶片時，可以減低1C晶片〜基板〜電源為止之迴路 此，初期動作之電源不足變小，所以，不容易引起電源:因 即使是藉此而構裝高頻區域之1(:晶片，也不引起初期啟動之錯2作 或錯誤等。此外’減低雜訊，因此，不引起錯誤動作或錯誤。、 此外，可以藉由成為多層芯基板，而在仍然確保多層芯 體層之厚度和之狀態下，使得多層芯基板之各個導體層 導 也就是說，可以藉此，而即使是形成微細之配線圖案，也能^ ::顧間之絕緣間隔’因此，也能夠提供高絕緣可靠性之印: 作為其他效果係可以藉由使得芯基板之電_或地線 之厚度變厚而增加怒基板之強度，即使是藉此而使得芯基板 薄，也能夠藉由基板本身，來緩和彎曲或發生之應力。 3免 此外，也在經過1C晶片〜基板〜電容器或電源層〜電源而供 源至1C晶片之狀態下，達到同樣之效果。可以減低前述迴路"了^ 為這樣，在電容器或介電質層之電源供應，不造成損失。名 晶片係瞬間消耗電力而進行複雜之演算處理或動作。可以起來1c 層開始供應至1C晶片之電力供應，而即使是構裝高頻區=由曰電源 也對於初期動作之電源不足（所謂發生電壓下降之狀兄 Β曰片，The present inventors have made earnest studies in order to achieve the foregoing object, and as a result, they have thought that the following invention will become the first invention of the gist structure. In other words, the first invention is a multilayer printed circuit board. An interlayer insulating layer and a conductor layer are formed on a core substrate, and electrical connection is performed through a via hole. It is characterized by how the conductor layer of the substrate is used for power or ground. At least one of the thickness sum is thicker than the thickness of the conductor layer on the interlayer insulating layer. In other words, using a core substrate as a multilayer core substrate does not only make the thickness of the conductor layers on the front and back surfaces of the core substrate thicker, that is, the thickness and thickness of each conductor layer. In the state of the multi-layer core substrate, the thicknesses of the conductor layers on the front and back surfaces of the core substrate and the conductor layers on the inner layer are respectively sufficient to contribute to 1C power supply or its stabilization. In this state, the conductive layer on the front and back surfaces and the conductive layer on the inner layer are electrically connected, and are suitable for electrical connection at two or more locations. In other words, the thickness and thickness of each conductor layer of the multilayer core substrate can be increased by multi-layering, and the conductor layer of the core can be used as the conductor layer for the power source. In addition, the conductor layer of the core can be used as the ground layer to reduce the signal to the 1C chip and overlap the electrical signal 2160-6825-PF; Ahddub 7 200529722 ·. Noise from the source 'or at κ: stable Ground supply power. Therefore, when a 1C wafer is configured on the multilayer printing, the circuit from 1C wafer to the substrate to the power source can be reduced. The power shortage in the initial operation is reduced, so it is not easy to cause a power source. 1 (: chip) in the frequency region does not cause initial operation errors or errors. In addition, it reduces noise, so it does not cause erroneous operations or errors. In addition, it can be used as a multilayer core substrate while still Ensuring the thickness and state of the multilayer core layer makes the conductor layers of the multilayer core substrate conductive, that is, it can be used, and even if a fine wiring pattern is formed, it can also ^: Gujian's insulation interval '. Able to provide high insulation reliability: As another effect, it can increase the strength of the substrate by making the thickness of the electrical substrate or ground wire of the core substrate thicker. Even if the core substrate is made thin by this, it can also be used by The substrate itself is used to ease the bending or stress. 3 Exemption In addition, the same can be achieved in the state where the power is supplied to the 1C wafer through the 1C wafer ~ the substrate ~ the capacitor or the power supply layer ~. The effect can be reduced. In this way, the power supply in the capacitor or the dielectric layer is not lost. Famous chips consume power instantly and perform complex calculations or operations. It can be started up at the 1c layer. The power supply to the 1C chip, and even if the high-frequency region is configured, the power supply is insufficient for the initial operation (the so-called voltage drop occurs. Brother B,

之電容器，來進行電源之供應。說起來由於使用高頻區域= 冓ϋ量 因此，發生初期動作時之電源不足（電壓下降），但H片， 晶片，足夠於構|之電容器或内藏之介電質層之電=’。在低頻率之1C 特別是在使用作為芯基板電源層之導體層 板之單面或兩面上之層間絕緣層上之導體層之厚度；： 效果成為最大限度。該狀態下之所謂層間絕緣屉 j ^使侍别述 層印刷電路板之增層部之層間絕緣層上之導體;導3體層係所謂增 成為圖8中之58、158)。 日°疋本案的話、則 芯基板之電源層係可以配置在基板之表層、 配置在基板之表面、背面、内層之内之至少丨屉:，/、兩邊。可以 在内層之狀態下’涵蓋於2層以上而成為多層::可= 戔留 2160-6825-PF；Ahddub 8 200529722 成為地線層。在基本上’如果芯基板之電源料 . 於層間絕緣層之導體層的話，則具有其效果。最好加厚 和地線，之導體層呈交互地進行配置係用以改善電氣特性。導體層 但是，最好是形成於内層。在形成於内層時， 或電容器間之中間，配置電源層。因此，由於雙方之距：二:端 妨礙之原因變少，抑制電源之不足之緣故。 勺， 緣声二ΐίΠ塞:種，印刷電路板係在芯基板上形成層間絕 緣層和導體層而透過導通孔來進行電氣連接之多層印刷電路板， 基板之電源用導體層之厚度和成為α卜層間絕緣層 上之導體層之厚度成為α2時，成為α2<α1$40α2。 在2之狀態下，完全沒有對於電源不足之效果。也就是 ΐ接相對於初期動作時之所發生之電壓下降而抑制其下降 度係變得不明確。 在即使疋超過al>4Ga2之狀態也進行檢討時，基板厚度變厚， 因此，相反地，成為在對於IC之電源供應時而需要時間之結果。也就 疋說可以理解成為本案效果之臨界點。即使是成為這個以上之厚度， 也無法要求電氣效果之提升。此外，在超過該厚度時，在芯基板之表 層形成導體層之狀態下，在用⑽成芯基板和進行連接之接端面等， 發生困難。此外，在形成上層之層間絕緣層時，凹凸變大，在層間絕 緣層’產生起伏，因此，無法整合阻抗。但是，即使是該範圍⑷〉40 α 2)，也沒有問題時發生。 夕層心基板之電源用導體層之厚度和“丨係更加理想是1·2α2< α1$40α 2。確認：如果是該範圍的話，則不發生由於電源不足（電壓 下降）所造成之1C晶片之錯誤動作或錯誤等。 該狀態下之所謂芯基板係指使用：玻璃環氧樹脂等含浸在芯材之 Μ月曰基板、陶瓷基板、金屬基板、複合著樹脂、陶兗和金屬所使用之 複合芯基板、在這些基板之内層設置導體層之基板、形成3層以上之 多層化之導體層之多層芯基板等。 為了使得多層芯基板之電源用導體層之厚度和變厚，因此，可以 使用在埋入金屬之基板上藉由電鍍、濺鍍等之一般進行之形成導體層 2160>6825-PF;Ahddub 9 200529722 - 之印刷電路板之方法所形成者。 镑μ俨t本t明道一種多層印刷電路板係在芯基板上形成層間絕 在：二ί严通孔來進行電氣連接之多層印刷電路板，其特 ίί:體之?線用導體層之厚度和成為W、層間絕緣層 ί “3和“2係似3_2。可以藉 由成為該靶圍而減低重疊在對於IC晶片之 夠穩定地進行對於1C之電源供庳。此外，Μ。^雜訊此外月b 之範圍時，增加其效果。應此外，在成為 此外’藉由相同厚度之材料所形成，因此，如果是層積之多 :電:=1定義具有電源層來作為印刷基板之導體層之層或基 此外，多層s基板係在内層具有相 對薄之導體層，内層之導體層係主 ; 用之導體層（所謂相對厚、相對薄传此h =導層或線 得相對厚，表層係指其相反。）。但是，:在^較於”他導體層時而變 為電源用或者是地線用之導體層，I ’可以使用表層之導體層，來作 源用層，使用其他面’來作為地線二:=7面’來作為電 為芯之平坦性。所以，在層間絕導=，因此，得到作 是在多層芯基板之表層配置薄導體層1體日’並*、、、產生起伏。即使 厚度，來確保充分之導體層之厚度⑽能夠以足夠於内層導體層之 這些來作為電源層用之導體層或地喙導體層。可以藉由使用 路板之電氣特性。 用之導體層’而改善多層印刷電 最好是在成為多層芯基板時，内爲 相對地變厚，並且，使用作為電源層：：體得導體層之厚度 而達到前述之電源強化。兔線之狀態發生。可以藉由該構造 此外，可以藉由在芯基板内，配置導體層和導體層間之訊號線而 2160-6825-PF；Ahddub 10 200529722 - 形成微型帶構造，因此，能夠降低電感，得到阻抗之整合。因此，可 以使得電氣特性也進行穩定化。此外’成為表層之導體層相對地變薄 之更加理想之構造。芯基板係可以使得通孔間距成為600 /z m以下。 最好是多層芯基板係適合在呈電氣隔絕之金屬板之兩面，介在樹 脂層，内層之導體層係還在該内層之導體層之外側，介在樹脂層，形 成表面之導體層所構成。可以藉由在中央部’配置呈電氣隔絕之金屬 板，而確保充分之機械強度。此外，藉由在金屬板之兩面，介在樹脂 層，使得内層之導體層，還在該内層之導體層之外側，介在樹脂層， 形成表面之導體層，而在金屬板之兩面，具有對稱性，在熱循環等， 防止彎曲、起伏之發生。 © 多層芯基板係可以在36合金或42合金等之低熱膨脹係數之金屬 板之兩面，介在絕緣層，使得内層之導體層，還在該内層之導體層之 外側，介在絕緣層，形成表面之導體層。可以藉由在中央部，配置呈 電氣隔絕之金屬板，而使得多層印刷電路板之X一Y方向之熱膨脹係 數，來接近1C之熱膨脹係數，提高在1c和多層印刷電路板之連接部 之樹脂層之局部加熱循環性。此外，可以藉由在金屬板之兩面，介在 絕緣層，還使得内層之導體層，在該内層之導體層之外側，介在絕緣 層，形成表面之導體層，而在金屬板之兩面，具有對稱性，在加熱循 環等，防止彎曲、起伏之發生。 圖10係在縱軸，顯示1C晶片之電壓，在橫軸，顯示時間緩過。 ®圖10係以不具備構裝1GHz以上之高頻IC晶片之電源供應用之電容器 之印刷電路板，來作為模型。線A係顯示1GHz之1C晶片之電壓缝時 變化，線B係顯示3GHz之1C晶片之電壓經時變化。在該圖，顯示在 開關成為0N(導通）後而在發生複數次之電壓下降内之第3次之電壓下 降。該經時變化係在開始啟動晶片時，瞬間需要大量之電源。在讀 供應變得不足時，下降電壓（X點、X，點）。然後，供應之電源係遂辦 地變得充足，因此，消除電壓之下降。但是，在電壓下降時，容易弓丨 起1C晶片之錯誤動作或錯誤。也就是說，成為由於電源之供應不足所 造成之1C晶片之功能無法充分地發揮功能及啟動而引起之意外。讀電 源不足（電壓下降）係隨著1C晶片之頻率增加而變大。因此，為了消除 2l60-6825-PF;Ahddub 11 200529722 日下降，所以，花費時間’進行要求之功能、啟動，結果，產生 為了補充前述之電源不足（電屢下降），因此 部之電容器，釋出該雷衮罘内夕％抑态夕φ、店 符田運接於外 壓下降變小。/電谷㈣之所儲存之電源，而使得電源不足或電 在圖11，以具備電容器之印刷基板，來作為模型。線 電容^電容器而顯示腿之ic晶月之電屢經時變化。在比起播 裝電容器之線A時，電堡下降之程度變小。此外，線^”、冓 所進行者還構裝更大電容之電容器而相同於線e來顯線c 外，即使是比較於線c，也使得電麼下降之程度變小。;^^化。此 知要求之1C晶片也進行功能及啟動。但是，正如圖工一曰此而使 晶片成為更高之高頻區域，需要更多之電容器容量，不，、使得1C 電容器所構裝之區域，所以，不容易確保電壓，無法提言必須叹定 並且，即使是所謂高密度化之方面，也變得困難。** 及功月b， 將在使得多層芯基板之電源用導體層之厚度和成為α 層上之導體層之厚度成為α2而改變α1/α2時之電壓、、下、層間絕緣 示在圖12中之圖形。在圖12中，線c係構裝小電容之電容Μ之狀態，顯 之1C晶片來顯示α 1= α 2之電壓之經時變化。此外，器而以1GHz 電容之電容器而以1GHz之1C晶片來顯示α1 = 1·5α2之1"係構裝小 變化，線Ε係構裝小電容之電容器而以…此之IC晶片來•暴電壓之經時 α 2之電壓之經時變化。隨著芯之導體層之厚度:變厚1 = 2· 〇 不足或電壓之下降。因此，可以說是所謂Ic晶片之功能、減小電源之 之發生變少。藉由使得芯基板之電源用導體層之厚度動作之意外 體層之體積。在增加體積時，減低導體之電阻，因此，厚而増力口導 之電源之電壓、電流之損失。因此，在1C晶片〜電源間”無斟於傳達 小，進行電源之供應，因此，並無引起錯誤動作或錯^等傳達損失變 下，特別是藉著由於電源用導體層之厚度和所造成^要因二在該狀態 芯基板之電源用導體層之厚度和更加厚於層間絕緣層上之變大，使得 度，而達到其效果。 導體層之厚 此外，即使是在芯基板内而内藏電容器或介電質層、 電 、曰電 2160-6825-PF；Ahddub 12 200529722 / 子零件之基板，也顯著地顯示其效果。可以藉由進行内藏而縮短ic 晶片和電容器或介電質層間之距離。因此，可以減低迴路電感。能夠 使得電源不足或電壓下降變小。例如即使是在内藏電容器或介電質層 之芯基板，也可以藉由使得芯基板之導體層及電源層之導體層之厚度 更加厚於層間絕緣層上之導體層厚度，而滅少主要電源和内藏之電容 器或介電質層之電源間之兩者之導體電阻，因此，能夠減低傳達之損 失’來更加發揮内藏電容器之基板之效果。 芯基板之材料係成為樹脂基板而進行檢證，但是，得知即使是陶 瓷、金屬芯基板也達到同樣之效果。此外，導體層之材質係也藉著由 銅所構成之金屬而進行，但是，無法確認所謂即使是其他金屬也抵銷 魯效果來增加錯誤動作或錯誤之發生，因此，認為在芯基板之材料不同 或者是形成導體層之材質不同，並無其效果之影響。更加希望的是芯 基板之導體層和層間絕緣層之導體層係藉由相同金屬而形成。電氣特 性、熱膨脹係數等之特性或物性並無改變，因此，達到本案之效果。 [第1發明之效果] 可以藉由第1發明而減低IC晶片〜基板〜電源之導體之電阻，減 低傳達之損失。因此，傳達之訊號或電源係發揮要求之能力。所以， 為了使得1C晶片之功能、動作等係正常地進行動作，因此，並無發生 錯誤動作或錯誤。能夠減低1C晶片〜基板〜地線之導體之電阻，可以 減輕在訊號線、電源線之雜訊之重疊，防土錯誤動作或錯誤。 ® 此外，也得知：藉由第1發明而使得發生於1C晶片之初期啟動時 之電源不足（電壓下降）之程度變小；得知即使是構裝高頻區域之1C 晶片、特別是3GHz以上之IC晶片，也 < 以毫無問題地進行啟動。因 此’也可以提高電氣特性或電氣連接性。 接著，可以藉由使得芯基板成為多層化，使得導體層之厚度和變 厚’而成為也具有良好之絕緣可靠性之印刷電路板。 此外，可以比起習知之印刷電路板，來使得在印刷基板之電路内 之電阻變得更加小。因此，即使是附加偏壓，進行在高溫高濕度下之 所進行之可靠性試驗（高溫高濕度偏壓試驗），也使得破壞之間變 長，所以，也可以提高可靠性。 216 0 - 6 82 5Ahddub 13 200529722 /曰此，，由於使得電源用導體層之電阻變低，因此，即使是流動多 1之電軋，也抑制發熱。也相同於地線層。即使是在該方面，也不容 易發生錯誤動作，使得Ic構裝後之印刷電路板之可靠性變高。 [第2發明] 扣作為第2發明係本發明人們朝向前述目的之實現而全心地進行研 九〜果心到至以下所示之内容成為要旨構造之第1發明。也就是 說’第2發明係以在具備連接表面和背面之複數個通孔並且具有表面 和背面之導體層及内層之導體層之3層以上之多層芯基板上形成層間 絕緣層和導體層㈣過導通孔來進行電氣連接之多層印刷電路板，盆 特徵在於：前述複數個通孔係由呈電氣地連接於1(：晶片之電源電路:戈 肇地線電路或者是訊號電路之許多電源用通孔和許多地線用通孔及許多 訊號用通輯構成，前述電源用通孔係在貫衫層芯基板内層之 用導體層之際，使得許多電源用通孔内之至少1C正下方或70%以上之 電源用通孔，在地線用導體層，不具有由電源用通孔開始延出之導體 電路及/或前述地線用通㈣在貫通乡層絲板内層之電㈣導體層 之際，使得許多地線用通孔内之至少1(：正下方或7〇%以上之地線用^ 孔，在電源用導體層，不具有由地線用通孔開始延出之導體 作為技術特徵。 $ 但是，並不需要使得1C正下方之全部通孔成為前述特 可以在一部分之通孔，適用本發明。 、孔， • 也就是說，一種印刷電路板係以在具備連接表面和背面之複數個 通孔並且具有表面和背面之導體層及内層之導體層之3層以上之多層 芯基板上形成層間絕緣層和導體層而透過導通孔來進行電氣連接之多 層印刷電路板，其特徵在於：前述複數個通孔係由呈電氣地連接於ic 晶片之電源電路或地線電路或者是訊號電路之許多電源用通孔和許多 地線用通孔及許多訊號用通孔所構成，前述電源用通孔係在貫通多層 芯基板内層之地線用導體層之際，使得許多電源用通孔内之Ic正下方 之一部分之電源用通孔，在地線用導體層，不具有由電源用通孔開始 延出之導體電路，前述地線用通孔係在貫通多層芯基板内層之電源用° 導體層之際，使得許多地線用通孔内之IC正下方之一部分之地線用通 2160-6825-PF;Ahddub 14 200529722 孔，在電源用導體層，不具有由地線用通孔開始延出之導體電路，， 作為技術特徵。 此外，以在地線用導體層之不具有由電源用通孔開始延出之導體 電路之電源料孔和在電源科體層之*具㈣地線用通孔開始 ，導體電路之地線用通孔係呈格子狀或千鳥狀地進行配置，來作為 徵。在該狀態下，電源用通孔和地線用通孔係交互地進行位處。 以下，將在地線用導體層之不具有由電源用通孔開始延出之導 電路之電源用通孔，稱為不具有假接端面之電源用通孔，將在電源用 導體層之不具有由地線魏關始延出之導體電路之地線用通孔 為不具有假接端面之地線用通孔，僅稱為不具有假接端面之通孔。 此外，以多層芯基板之電源用導體層之厚度和α1相對於層 緣層上之導體層之厚度W而成為a2<ak40a2，來作為技術特徵 此外’以多層芯基板之地線用導體層之厚度和α3相對於層 緣層上之導體層之厚度α 2而成為40 〇：2,來作為技術特科 [第2發明之效果] 、风。 在第2發明，在電源用或/及地線用通孔中之1(：正下方或7 上之通孔係在多層芯基板之内層不具有假接端面。 0以 、作為第2發明之第1效果係使得通孔間隔成為窄間距，因此，处 夠進行微細化。可以藉此而進行印刷電路板之小型化。 吨 作為第2效果係能夠使得電源用通孔和地線用通孔間之間隔 狹窄，因此，可以減少相互電感。所以，由於Ic初期動作之第丨，得 第2次之電源下降所造成之電源不足變小。不容易引起電源不足^和 使是藉此而構裝高頻區域之IC晶片，也不容易y起初期啟動之鉍^即 作或錯誤等。 動 作為第3效果係使得在IC電晶體來供應電源之配線長度變耘， 此，不容易引起1C之電壓下降。相對於此，在具有假接端面之多爲 刷電路板，使得在1C電晶體來供應電源之配線長度變長。為何如^印 由於電氣係谷易流動在導體之表面，因此，在具有假接端面之狀陳 之配線長度係在通孔之配線長度加入假接端面之表面之配線長度之下 故。 緣 2160-6825-PF;Ahddub 15 200529722 - 即使不具有假接端面之通孔成為ic正下方之一部分，也得到同樣 之效果。為何如此，由於電氣係優先地流動在電阻小之配線，因此， 即使不具有假接端面之通孔成為一部分，也可以經由不具有假接端面 之通孔，在1C電晶體來供應電源之緣故。但是，不具有假接端面之電 源用通孔和地線用通孔係最好是分別對於全電源用通孔、全地線用通 孔而個別成為30%以上、更加理想是50%以上。在不具有假接端面之通 孔數目變少時，在此種通孔集中電氣，因此，本發明之效果變小。 此外，不具有假接端面之電源用通孔和不具有假接端面之地線用 通孔係最好是呈格子狀或千鳥狀地進行配置。在該狀態下，更加理想 是交互地進行配置。為何如此，由於相互電感減少，因此，在短時間， φ 進行對於1C電晶體之電源供應之緣故。 作為第4效果係可以使得多層芯之内層之電源層或地線層之導體 面積變多，因此，兩導體層之導體電阻變小，結果，順暢地進行對於 IC電晶體之電源供應。為何如此，由於沒有假接端面，因此，可以更 加接近通孔而形成電源層或地線層之緣故（參考圖37)。在比較圖37 中之通孔之V周邊和W周邊時，在W並無假接端面，因此，可以接近 於通孔而形成導體層，結果，比起V周邊，還形成更多之導體層。 由以上之結果而得知：即使是同時進行開關，如果也藉由本發明 之多層印刷電路板的話，則1C電晶體不容易成為電源不足，不容易發 生錯誤動作。 • 此外，最好是使得多層芯基板之表面和背面之導體層及内層之導 體層間之厚度變厚、特別是内層之導體層之厚度變厚。 作為該效果係可以藉由使得導體層變厚而增加導體本身之體積。 可以藉由增加其體積而減低在導體之電阻。因此，藉由使用導體層來 作為電源層而提尚電源對於I c晶片之供應能力。此外，可以藉由使用 導體層來作為地線層而減低重疊在對於Ic晶片之訊號及電源之雜 訊。因此，可以在該印刷電路板構裝Ic晶片時，減低IC晶片〜基板 〜電源為止之電感’成夠主要改善初期動作之第3次電壓下降。此外， 正如圖34所示，電位相反之通孔和導體層呈對向之部分之面積（對向 面積）和距離增大，同時，兩者呈接近，因此，更加減低第丨次和第2 2160-6825-PF；Ahddub 16 200529722 次之電壓下降。通孔係不具有假接端面，因此，例如不具有假接端面 之電源用通孔和相反電位之地線層間之距離呈接近。此外，地線層變 厚，因此，使得電源用通孔和地線層呈對向之距離變長。所以，比起 成為不具有假接端面之多層印刷電路板，還可以更加改善電壓之下 降。作為圖34所示之X距離係最好是15〜150//m。在成為15#m以 下時，降低絕緣可靠性。另一方面，在超過15〇//m時，使得改善電壓 下降之效果變小。 像這樣，在通孔貫通多層芯基板之具有其他電位之内層時，在IC 正下方或70%以上之通孔’不設置假接端面，可以藉由使得導體層變 厚，而改善發生於初期動作時之主要之電壓下降（由第丨次開始至第3 •次之電壓下降）。因此，即使是在該印刷電路板構裝高頻之IC晶片， 也不引起初期啟動之錯誤動作或錯誤等。 不具有假接端面之通孔係即使是在Ic正下方，成為一部分，也得 到相同之效果。 在内層並m假接端面之多層芯構造係特別使得内層之導體厚 度=厚於多層芯基板之表背面之導體厚度，有效於確保芯之導體層 =厚度和⑷）之狀態。其理由係由於在表f面之導體層，必須有用以 付到呈電氣地連接在形成於其上面之增層之之Capacitor to supply power. Speaking of the use of high-frequency region = volume, the power supply during the initial operation is insufficient (voltage drop), but the H chip, chip is enough to build the capacitor or built-in dielectric layer of electricity = '. 1C at low frequencies, especially the thickness of the conductor layer on one or both sides of the interlayer insulation layer used as the conductor layer of the core substrate power supply layer: The effect is maximized. In this state, the so-called inter-layer insulation drawer ^ enables the conductors on the inter-layer insulation layer of the layer-increasing part of the printed circuit board; the conductor layer is so-called increased to 58 and 158 in FIG. 8). In the case of this case, the power supply layer of the core substrate can be arranged on the surface layer of the substrate, on the surface, the back surface, and the inner layer of the substrate, at least, on both sides. In the state of the inner layer, it can cover more than 2 layers and become a multi-layer :: may = retention 2160-6825-PF; Ahddub 8 200529722 becomes the ground layer. Basically, if the power supply material of the core substrate is on the conductor layer of the interlayer insulation layer, it has its effect. It is best to thicken and ground, and the conductor layers are arranged interactively to improve the electrical characteristics. Conductor layer However, it is preferably formed on the inner layer. When formed on the inner layer or between capacitors, a power supply layer is arranged. Therefore, due to the distance between the two sides: two: the reason for the hindrance is reduced, and the lack of power is suppressed. Scoop, edge sound: a kind of multilayer printed circuit board in which a printed circuit board forms an interlayer insulating layer and a conductor layer on a core substrate and is electrically connected through a via hole, and the thickness of the conductor layer of the substrate is When the thickness of the conductor layer on the interlayer insulating layer becomes α2, it becomes α2 < α1 $ 40α2. In the state of 2, there is no effect on power shortage at all. In other words, it is not clear how much the connection is suppressed from the voltage drop that occurs during the initial operation. When the state is reviewed even when 疋 exceeds al > 4Ga2, the thickness of the substrate becomes thicker, and conversely, it takes a time to supply power to the IC. That is to say, it can be understood as the critical point of the effect of this case. Even if the thickness is more than this, the improvement of the electrical effect cannot be demanded. In addition, when the thickness is exceeded, it becomes difficult to form a core substrate by using a conductive layer on the surface layer of the core substrate and to make a connection end surface for connection. In addition, when the upper interlayer insulating layer is formed, the unevenness becomes large, and undulations occur in the interlayer insulating layer '. Therefore, the impedance cannot be integrated. However, even in this range ⑷> 40 α 2), no problem occurred. The thickness and the thickness of the conductor layer for the power supply substrate of the core substrate are more preferably 1 · 2α2 < α1 $ 40α 2. Confirm that if it is within this range, the 1C chip due to insufficient power supply (voltage drop) will not occur. Wrong operation or error, etc. The so-called core substrate in this state refers to the use: glass epoxy resin and other substrates impregnated with the core material, ceramic substrates, metal substrates, composite resin, ceramics, and metal. Composite core substrates, substrates in which conductor layers are provided on the inner layers of these substrates, multilayer core substrates forming three or more multilayered conductor layers, etc. In order to increase the thickness and thickness of the conductor layers for power supply of multilayer core substrates, it is possible to It is formed by using a method of forming a conductor layer 2160 >6825-PF; Ahddub 9 200529722-a printed circuit board which is generally performed on a substrate embedded in metal by electroplating, sputtering, or the like. A multilayer printed circuit board is a multilayer printed circuit board that forms an interlayer insulation on a core substrate: two rigorous through holes for electrical connection. Its special feature is the thickness and composition of the conductor layer for the body wire. W, interlayer insulation layer "3 and" 2 series is similar to 3_2. It can reduce the overlap by becoming the target range. For IC chips, the supply of power to 1C can be stably performed. In addition, M. ^ Noise and other months The range of b increases the effect. In addition, it should be formed by materials of the same thickness. Therefore, if there are as many layers as possible: electricity: = 1 defines a power supply layer as the conductor layer of the printed substrate. In addition, the multilayer s substrate has a relatively thin conductive layer on the inner layer, and the inner conductive layer is the main layer; the used conductive layer (the so-called relatively thick, relatively thin) h = the conductive layer or the wire is relatively thick, and the surface layer is It means the opposite.). However, when compared with "other conductor layers," it becomes a conductor layer for power or ground. I 'can use the surface conductor layer as the source layer and use other surfaces. 'Let's use the ground wire 2: = 7 plane' as the flatness of the electric core. Therefore, the interlayer insulation is =. Therefore, it is obtained that the thin conductor layer 1 is disposed on the surface layer of the multi-layered core substrate, and undulation occurs. Even if it is thick enough to ensure a sufficient thickness of the conductor layer, it is possible to use enough of the inner conductor layer as the conductor layer or the beak conductor layer for the power supply layer. You can use the electrical characteristics of the board. It is preferable to use the conductor layer 'to improve multilayer printed wiring. When the multilayer core substrate is formed, the inner layer is relatively thickened, and it is used as a power source layer: to obtain the thickness of the conductor layer to achieve the aforementioned power source strengthening. The state of the rabbit line occurs. This structure can also be used. In addition, the conductor layer and the signal line between the conductor layers can be arranged in the core substrate. 2160-6825-PF; Ahddub 10 200529722-Forms a micro-strip structure, so it can reduce inductance and get impedance integration . Therefore, the electrical characteristics can also be stabilized. In addition, it becomes a more desirable structure in which the surface conductor layer is relatively thin. The core substrate system can make the through-hole pitch be 600 / z m or less. Preferably, the multilayer core substrate is suitable for being formed on both sides of the metal plate which is electrically isolated, interposed between the resin layer, and the inner conductor layer is on the outer side of the inner conductor layer, interposed between the resin layer and the surface conductor layer. It is possible to ensure sufficient mechanical strength by arranging an electrically isolated metal plate at the center portion. In addition, the resin layer is interposed on both sides of the metal plate, so that the conductor layer of the inner layer is on the outside of the conductor layer of the inner layer, and the resin layer is formed on the resin layer to form a surface conductor layer. The two sides of the metal plate have symmetry. In order to prevent bending and undulation during thermal cycling, etc. © Multi-layer core substrate can be insulated on both sides of metal plates with low thermal expansion coefficients such as 36 alloy or 42 alloy, so that the inner conductor layer is outside the conductor layer of the inner layer and interposed between the insulation layer to form the surface. Conductor layer. The thermal expansion coefficient in the X-Y direction of the multilayer printed circuit board can be approached to the thermal expansion coefficient of 1C by arranging an electrically isolated metal plate in the central portion, and improving the resin at the connection portion of the 1c and the multilayer printed circuit board. Local heating cycle of the layer. In addition, the insulation layer on both sides of the metal plate can also be used to make the inner layer of the conductor layer. On the outside of the inner layer of the conductor layer, the insulation layer can be formed to form the surface conductor layer. On both sides of the metal plate, there is symmetry. It can prevent bending and undulation during heating cycle. Fig. 10 shows the voltage of the 1C wafer on the vertical axis, and the display time is slowed down on the horizontal axis. Figure 10 shows a model with a printed circuit board that does not have a capacitor for power supply for a high-frequency IC chip with a frequency of 1 GHz or higher. Line A shows the change in the voltage of the 1C wafer at 1GHz, and line B shows the change in the voltage of the 1C wafer at 3GHz over time. In this figure, after the switch becomes 0N (on), the voltage drop for the third time within a plurality of voltage drops occurs. This change over time requires a large amount of power instantaneously when the chip is started. When the read supply becomes insufficient, the voltage is dropped (point X, point X). Then, the power supply is sufficient, so the voltage drop is eliminated. However, when the voltage drops, it is easy to cause incorrect operation or error of the 1C chip. In other words, it is an accident caused by the insufficient function and activation of the 1C chip due to insufficient power supply. The insufficient read power (voltage drop) increases with the frequency of the 1C chip. Therefore, in order to eliminate the decline of 2l60-6825-PF; Ahddub 11 200529722, it took time to perform the required functions and start up. As a result, in order to supplement the aforementioned power shortage (repeated power reduction), the capacitors were released. The thunderbolt on the eve of the percent inhibition is φφ, and the store's Futianyun picks up when the external pressure decreases. / Electric Valley's stored power supply, so that the power supply is insufficient or electricity. In Figure 11, a printed circuit board with capacitors is used as a model. The line capacitance ^ capacitor shows the ic crystal moon's electricity of the leg changes over time. Compared with the line A where the capacitor is mounted, the degree of the electric descent decreases. In addition, the line ^ ", 冓 also constructed a capacitor with a larger capacitance and the same line e to display the line c, even if compared to the line c, it will make the degree of electrical decline smaller. ^^ 化The 1C chip required by this knowledge also performs functions and starts. However, as mentioned above, making the chip into a higher frequency region requires more capacitor capacity. No, the area where the 1C capacitor is constructed Therefore, it is not easy to ensure the voltage, it is impossible to say that it must be said, and even the so-called high-density aspect becomes difficult. ** and work month b, will make the thickness of the power conductor layer of the multilayer core substrate and The thickness of the conductor layer on the α layer becomes α2, and the voltage, lower, and interlayer insulation when changing α1 / α2 are shown in the graph in Fig. 12. In Fig. 12, the line c is the state where the capacitor M of the small capacitor is installed The 1C chip shows the time-dependent change of the voltage of α 1 = α 2. In addition, the capacitor with a 1GHz capacitor and the 1C chip with a 1GHz chip display α1 = 1 · 5α2 1 " Line E is a capacitor with small capacitance • The change of the voltage of the α 2 voltage over time. With the thickness of the core's conductor layer: thicker 1 = 2 · 0 is insufficient or the voltage drops. Therefore, it can be said that the function of the so-called IC chip is reduced. The occurrence of the power source is reduced. By making the thickness of the conductor layer of the core substrate the thickness of the unexpected body layer. When the volume is increased, the resistance of the conductor is reduced. Therefore, the voltage and current of the thick and strong power source Therefore, the transmission between 1C chip and the power supply is small, and the power supply is supplied. Therefore, there is no erroneous operation or error, and the transmission loss does not change, especially due to the thickness of the conductor layer for the power supply and The reason is that the thickness of the conductor layer for the power substrate of the core substrate in this state is thicker and thicker than that on the interlayer insulating layer, so that the degree is reached, and its effect is achieved. Thickness of the conductor layer In addition, even if a capacitor or a dielectric layer is built in the core substrate, the electric and electrical components are 2160-6825-PF; Ahddub 12 200529722 / Sub-component substrate, which shows its effect significantly. The distance between the IC chip and the capacitor or the dielectric layer can be shortened by performing built-in. Therefore, loop inductance can be reduced. It can make the power shortage or voltage drop smaller. For example, even a core substrate with a built-in capacitor or a dielectric layer, the thickness of the conductor layer of the core substrate and the conductor layer of the power source layer can be made thicker than the thickness of the conductor layer on the interlayer insulation layer, so that the thickness can be reduced. The resistance of the conductor between the main power supply and the built-in capacitor or the power supply of the dielectric layer can reduce the loss of transmission 'to further exert the effect of the substrate of the built-in capacitor. The material of the core substrate was verified as a resin substrate. However, it was found that the same effect was achieved even with ceramic and metal core substrates. In addition, the material of the conductor layer is also made of a metal made of copper. However, it cannot be confirmed that even other metals can offset the Lu effect and increase the occurrence of erroneous operations or errors. Therefore, it is considered that the material of the core substrate is Different or different materials forming the conductor layer have no effect on its effect. It is more desirable that the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer be formed of the same metal. The electrical characteristics, thermal expansion coefficient, and other characteristics or physical properties have not changed. Therefore, the effect of this case is achieved. [Effect of the first invention] According to the first invention, the resistance of the conductors of the IC chip to the substrate to the power source can be reduced, and the loss of transmission can be reduced. Therefore, the signal or power transmitted is capable of performing the required function. Therefore, in order to make the functions and operations of the 1C chip operate normally, no erroneous operation or error occurred. It can reduce the resistance of the conductors of 1C chip ~ substrate ~ ground wire, can reduce the overlap of noise on signal lines and power lines, and prevent soil malfunctions or errors. ® In addition, it was also found that the degree of power shortage (voltage drop) at the initial startup of the 1C chip was reduced by the first invention; it was also found that even the 1C chip with a high-frequency region, especially at 3 GHz The above IC chip is also activated with no problems. Therefore, it is also possible to improve electrical characteristics or electrical connectivity. Next, by making the core substrate multilayer, the thickness and thickness of the conductor layer can be made into a printed circuit board that also has good insulation reliability. In addition, the resistance in the circuit of the printed circuit board can be made smaller than that of the conventional printed circuit board. Therefore, even if the bias voltage is applied and the reliability test (high temperature and high humidity bias test) is performed under high temperature and high humidity, the breakage lengthens, so the reliability can be improved. 216 0-6 82 5Ahddub 13 200529722 / This means that the electric resistance of the power supply conductor layer is reduced, so that even in the case of electric rolling with a large flow, heat generation is suppressed. It is also the same as the ground plane. Even in this respect, erroneous operation is not easy to occur, which makes the reliability of the printed circuit board after the IC is mounted high. [Second invention] As the second invention, the present inventors have devoted themselves to the realization of the aforementioned object. The first invention, which has the gist structure to the content shown below, is described below. That is, the "second invention" is to form an interlayer insulation layer and a conductor layer on a multilayer core substrate having a plurality of through holes connecting the front and back surfaces and having three or more conductor layers on the front and back surfaces and the inner conductor layer. A multilayer printed circuit board for conducting electrical connections through vias, the basin is characterized in that the aforementioned plurality of through-holes are electrically connected to 1 (: power circuit of the chip: Ge Zhao ground wire circuit or many power sources for signal circuits Through-holes and through-holes for many ground wires and many signal-throughs are used. The aforementioned power-supply through-holes are located at the conductor layer on the inner layer of the core substrate of the shirt. 70% or more of the power supply through-holes do not have a conductor circuit extending from the power supply through-holes in the ground conductor layer and / or the above-mentioned ground conductor through the electrical conductor layer that penetrates the inner layer of the rural wire board At this time, at least 1 (: directly below or 70% or more of the ground wire through holes in many ground wire through holes, and the conductor layer for power supply does not have a conductor extending from the ground wire through hole as Technical characteristics. It is not necessary to make all through holes directly below 1C into the aforementioned through holes that can be part of the above, and to apply the present invention. Holes, that is, a printed circuit board is provided with a plurality of through holes having a connecting surface and a back surface. A multilayer printed circuit board in which an interlayer insulating layer and a conductor layer are formed on a multilayer core substrate having three or more layers of a conductor layer on the front and back and an inner conductor layer and electrically connected through a via hole, wherein: Each through hole is composed of a power supply circuit or a ground circuit that is electrically connected to the IC chip, or a plurality of power supply through holes, a plurality of ground through holes, and a plurality of signal through holes. When the ground wire conductor layer penetrates the inner layer of the multilayer core substrate, a part of the power supply through hole directly below Ic in many power supply through holes is not included in the ground wire conductor layer. In the extended conductor circuit, the aforementioned through-holes for ground wires are located below the ICs in the through-holes for the power supply through the inner layer of the multi-layer core substrate, so that many of the through-holes for ground wires are directly below the IC. Part of the ground wire is through 2160-6825-PF; Ahddub 14 200529722 hole, in the power conductor layer, does not have a conductor circuit extending from the ground wire through hole as a technical feature. In addition, it is used for ground wire The conductor layer does not have the power supply hole of the conductor circuit that extends from the power supply through hole and the ground wire through hole in the power supply body layer. The ground line through hole of the conductor circuit is in the shape of a grid or a thousand birds. In this state, the through-holes for the power supply and the through-holes for the ground line are alternately positioned. In the following, the absence of the conductor layer for the ground line starts from the through-holes for the power supply. The power supply through hole of the lead circuit is called a power supply through hole without a dummy end surface. The ground wire through hole in the power supply conductor layer without the conductor circuit extending from the ground wire Weiguan is A through-hole for a ground wire without a dummy end face is simply called a through-hole without a dummy end face. In addition, the thickness of the power conductor layer of the multilayer core substrate and α1 relative to the thickness of the conductor layer on the edge layer W are a2 < ak40a2 as technical features. The thickness and α3 are 40: 2 with respect to the thickness α 2 of the conductive layer on the edge layer, and are used as a technical specialty [effect of the second invention] and wind. In the second invention, one of the through holes for the power supply or / and the ground wire (1 :: The through holes directly below or 7 are in the inner layer of the multilayer core substrate and do not have a dummy end surface. 0, as the second invention The first effect is to narrow the pitch of the through holes, so it can be miniaturized. This can reduce the size of the printed circuit board. As a second effect, the power supply vias and ground vias can be used. The interval between them is narrow, so that mutual inductance can be reduced. Therefore, due to the first operation of Ic, the power shortage caused by the second power drop is reduced. It is not easy to cause power shortage ^ It is not easy to install the IC chip in the high-frequency region to start the bismuth at the initial startup, or to make mistakes. The third effect is to make the length of the wiring for supplying power to the IC transistor harder. This does not easily cause 1C. The voltage drops. In contrast, brushed circuit boards are used in many cases with fake end faces, which makes the length of the wiring for supplying power to the 1C transistor longer. Why is the printing printed on the surface of the conductor because of the electrical system valley? , With a fake end The wiring length of the surface is below the wiring length of the through hole plus the wiring length of the surface of the dummy end surface. Edge 2160-6825-PF; Ahddub 15 200529722-Even if the through hole without the dummy end surface becomes ic positive The same effect is also obtained in the lower part. Because of this, the electrical system preferentially flows on the wiring with low resistance, so even if a through-hole without a dummy end surface becomes a part, it can pass through a through-hole without a dummy end surface. The reason is that the 1C transistor is used to supply power. However, the through-holes for power and ground through-holes that do not have false end faces are preferably individually used for all-power through-holes and all-ground through-holes. 30% or more, and more preferably 50% or more. When the number of through-holes without dummy end faces is reduced, electricity is concentrated in such through-holes, and therefore, the effect of the present invention is reduced. In addition, without the dummy end faces, It is best to arrange the power supply through-holes and ground wire through-hole systems without a dummy end surface. In this state, it is more ideal to arrange them interactively. Why? The mutual inductance is reduced. Therefore, in a short period of time, φ supplies power to the 1C transistor. As a fourth effect, the area of the power supply layer or the ground layer of the inner core of the multilayer core can be increased. Therefore, the two conductors The conductor resistance of the layer becomes smaller, and as a result, the power supply to the IC transistor is smoothly performed. Why? Because there is no dummy end surface, the power layer or ground layer can be formed closer to the through hole (refer to Figure 37). ). When comparing the V-periphery and W-peripheral of the through-hole in FIG. 37, there is no false end surface at W, so the conductor layer can be formed close to the through-hole, and as a result, more than Conductor layer. From the above results, it is known that even if the switching is performed at the same time, if the multilayer printed circuit board of the present invention is used, the 1C transistor will not easily become insufficient in power supply and will not easily malfunction. • In addition, it is better to increase the thickness between the conductor layers on the front and back of the multilayer core substrate and the conductor layers on the inner layer, especially the thickness of the conductor layer on the inner layer. The effect is to increase the volume of the conductor by making the conductor layer thicker. The resistance in the conductor can be reduced by increasing its volume. Therefore, by using the conductor layer as the power source layer, the power supply capacity of the IC chip is improved. In addition, by using a conductor layer as a ground layer, it is possible to reduce the noise that is superimposed on the signal and power of the IC chip. Therefore, when the IC chip is mounted on the printed circuit board, the inductance from the IC chip to the substrate to the power source can be reduced to sufficiently improve the third voltage drop in the initial operation. In addition, as shown in FIG. 34, the area (opposite area) and distance between the through-hole and the conductor layer facing each other with opposite potentials increase, and at the same time, the two are close, so the first and second times are further reduced. 2160-6825-PF; Ahddub 16 200529722 voltage drops. The through-hole system does not have a dummy end surface. Therefore, for example, the distance between the power supply through-hole without the dummy end surface and the ground layer of the opposite potential is close. In addition, the ground layer becomes thicker, so that the distance between the power supply via and the ground layer becomes longer. Therefore, the voltage drop can be improved more than a multilayer printed circuit board without a dummy end surface. The X distance shown in FIG. 34 is preferably 15 to 150 // m. When it is 15 # m or less, the insulation reliability is reduced. On the other hand, when it exceeds 15 // m, the effect of improving the voltage drop becomes small. In this way, when the through-hole penetrates the inner layer of the multilayer core substrate with other potentials, no dummy end surface is provided in the through-holes directly below the IC or above 70%, and the improvement can occur in the initial stage by making the conductor layer thicker. The main voltage drop during operation (from the first time to the third voltage drop). Therefore, even if a high-frequency IC chip is mounted on the printed circuit board, it does not cause an erroneous operation or error in the initial startup. A through-hole system without a dummy end face has the same effect even if it is a part directly below Ic. The multi-layered core structure of the inner layer and the pseudo-joint end face particularly makes the thickness of the inner layer conductor thicker than the thickness of the front and back surfaces of the multi-layered core substrate, which is effective to ensure the state of the core conductor layer = thickness and ⑷). The reason for this is that the conductor layer on the surface f must be effective for electrically connecting the additional layers formed on it.

τ接端面或其他導想電路間之绝:可 之間之絕緣間隔變寬’结果’無法進行通孔 二匕吏：疒 使得多層芯基板之表背面之導體厚度變厚時在:=丄 面之層間絕緣層產生起伏，因此，無法進行阻抗整合。/成於”上 ，収夠於多層芯基板之表層之導體層和二 成為芯之導體層之厚度。在該狀態下，表層之 係有電氣之連接，並且，適用在2個部仿 ^内層之導體層 如果是銲塾、接端面程度之面積的話，則該面=連接時。此外， 非足夠之厚度。賴導體層料好是電^或㈣2體層之厚度係並 在該狀態下，可以是由3層（表層+内層 ^ 可以是3廣以上之多層芯基板。〜於需要二多=基 2160-6825-pp.Ahddub 17 200529722 板之内層埋入及形成電容器或介電質層、電阻等之零件之電子零件收 納多層芯基板。 此外，最好是在使得多層芯基板之内層之導體層變厚時，在IC 晶片之正下方，配置該導體層。可以藉由配置在IC晶片之正下方而使 得ic晶片和電源層間之距離成為最短，因此，能夠更加減低電感。所 以，成為更佳效率之電源供應，特別是消除第3次之電壓下降。在此 時，也最好是相對於多層芯基板之導體層之厚度和成為αΐ、層間絕緣 層上之導體層之厚度成為α2而成為α2<〇：1$4()α:2。 曰 使得多層芯基板之内層之導體層之厚度更加厚於層間絕緣層上之 導體層。可以藉此而即使是在多層芯基板之表面配置薄導體層，也利τ The connection between the end faces or other imaginary circuits: the insulation gap between them can be widened. 'Results' cannot be through-holes. Two: 疒 When the thickness of the conductor on the front and back surfaces of the multilayer core substrate is thickened: = 丄The interlayer insulation layer is undulated, so impedance integration cannot be performed. / 成 于 ", the thickness of the conductor layer of the surface layer of the multi-layer core substrate and the conductor layer of the two cores are obtained. In this state, the surface layer is electrically connected, and it is suitable to be used in two parts. If the conductor layer is the area of the solder joint and the end face, the surface = at the time of connection. In addition, the thickness is not sufficient. It depends on the thickness of the conductor layer or the thickness of the body layer in this state. It consists of 3 layers (surface layer + inner layer ^ can be a multi-layered core substrate with a thickness of 3 or more. ~ Need more than two == 2160-6825-pp.Ahddub 17 200529722 The inner layer of the board is embedded and forms a capacitor or a dielectric layer, a resistor Electronic components such as components store a multilayer core substrate. In addition, it is preferable to arrange the conductor layer directly below the IC chip when the conductor layer of the inner layer of the multilayer core substrate is thickened. It can be arranged on the IC chip. Directly below, the distance between the IC chip and the power supply layer is minimized, so that the inductance can be further reduced. Therefore, it becomes a more efficient power supply, especially to eliminate the third voltage drop. At this time, it is also better to be relatively to The thickness of the conductor layer of the multilayer core substrate becomes αΐ, and the thickness of the conductor layer on the interlayer insulating layer becomes α2 and becomes α2 < 0: 1 $ 4 () α: 2. This makes the thickness of the conductor layer of the inner layer of the multilayer core substrate more The conductor layer is thickened on the interlayer insulation layer. It can be used even if a thin conductor layer is arranged on the surface of the multilayer core substrate.

用足夠於内層變厚之導體$，確絲分之厚度，來作為芯之^體層。 也就是說，即使是供應大容量之電源，也_毫無問題地進行啟動， 因此’不引起錯誤動作或動作不良。在此時，也最好是㈣於多層怒 ，板，導體層之厚度和成為仏層間絕緣層上之導體層之厚度成為α 2 而成為 α2&lt;α1$40α2。 圖28係顯示由電源成為0Ν(導通）之瞬間開始之^電壓之時間變 2 =縱軸，，IC之電壓，在橫軸’顯示時間經過。圖Μ係以構 上之同頻IC晶片並且不具備電源用電容器之印刷電路板， 來作為模型。線B係顯示對於1GHz之Ic晶片之電壓經時變化，線a 不曰對於3GH^ IC晶片之電壓經時變化。該經時變化係在開始啟 日日片時瞬間需要大量之電源。在該供應變得不足時，下降電壓 (X點、X’，點：第1次之電壓下降）。然後，重複地進行—旦在電壓上 升後、還下降（第2次之電壓下降）並且在上升後、下降（第3次之電壓 下降）以後之變小之振幅，同時，電壓逐漸地上^但是，在電壓下降 時，容易弓丨起1C晶片之錯誤動作或錯誤。也就是說，成為由於電源之 供應不足所造成之1C晶片之杨無法充分地發揮功能及啟動而引起 之意外。該電源不足（電壓下降）係隨著1(：晶片之頻率增加而變大。因 此，為了消除電壓之下降，所以，花費時間，進行要求之功能、啟動， 結果，產生時滯。 圖29係顯示在習知構造之印刷電路板及本發明之印刷電路板構 18 2160-6825-PF；Ahddub 200529722 / 裝高頻之1C晶片時之1C電壓之時間變化。此外，1(:之電壓測定係無 法直接地進行測定，因此，在印刷電路板，形成能夠測定之測定電路。 A之多層芯（習知構造）係成為4層，全部之通孔具有假接端面，並且， 電源用之各層之導體厚度係全部相同而成為15 # m(芯基板之電源層 係2層、層間絕緣層上之導體厚度係3 〇 v in)。B之多層芯係相同於a 而成為4層，但是，在表層具有l5//m之電源用導體層，在内層具有 30/zm之電源用導體層，1C正下方之電源用通孔係在多層芯之内層之 地線層，不具有由電源用通孔開始延出之導體電路，1C正下方之地線 用通孔係在多層芯之内層之電源層，不具有由地線用通孔開始延出之 導體電路。C係在B之多層芯，使得内層之導體厚度成為75/zm。多層 •芯之導體層係交互地配置電源層和接地層。A、B、C係皆在前述多層 芯呈交互地增層著層間絕緣層和導體層之多層印刷電路板。由圖2g 而得知：藉由成為本發明之不具有由通孔開始延出之導體電路之多層 芯構造而改善第1次和第2次之電壓下降。因此，可以說是使得Ic 晶片之功能和動作之意外之發生變少。此外，得知藉由使得内層之導 體厚度變厚而還更加改善第1次和第2次之電壓下降。在内層電路之 厚度成為40〜150/zm之狀態下，也成為相同於75//m之同樣結果。 此外，在多層芯基板，即使是在多層芯基板之全部層之電源層之 導體層之厚度更加厚於層間絕緣層上之導體層之厚度時，即使是在多 層芯基板之全部層之電源層之導體層之厚度相同於層間絕緣層上之導 響體層之厚度或者是這個以下之時，也在使得足夠於全部層之導體厚度 之厚度總和更加厚於層間絕緣層上之導體層之厚度時，達到其效果。 【實施方式】 A·第1實施例 (第1實施例一 1) 參考圖1〜圖9而就本發明之第1實施例一1之多層印刷電路板， 來進行說明。 首先，就第1實施例一 1之多層印刷電路板10之構造而言，參考 圖8、圖9而進行說明。圖8係顯示該多層印刷電路板1〇之剖面圖， 2160-6825-PF；Ahddub 19 200529722 •-圖9係顯不在圖8所示之多層印刷電路板1()安裝IC晶片9()而載置至 標點器板94之狀態。正如圖8所示，在多層印刷電路板1〇，使用多 層芯基板30。在多層芯基板30之表面側，形成導體電路料、導體層 34P ’在背面，形成導體電路34、導體層34E。上層之導體層34p係形 成為電源用平面層，下側之導體層34E係形成為地線用平面層。此外， 在多層芯基板30内部之表面側，形成内層之導體電路16、導體層16E， 在背面，形成導體電路16、導體層16p。上層之導體層蘭係形成為 地線用平面層，下側之導體層16P係形成為電源用平面層。和電源用 平面層間之連接係藉由通孔或導通孔而進行。平面層係可以是僅單邊 之單層，也可以配置成為2層以上。最好是藉由2層〜4層所形成。 魯在5層以上，無法確認電氣特性之提升，因此，即使是成為這個以上 之多層，也使知其效果成為相同於4層之同樣程度。在内層成為5層 以上時ϋ板之厚度變厚，因此，相反地，也有電氣特性惡化之狀 態發生。特別是由於藉由2層所形成者係在所謂多層芯基板之剛性整 合之方面，使得基板之延伸率呈一致，因此，不容易出現f曲之緣故。 在多層芯基板30之中央，收納呈電氣隔絕之金屬板12。（該金屬板12 係也發揮作為芯材之功能，但是，並無進行通孔或導通孔等之電氣連 接。主要是提高對於基板彎曲之剛性。）在該金屬板12，透過絕緣樹 脂層14,而在表面側，形成内層之導體電路16、導體層16£，在背面， 形成導體電路16、導體層16P，並且，透過絕緣樹脂層18，而在表面 側，形成導體電路34、導體層34P，在背面，形成導體電路34、導體 層34E。多層芯基板30係、透過通孔36而得到表面側和背面側間之連 接。此外，也得到和内層間之電氣連接。 在多層怒基板30表面之導體層34p、34E之上，配置形成導通孔 60和導體電路58之層間樹脂絕緣層5〇以及形成導通孔16〇和導體電 路158之層間樹脂絕緣層150。在該導通孔16〇和導體電路158之上 層，形成銲錫阻劑層70，透過該銲錫阻劑層7〇之開口部71，而在導 通孔160和導體電路158，形成凸塊mu、76D。 正如圖9中所示’多層印刷電路板1()之上面侧之錫錯凸塊糊 係連接至1C晶片90之接端面92。此外，還構裝晶片電容器98。另一 2160-6825-PF;Ahddub 20 200529722 -，面了側之外部端子了⑽係連接至標點器板94之接端面 9 6。該狀 態下之所謂外部端子係指pGA、BGA、錫錯凸塊等。 第1實施例-1之多層印刷電路板之製造製程 A·層間樹脂絕緣層之樹脂薄膜之製作 將雙笨紛A型環氧樹脂（環氧當量455、油化蜆殼環氧公司製 Epikote 1001)29重量份、曱酚酚醛清漆型環氧樹脂（環氧當量215、 大:本油墨化予工業公司製Epikur〇nN_673)39重量份、含三嗦構造 之苯盼祕清漆樹脂（笨盼性氮氧基當量12〇、大日本油墨化學工業公 司製苯紛鹽KA- 7052)3〇重量份，授拌同時加熱熔解於乙基二乙二酵 乙酸鹽20重量份和溶劑力2〇重量份，添加末端環氧化聚丁二稀橡膠 鲁（Nagase化成工業公司製TenarekkusuR_45EpT)15重量份和2_苯基 一 4,5—雙（羥基甲基）咪唑粉碎品ι·5重量份、微粉碎二氧化矽2.5 重量份、矽系消泡劑〇· 5重量份，調製環氧樹脂組成物。 在使用滚輥塗敷器而將得到之環氧樹脂組成物塗敷在厚度38_ 之PET薄膜上來使得乾燥後之厚度成為^&quot;^^灸，藉由在8〇〜12(rc， 進行10分鐘之乾燥’而製作層間樹脂絕緣層用樹脂薄膜。 B. 樹脂填充材之調製 藉由將雙苯盼F型環氧單體（油化蜆殼公司製、分子量：31〇、 YL983U)100重量份、在表面塗敷矽烷偶合劑之平均粒徑1. 6/ζπι並且 最大粒子之直徑15/zm以下之3丨〇2球狀粒子（Adotec公司製、CRS 1101 攀一CE)170重量份以及矯平劑（Sann〇puk〇公司製、Peren〇ru S4)1· 5重 量份，放置在容器，進行攪拌及混合，而調製其黏度在23± l〇c成為 44〜49Pa · s之樹脂填充材。此外，作為硬化劑係使用咪唑硬化劑（四 國化成公司製、2E4MZ —CN)6.5重量份。作為填充材用樹脂係可以使 用其他之環氧樹脂（例如雙苯酚A型、酚醛清漆型等）、聚醢亞胺樹脂、 苯酚樹脂等之熱硬化性樹脂。 C. 多層印刷電路板之製造 就圖8所示之多層印刷電路板10之製造方法，參考圖1〜圖7而 進行說明。 (1)〈金屬層之形成製程〉 2160-6825-PF;Ahddub 21 200529722 在圖1(A)所示之厚度20〜400 //m之間之内層金屬芦 板）12，設置貫通表背面之開口 12a(圖1 (B))。在第1實於^ (金屬 20 之金屬板。作為金屬層之材質係可以使用配合鋼、鎳、*使用 鐵等之金屬者。在此，在使用低熱膨脹係數之36合金或42、合$、鋁、 可以使得芯基板之熱膨脹係數接近於1C之熱膨脹係數，因此，=時’、 低熱應力。開口 12β係藉由穿孔、蝕刻、鑽孔、雷射等而-把夠減 可以隨著狀態之不同，而在形成開口 12a之金屬層12之敕/订穿設。 電解電鍍、無電解電鍍、置換電鍍、濺鍍，來被覆金屬膜13 (精由 此外，金屬板12係可以是單層，也可以是2層以上之複數屑 C)) ° 金屬膜13係最好是在開口 12a之角部，形成曲面。藉此而並9益此外’ 中之點，不容易引起在其周邊之破裂等之意外。此外，、P、、、應力集 以不内藏於芯基板内。 反丨2係可 (2)〈内層絕緣層及導體層之形成製程〉 為了覆蓋金屬層12之整體而填充開口 12a内，因此，使 脂。作為形成方法係例如可以藉由厚度30〜4〇〇 程度之B a絕緣樹 脂薄膜，以金屬板12來夾住（圖1(D))，並且，還在^外側^階狀樹 275 /zm之銅箔後，進行熱壓合及硬化，形成絕緣樹脂層=積丨2〜 16(圖1(E))。可以隨著狀態之不同而進行塗敷、塗敷和 I體層 合、或者是僅塗敷開口部分，然後，藉由薄膜所形成。、δ之混 作為材料係最好是使用將聚醯亞胺樹脂、環氧樹脂、 ΒΤ樹脂等之熱硬化性樹脂來含浸於玻纖布、聚醯胺不織布 、 膠$。除了這個以外，也可以使用樹脂。在第i實施例，使用心⑽^ 形成導體層16之方法係可以在金屬訂，藉由電鑛等而形成。 (3)〈内層金屬層之電路形成製程〉 可以成為2層以上。可以藉由加成法而形成金屬層。 經過加成法、蝕刻製程等而由内層金屬層16開始，形成内層導體 層16、16P、16E(® 1(F))。此時之内層導體層之厚度係形成為1〇〜 250 //m。但是’可以超過前述範圍。此外，在第1實施例，内層之電 源用導體層之厚度係25/zm厚度。為了能夠在該電路形成製程來評價 2160-6825-PF；Ahddub 22 200529722 / 芯基板之絕緣可靠性，因此，作為測試圖案（芯基板之絕緣電阻評價用 圖案）係形成導體幅寬/導體間之間隔=15〇 em/lSO/zm之絕緣電阻測 疋用之鋸齒狀圖案。此時，可以在呈電氣地連接於1C電源之電源用通 孔貫通内層電路之接地層時，不具有由電源用通孔開始延出之配線圖 案。同樣地，可以在呈電氣地連接於1C接地之接地用通孔也貫通内層 電路之電源層時，不具有由接地用通孔開始延出之配線圖案。可以藉 由成為此種構造而使得通孔間距變得狹窄。此外，通孔和内層電路間 之間隔成為窄間距，因此，減少相互電感。 (4) 〈外層絕緣層及導體層之形成製程〉 為了覆蓋内層導體層16、16P、16E之整體，並且，填充其電路間 ，間隙，因此，使用絕緣樹脂。作為形成方法係在一直到（3)為止之所 幵之途中基板之兩面，例如在以厚度3〇〜2〇〇# m程度之B台階狀樹 =4=厚度1〇〜275&quot; m之金屬猪之順序而進行層積後，在進行熱壓 二。進仃硬化，形成芯基板之外層絕緣樹脂層18及芯基板之最外 獻人曰(圖2(B))。可以隨著狀態之不同而進行塗敷、塗敷和薄膜 ϊΐϊΓ::而使得表面變得平坦。此外，可以使用以玻纖布、聚醯 風产1膠Η為芯材之B台階狀膠片。在第1實施例，使用2〇〇/Zm Ϊ為形成金屬^以外之方法係、層積單面銅㉟基板。可以 ^ 藉由電鍍等而成為2層以上。可以藉由加成法而形成金 (5) 〈通孔之形成製程〉 ί圖板表背面之開口直徑50〜400 M m之通孔用通孔36 α i 茲t成方法係藉由鑽孔、，射、或者是雷射和鑽孔之複 而#用i 雷射而進行最外層之絕緣層之開口，隨著狀態之不同，Use a conductor $ thick enough to thicken the inner layer to determine the thickness of the wire, as the core body layer. In other words, even if a large-capacity power source is supplied, it can be started without any problems, so it does not cause malfunction or malfunction. At this time, it is also preferable that the thickness of the multi-layer board, the thickness of the conductor layer and the thickness of the conductor layer on the interlayer insulation layer be α 2 and α 2 &lt; α 1 $ 40 α 2. Fig. 28 shows the time change of the voltage starting from the moment when the power source becomes ON (on) 2 = vertical axis, and the voltage of the IC is displayed on the horizontal axis. Figure M is a model of a printed circuit board with the same frequency IC chip and no capacitor for power supply. Line B shows the voltage change over time for the 1GHz IC chip, and line a does not show the voltage change over time for the 3GH ^ IC chip. This change over time requires a lot of power at the moment of starting the sun-dial film. When this supply becomes insufficient, the voltage is lowered (point X, X ', point: the first voltage drop). Then, it is repeated-once the voltage rises, it also drops (the second time the voltage drops) and after the rise, it decreases (the third time the voltage drops) and the amplitude becomes smaller, and at the same time, the voltage gradually increases ^ but When the voltage drops, it is easy to cause the wrong action or error of the 1C chip. In other words, Yang, which became a 1C chip due to insufficient power supply, was unable to fully function and start up. This power shortage (voltage drop) increases as the frequency of the chip (1 :) increases. Therefore, in order to eliminate the voltage drop, it takes time to perform the required function and start, and as a result, a time lag occurs. Figure 29 Series The printed circuit board of the conventional structure and the printed circuit board structure of the present invention 18 2160-6825-PF; Ahddub 200529722 / high-frequency 1C chip time change of 1C voltage. In addition, the voltage measurement of 1 (: Measurement cannot be performed directly, so a measurement circuit that can be measured is formed on a printed circuit board. The multilayer core (conventional structure) of A has four layers, all through-holes have dummy end faces, and the layers of each layer for power supply The conductor thickness is all the same and becomes 15 # m (the power supply layer of the core substrate is 2 layers, and the conductor thickness on the interlayer insulation layer is 30 volts). The multilayer core system of B is the same as a and becomes 4 layers. The surface layer has a power conductor layer of 15 // m, the inner layer has a power conductor layer of 30 / zm, and the power supply vias directly below 1C are in the ground layer of the inner layer of the multi-layer core. There are no power supply vias. Beginning of the extended conductor The ground wire vias directly below 1C are connected to the power supply layer of the inner layer of the multi-layer core. There is no conductor circuit extending from the ground wire vias. C is a multi-layer core of B, which makes the inner conductor thickness 75 / zm. The conductor layer of the multi-layer core is alternately configured with the power layer and the ground layer. A, B, and C are multilayer printed circuit boards with interlayer insulation layers and conductor layers alternately layered on the aforementioned multi-layer core. Figure 2g shows that the first and second voltage drops are improved by the multilayer core structure of the present invention, which does not have a conductor circuit extending from a through hole. Therefore, it can be said that the function of the IC chip is made The occurrence of accidents and movements is reduced. In addition, it is learned that the first and second voltage drops are further improved by making the thickness of the inner conductor thicker. The thickness of the inner circuit is 40 ~ 150 / zm. In the multilayer core substrate, the thickness of the conductor layer of the power supply layer in all layers of the multilayer core substrate is even thicker than that of the conductor layer on the interlayer insulation layer. Thickness, even on multilayer cores The thickness of the conductor layer of the power supply layer of all the layers of the board is the same as or less than the thickness of the conductor layer on the interlayer insulation layer, which also makes the total thickness of the conductor thickness sufficient for all layers thicker than the interlayer insulation. The effect is achieved when the thickness of the conductor layer on the layer is achieved. [Embodiment] A. First Embodiment (First Embodiment 1) Referring to FIG. 1 to FIG. 9, a multilayer of the first embodiment 1 of the present invention will be described. A printed circuit board will be described. First, the structure of the multilayer printed circuit board 10 according to the first embodiment 1 will be described with reference to FIGS. 8 and 9. FIG. 8 shows the multilayer printed circuit board 10. Sectional view, 2160-6825-PF; Ahddub 19 200529722 • Figure 9 shows the state where the multi-layer printed circuit board 1 () shown in FIG. 8 is mounted with the IC chip 9 () and placed on the puncture board 94. As shown in FIG. 8, in the multilayer printed circuit board 10, a multilayer core substrate 30 is used. A conductor circuit material and a conductor layer 34P 'are formed on the front side of the multilayer core substrate 30, and a conductor circuit 34 and a conductor layer 34E are formed on the back side. The upper conductor layer 34p is formed as a power plane layer, and the lower conductor layer 34E is formed as a ground plane layer. In addition, an inner layer of the conductor circuit 16 and a conductor layer 16E are formed on the front side of the inside of the multilayer core substrate 30, and a conductor circuit 16 and a conductor layer 16p are formed on the back surface. The upper conductive layer blue is formed as a ground plane layer, and the lower conductive layer 16P is formed as a power plane layer. The connection to the power supply plane layer is made through vias or vias. The planar layer system may be a single layer having only one side, or may be arranged in two or more layers. It is preferably formed by two to four layers. Lu has more than 5 layers and cannot confirm the improvement of electrical characteristics. Therefore, even if it is more than this layer, the effect is known to be the same as that of 4 layers. When the inner layer becomes five or more layers, the thickness of the fascia becomes thicker. Therefore, on the contrary, the electrical characteristics deteriorate. In particular, since the layer formed by two layers is in the aspect of rigid integration of the so-called multi-layer core substrate, the elongation of the substrate is uniform, so it is not easy to cause f-curves. In the center of the multilayer core substrate 30, an electrically isolated metal plate 12 is housed. (The metal plate 12 also functions as a core material, but there is no electrical connection such as through holes or vias. The main purpose is to improve the rigidity of the substrate.) The metal plate 12 passes through the insulating resin layer 14 On the front side, the inner conductor circuit 16 and the conductor layer 16 are formed, on the back side, the conductor circuit 16 and the conductor layer 16P are formed, and through the insulating resin layer 18, on the surface side, the conductor circuit 34 and the conductor layer are formed. 34P, a conductor circuit 34 and a conductor layer 34E are formed on the back surface. The multilayer core substrate 30 is connected to the front side and the back side through the through-hole 36. In addition, an electrical connection to the inner layer is obtained. On the conductor layers 34p and 34E on the surface of the multilayer substrate 30, an interlayer resin insulating layer 50 forming a via 60 and a conductor circuit 58 and an interlayer resin insulating layer 150 forming a via 160 and a conductor circuit 158 are arranged. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps mu and 76D are formed in the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. As shown in FIG. 9, the tin bump bump on the upper side of the 'multilayer printed circuit board 1 () is connected to the junction end surface 92 of the 1C chip 90. In addition, a chip capacitor 98 is also constructed. The other 2160-6825-PF; Ahddub 20 200529722-, the external terminal on the side is connected to the end face 96 of the puncture plate 94. The so-called external terminals in this state refer to pGA, BGA, tin bumps, and the like. The manufacturing process of the multilayer printed circuit board of the first embodiment-1, the production of the resin film of the interlayer resin insulating layer, the Shuangfanfen A-type epoxy resin (epoxy equivalent 455, Epikote 1001 manufactured by Sinopec Epoxy Corporation) 29 parts by weight, phenol novolac-type epoxy resin (epoxy equivalent 215, large: Epikauron N_673, manufactured by Ben Ink Chemicals Co., Ltd.) 39 parts by weight, benzophenone varnish resin containing trifluorene structure Oxygen equivalent of 120, Dainippon Ink Chemical Industry Co., Ltd. benzene salt KA-7052) 30 parts by weight, while heating and melting 20 parts by weight of ethyldioxalate acetate and 20 parts by weight of solvent power, Added 15 parts by weight of terminal epoxidized polybutadiene rubber Lu (TenarekkusuR_45EpT manufactured by Nagase Kasei Kogyo Kogyo Co., Ltd.) and 2-phenyl-4,5-bis (hydroxymethyl) imidazole crushed product, 5 parts by weight, finely divided dioxide 2.5 parts by weight of silicon and 0.5 parts by weight of a silicon-based defoamer are used to prepare an epoxy resin composition. The obtained epoxy resin composition was coated on a PET film having a thickness of 38 mm using a roller applicator so that the thickness after drying became ^ &quot; ^^ moxibustion. Minutes of drying 'to produce a resin film for interlayer resin insulation layer. B. Preparation of resin fillers: 100 parts by weight of bisphenol hope F-type epoxy monomer (manufactured by Sinopec Corp., molecular weight: 31〇, YL983U) 170% by weight of a spherical particle (manufactured by Adotec Corporation, CRS 1101 Panichi CE) with an average particle diameter of 1.6 / ζπι and a maximum particle diameter of 15 / zm or less, coated on the surface, and 170 wt. 1.5 parts by weight of a flattening agent (manufactured by Sannopuko Co., Perenoru S4), placed in a container, stirred and mixed, and adjusted to a resin filling material having a viscosity of 23 ± 10c at 44 ± 49 Pa · s In addition, 6.5 parts by weight of an imidazole hardener (manufactured by Shikoku Chemical Co., Ltd., 2E4MZ-CN) is used as the hardener. Other resins (such as bisphenol A type, novolac type, etc.) can be used as the resin for the filler. ), Thermosetting properties of polyimide resin, phenol resin, etc. C. Manufacturing of multilayer printed circuit board The manufacturing method of multilayer printed circuit board 10 shown in FIG. 8 will be described with reference to FIGS. 1 to 7. (1) <Formation Process of Metal Layer> 2160-6825-PF Ahddub 21 200529722 In the inner layer metal reed board with a thickness between 20 and 400 // m as shown in Fig. 1 (A), 12 is provided with an opening 12a penetrating the back surface (Fig. 1 (B)). In the first, it is true that ^ (metal 20 is a metal plate. As the material of the metal layer, it is possible to use a metal with steel, nickel, * iron, etc. Here, 36 alloys with low thermal expansion coefficients or 42 are used. , Aluminum, can make the thermal expansion coefficient of the core substrate close to the thermal expansion coefficient of 1C, so == ', low thermal stress. The opening 12β is through perforation, etching, drilling, laser, etc.-can be reduced enough as the state The difference is that the metal layer 12 is formed in the opening 12a. Electrolytic plating, electroless plating, displacement plating, and sputtering are used to cover the metal film 13 (Besides, the metal plate 12 can be a single layer It is also possible to use multiple chips of two or more layers C)) ° The metal film 13 is preferably formed at the corner of the opening 12a to form a curved surface. Taking advantage of this, it is not easy to cause accidents such as rupture in its periphery. In addition, the stress concentrations of P, P, and are not built in the core substrate. Reverse 2 is possible. (2) <Formation process of inner layer insulation layer and conductor layer> The inside of the opening 12a is filled in order to cover the entire metal layer 12, and therefore grease is used. As a forming method, for example, a B a insulating resin film having a thickness of about 30 to 400 can be sandwiched by the metal plate 12 (FIG. 1 (D)), and the tree 275 / zm can be formed on the outer side. The copper foil is then heat-pressed and hardened to form an insulating resin layer = 2 to 16 (Fig. 1 (E)). Depending on the state, coating, coating and I-body lamination may be performed, or only the opening portion may be coated and then formed by a thin film. As a material system, it is best to impregnate glass fiber cloth, polyamide non-woven cloth, and glue with a thermosetting resin such as polyimide resin, epoxy resin, and BT resin. Besides this, resins can also be used. In the i-th embodiment, the method for forming the conductor layer 16 using a core electrode can be formed on a metal substrate, and formed by electric ore or the like. (3) <Process for forming circuit of inner metal layer> The number of layers can be two or more. The metal layer can be formed by an addition method. After the addition method, the etching process, and the like, starting from the inner metal layer 16, the inner conductor layers 16, 16P, and 16E (® 1 (F)) are formed. At this time, the thickness of the inner conductor layer is formed to be 10 to 250 // m. However, 'may exceed the foregoing range. In the first embodiment, the thickness of the conductor layer for power supply in the inner layer is 25 / zm. In order to be able to evaluate the 2160-6825-PF in this circuit formation process; Ahddub 22 200529722 / core substrate insulation reliability, therefore, the test pattern (pattern for insulation resistance evaluation of the core substrate) is formed as a conductor width / between conductors Zigzag pattern for insulation resistance measurement with interval = 15〇em / lSO / zm. In this case, when the power supply through-hole electrically connected to the 1C power supply penetrates the ground layer of the inner circuit, there is no wiring pattern extending from the power supply through-hole. Similarly, when the grounding through-hole electrically connected to the 1C ground also penetrates the power supply layer of the inner layer circuit, there is no wiring pattern extending from the grounding through-hole. By adopting such a structure, the pitch of the through holes can be narrowed. In addition, the space between the via and the inner-layer circuit becomes narrow, so that mutual inductance is reduced. (4) <Formation process of outer insulation layer and conductor layer> In order to cover the whole of the inner conductor layers 16, 16P, and 16E and fill the gaps between the circuits, insulating resin is used. As the formation method, it is on both sides of the substrate on the way up to (3), for example, a stepped tree with a thickness of about 30 to 200 # m = B = a thickness of 10 to 275 &quot; m of metal Pigs were laminated in order, followed by hot pressing. It is hardened to form the insulating resin layer 18 as the outer layer of the core substrate and the most contributor to the core substrate (Fig. 2 (B)). Coating, coating and filming can be performed depending on the state ϊΐϊΓ :: to make the surface flat. In addition, you can use a B-step film with glass fiber cloth and polyisocyanate as the core material. In the first embodiment, a method other than 200 / Zm ㉟ was used to form a single-sided copper ㉟ substrate in a method other than metal 金属. It can be made into two or more layers by plating or the like. Gold can be formed by the addition method (5) <Forming process of through-holes> The through-holes with opening diameters of 50 ~ 400 M m on the back surface of the drawing board are 36 through i through holes α α The method is by drilling ,, shot, or both the laser and the drilled hole, and # the opening of the outermost insulating layer with i laser, depending on the state,

Hi及2 開口，來作為標靶符號，然後，藉由鑽孔器而進行Hi and 2 openings, as the target symbol, and then through the drill

開貰通。）。作為形狀係最好是具有直線狀侧壁。可以隨著狀離之 不同而成為錐形狀。 J以丨现者狀H 成電通之導電性’因此’最好是在通孔用通孔勤内，形 成電鑛膜22，在粗化表面後（圖2⑼），將填充樹脂23予以填充（圖 2160-6825-pp.Ahddub 23 200529722 ;=E))/，為填充樹脂係可以使用進行藉由電氣絕緣之樹脂材料（例如 含有樹脂成分、硬化劑、粒子等）、金屬粒子所造成之電氣連接之導電 f生材料（例如含有金、銅等之金屬粒子、樹脂材料、硬化劑等。）之任 何-種。在填充後，進行假錢，藉由研磨而除讀著於基板表面之 電解銅電鍍膜22上之多餘之填充樹脂，在15〇〇c，進们小時之乾燥 及完全硬化。 ' 作為電鍍係可以使用電解電鍍、無電解電鍍、面板電鍍（無電解電 鏡和電解電鍍）等。作為金屬係藉由含有銅、鎳、始、鱗等而形成。作 為電鍍金屬之厚度係最好是形成於5〜3〇/zm之間。 填充於通孔用通孔36 α内之填充旨23係最好是使用由樹脂材 ·，、硬化劑、粒子等之所構成之絕緣材料。作為粒子係藉由二氧化矽、 氧化銘等之無機粒子、金、銀、銅等之金屬粒子、樹脂粒子等之單獨 或複合而進行配合。可以使錄徑Q•卜5&quot;m者成為相同粒徑或者是 複合粒徑者。作為樹脂材料係可以使用：環氧樹脂（例如雙苯酚型 環氧樹脂、酚醛清漆型環氧樹脂等）、苯酚樹脂等之熱硬化性樹脂、具 有感光性之紫外線硬化樹脂、熱塑性樹脂等之單一或混合者。作為硬 化劑係可以使用咪㈣硬化劑、胺系硬化㈣。除了這個以外，也可 以▲包含硬化穩㈣、反應穩定劑、粒子等。可以使用導電性材料。該 狀態係由金屬粒子、樹脂成分、硬化劑等之所構成者成為導電性材料 之導電性射。可以隨著狀態之不同而使用在勒、絕賴脂等之絕 響緣材料之表層形成具有導電性之金屬膜者等。也可以藉由電鑛而填充 通孔用通孔36α内。由於導電性糊膏係成為硬化收縮，因此，在表声 形成凹部之緣故。 θ (6)〈最外層之導體電路之形成製程〉 可以藉由在整體，被覆電鍍膜，而在通孔36之正上方，形成蓋電 鍍25(圖3(A))。然後，經過隆起法、蝕刻製程等而形成外層導 路34、34卜顯圖3⑻藉此而完成多層芯基板3〇。此曰外 實施例，多層芯基板表面之電源用導體層之厚度係15//m厚度。 此時，雖然並無進行圖示，但是，可以藉由導通孔或盲通孔、盲 導通孔而進行和多層芯基板内層之導體層16等之間之電氣連接。 2160-6825-PF;Ahddub 24 200529722 ， （Ό對於形成導體電路34之多層芯基板30，來進行黑化處理及還 •原處理，在導體電路34、導體層34Ρ、34Ε之整個表面了形^粗化面 34 冷（圖 3(C))。 (8) 在多層芯基板30之導體電路非形成部，形成樹脂填充材4〇 之層（圖4(A))。 ' (9) 藉由帶狀打磨器等之研磨，來對於結束前述處理之基板之單 面，進行研磨，而在導體層34Ρ、34Ε之外緣部，不殘留樹脂填充材 40，接著，除去由於前述研磨所造成之損傷，因此，在導體層34Ρ、 34Ε之整個表面（包含通孔之接端面表面），藉由拋光等而還進行研 磨。即使是就基板之其他面而言，也同樣地進行此種一連串之研磨。 鲁接著，在100°C，進行1小時之加熱處理，在150°C，進行1小時之加 熱處理而硬化樹脂填充材40(圖4(B))。 此外，可以不進行導體電路間之樹脂填充。該狀態係藉由層間絕 緣層等之樹脂層而進行絕緣層之形成和導體電路間之填充。 (10) 在前述多層芯基板30，藉由喷霧器而將蝕刻液吹附在基板之 兩面，藉由蝕刻等而蝕刻導體電路34、導體層34P、34E之表面和通 孔36之接端面之表面，在導體電路之整個表面，形成粗化面36/?(圖 4(C))。 (11) 藉由在多層芯基板30之兩面，將層間樹脂絕緣層用樹脂薄膜 50 r載置於基板上，在進行假壓合及裁斷後，並且，還使用真空層壓 •裝置，進行貼附，而形成層間樹脂絕緣層（圖5(A))。 (12) 接著，藉由波長10· 4/z m之C〇2氣體雷射，以束直徑4. 0mm、 頂蓋模式、脈衝幅寬3.0〜7·9/ζ秒、罩幕之貫通孔之直徑1.0〜 5. 0mm、1〜3次發射之條件，在層間樹脂絕緣層，形成直徑80〜100 /zm之導通孔用開口 50a(圖5(B))。 (13) 將基板30浸潰在包含60g/l之過錳酸之80°C之溶液10分 鐘，在包含導通孔用開口 50a内壁之層間樹脂絕緣層50之表面，形成 粗化面50α (圖5(C))。粗化面係形成於0· 1〜5//m之間。 (14) 接著，在將結束前述處理之基板30浸潰於中和溶液（Sibuley 公司製）後，進行水洗。此外，藉由在粗面化處理（粗化深度3/zm)之 2160-6825-PF;Ahddub 25 200529722 . 該基板之表面賦予鈀觸媒，而在層間樹脂絕緣層之表面及導通孔用開 口之内壁面，附著觸媒核。 (15) 接著，在無電解銅電鍍水溶液中，浸潰賦予觸媒之基板’在 整體粗面，形成厚度0. 6〜3. 0//m之無電解銅電鍍膜，得到在包含導 通孔用開口 50a内壁之層間樹脂絕緣層50之表面形成無電解銅電鍍膜 52的基板（圖5(D))。 [無電解銅電鍍液] 硫酸銅：0. 03mol/l EDTA ： 0.200raol/l HCHO ： 0.18g/l _ NaOH : 0.100mol/l a, a’ 一聯二吼°定：100mg/l 聚乙二醇：0· 10g/l [電鍍條件] 在34C之液體溫度40分鐘 (16) 藉由在形成無電解銅電鍍膜52之基板，貼附市面販賣之感光 性乾膜，在載置罩幕來進行曝光後，進行顯影處理，而設置電鍍阻劑 54(圖6(A))。此外，在該層間絕緣層上之一部分，為了評價由於多層 芯基板之導體厚度所發生之層間絕緣層之起伏之影響，因此，形成電 鍍阻劑，來使得電鍍形成後之配線圖案（最小線間距、線幅寬形成能力 ®評價圖案）成為導體幅寬/導體間之間隔= 5/5//m、7. 5/7. 5/zm、10/10 //m、12· 5/12. 5//m、15/15//m。電鍍阻劑之厚度係使用10〜30/zm 之間。 (17) 接著，在基板30施行電解電鍍，在電鍍阻劑54之非形成部， 形成厚度5〜20//m之電解銅電鍍膜56(圖6(B))。 [電解電鍍液] 硫酸 2. 24mol/l 硫酸銅 0. 26mol/l 添加劑 19. 5ml/l (Atoteck-Japan 公司製、Kaparashido GL) 2160-6825-PF;Ahddub 26 200529722 - [電解電鍍條件] 電流密度 lA/dm2 時間 90± 5分鐘Opened. ). The shape system preferably has a linear side wall. It can be tapered depending on the shape. J becomes the electrical conductivity of the electric current in the form of H. Therefore, it is best to form the electro-membrane 22 in the through hole for the through hole. After roughening the surface (Figure 2⑼), the filling resin 23 is filled ( Figure 2160-6825-pp.Ahddub 23 200529722; = E)) /, for filling the resin system can be used for electrical insulation of resin materials (such as containing resin components, hardeners, particles, etc.), electrical caused by metal particles Any one of the connected conductive materials (such as metal particles containing gold, copper, etc., resin materials, hardeners, etc.). After the filling, fake money is removed, and the excess filling resin on the electrolytic copper plating film 22 read on the surface of the substrate is removed by grinding, and dried and completely hardened at 150 ° C for 1 hour. '' As the plating system, electrolytic plating, electroless plating, and panel plating (electroless microscopy and electrolytic plating) can be used. The metal system is formed by containing copper, nickel, starting, scale, and the like. The thickness of the plated metal is preferably between 5 and 30 / zm. The filling purpose 23 to be filled in the through hole 36 α for the through hole is preferably an insulating material made of a resin material, a hardener, particles, or the like. As the particles, inorganic particles such as silicon dioxide and oxide oxide, metal particles such as gold, silver, copper, and resin particles are used alone or in combination. It is possible to make the recording diameter Q · bu 5 &quot; m the same particle diameter or composite particle diameter. As the resin material, epoxy resin (such as bisphenol epoxy resin, novolac epoxy resin, etc.), thermosetting resin such as phenol resin, photosensitive ultraviolet curing resin, thermoplastic resin, etc. can be used. Or mixed. As the hardening agent system, a proton curing agent and an amine curing agent can be used. In addition to this, ▲ may include hardening stabilizers, reaction stabilizers, particles, and the like. A conductive material can be used. This state is a conductive radiation in which a material composed of metal particles, a resin component, a hardener, and the like becomes a conductive material. Depending on the state, a conductive metal film can be used on the surface layer of a sound-insulating edge material, such as a resin or a resin. The through holes 36α for through holes may be filled by electric ore. Since the conductive paste is hardened and shrunk, a recess is formed in the surface sound. θ (6) <Forming process of outermost conductor circuit> A cover plating 25 can be formed by coating the whole with a plating film and directly above the through hole 36 (Fig. 3 (A)). Then, the outer layer guides 34 and 34 are formed through a bumping method, an etching process, and the like, as shown in FIG. 3, thereby completing the multilayer core substrate 30. In this embodiment, the thickness of the power conductor layer on the surface of the multilayer core substrate is 15 // m. At this time, although not shown in the figure, electrical connection with the conductive layer 16 and the like in the inner layer of the multilayer core substrate can be performed through vias, blind vias, and blind vias. 2160-6825-PF; Ahddub 24 200529722 ， (Ό For the multilayer core substrate 30 forming the conductor circuit 34, blackening treatment and reduction treatment are performed, and the entire surface of the conductor circuit 34, the conductor layer 34P, 34E is shaped ^ The roughened surface 34 is cold (Fig. 3 (C)). (8) A layer of a resin filler 40 is formed in the non-conductor portion of the conductor circuit of the multilayer core substrate 30 (Fig. 4 (A)). The polishing of a belt-shaped sander etc. is performed to polish one side of the substrate on which the aforementioned processing is completed, and the resin filler 40 is not left on the outer edge portions of the conductor layers 34P and 34E. Then, the resin filler 40 is removed by the aforementioned polishing Damage, therefore, the entire surfaces of the conductor layers 34P and 34E (including the end surface surfaces of the through holes) are polished by polishing or the like. Even in the case of the other surfaces of the substrate, a series of such processes are performed similarly. Grinding: Next, heat treatment is performed at 100 ° C for 1 hour and at 150 ° C for 1 hour to harden the resin filler 40 (Fig. 4 (B)). In addition, it is not necessary to conduct between conductors and circuits. Filled with resin. This state is achieved by interlayer insulation The resin layer is used to form the insulating layer and fill the conductor circuit. (10) The multilayer core substrate 30 is sprayed with an etchant on both sides of the substrate by a sprayer, and the conductor circuit 34 is etched by etching or the like. The surfaces of the conductor layers 34P and 34E and the surfaces of the end faces of the through holes 36 form a roughened surface 36 /? Across the entire surface of the conductor circuit (Fig. 4 (C)). (11) By using the multilayer core substrate 30 On both sides, the interlayer resin insulation layer is placed on the substrate with a resin film 50 r on the substrate, and after false compression bonding and cutting, it is also attached using a vacuum lamination device to form an interlayer resin insulation layer (Fig. 5 (A)). (12) Next, a CO 2 gas laser with a wavelength of 10. 4 / zm is used, with a beam diameter of 4.0 mm, a cap mode, and a pulse width of 3.0 to 7.9 / ζsec. The diameter of the through hole of the cover is 1.0 to 5.0 mm, and the emission is 1 to 3 times. In the interlayer resin insulation layer, an opening 50a for a via hole with a diameter of 80 to 100 / zm is formed (Fig. 5 (B)). (13) ) The substrate 30 was immersed in a solution of 80 ° C containing 60 g / l permanganic acid for 10 minutes, and the interlayer resin insulating layer 50 including the inner wall of the via hole opening 50a On the surface, a roughened surface 50α is formed (FIG. 5 (C)). The roughened surface is formed between 0.1 and 5 // m. (14) Next, the substrate 30 that has been subjected to the aforementioned processing is immersed in neutralization. The solution (manufactured by Sibuley Co., Ltd.) was washed with water. In addition, a roughening treatment (roughening depth 3 / zm) of 2160-6825-PF; Ahddub 25 200529722 was applied to the surface of the substrate. A catalyst core is attached to the surface of the interlayer resin insulating layer and the inner wall surface of the opening for the via hole. (15) Next, in the electroless copper electroplating aqueous solution, the substrate provided with the catalyst is immersed in the entire rough surface to form an electroless copper electroplated film having a thickness of 0.6 to 3. 0 // m to obtain a via hole. A substrate on which an electroless copper plating film 52 is formed on the surface of the interlayer resin insulating layer 50 on the inner wall of the opening 50a (FIG. 5 (D)). [Electroless copper electroplating solution] Copper sulfate: 0.03mol / l EDTA: 0.200raol / l HCHO: 0.18g / l _ NaOH: 0.100mol / la, a 'two-in-one method: 100mg / l polyethylene Alcohol: 0 · 10g / l [Plating conditions] At a liquid temperature of 34C for 40 minutes (16) A commercially-available photosensitive dry film is attached to a substrate on which an electroless copper plating film 52 is formed, and placed on a cover After the exposure is performed, a development process is performed to provide a plating resist 54 (FIG. 6 (A)). In addition, in order to evaluate the influence of the fluctuation of the interlayer insulating layer due to the conductor thickness of the multilayer core substrate on a part of the interlayer insulating layer, a plating resist is formed to make the wiring pattern (minimum line spacing) after the plating is formed. 、 Line width forming ability® evaluation pattern) becomes conductor width / interval between conductors = 5/5 // m, 7. 5/7. 5 / zm, 10/10 // m, 12 · 5/12. 5 // m, 15/15 // m. The thickness of the plating resist is between 10 and 30 / zm. (17) Next, electrolytic plating is performed on the substrate 30, and an electrolytic copper plating film 56 having a thickness of 5 to 20 // m is formed on the non-formed portion of the plating resist 54 (FIG. 6 (B)). [Electrolytic plating solution] sulfuric acid 2.24mol / l copper sulfate 0.26mol / l additive 19.5ml / l (manufactured by Atoteck-Japan, Kaparashido GL) 2160-6825-PF; Ahddub 26 200529722-[electrolytic plating conditions] current Density lA / dm2 Time 90 ± 5 minutes

溫度 22± 2°C (18) 此外，在藉由5%程度之Κ0Η而剝離及除去電鍍阻劑後，藉由 硫酸和過氧化氫之混合液，來對於該電鍍阻劑下之無電解電鍍膜，進 行蝕刻處理及溶解除去，成為獨立之導體電路58及導通孔6〇(圖 6(C))。 (19) 接著，進行相同於前述（12)之同樣處理，在導體電路58及導 通孔60之表面，形成粗化面58α、60α。本實施例之層間絕緣層上 鲁之導體層之厚度係20/z m(圖6(D))。 曰 (20) 藉由重複地進行前述（u)〜（19)之製程而還形成上層之導體 電路，得到多層電路板（圖7(A))。 (21) 接著，在多層電路基板之兩面，以12〜3〇 之厚度來塗敷 市面販賣之銲錫阻劑組成物70,在以70°C、20分鐘之條件以及7(rc、 30分鐘之條件而進行乾燥處理後（圖7(B))，將描劃銲錫阻劑開口部之 圖案之厚度5mm之光罩，密合在銲錫阻劑層7〇，以1〇〇〇mJ/cm2之紫外 線來進行曝光，以DMTG溶液來進行顯影處理，形成2〇〇am直徑之開 口 71(圖 7(C))。 接著，還分別以在80°c、1小時、在10(Tc、1小時、在I20°c、 • 1小時、在150°C、3小時之條件，個別地進行加熱處理，硬化銲錫阻 劑層，形成具有開口並且其厚度1〇〜25/zm之銲錫阻劑圖案層。 (22) 接著，將形成銲錫阻劑層7〇之基板，浸潰在無電解鎳電鍍 液，在開口部71 ,形成厚度5//m之鎳電鍍層72。此外，將該基板浸 潰於無電解金電鍍液，在鎳電鍍層72上，形成厚度〇· 03//m之金電鍍 層74(圖7(D))。除了鎳—金屬以外，也可以形成錫、貴金屬層（金、 銀、鈀、白金等）之單層。 (23) 然後’在載置基板之ic晶片之面之銲錫阻劑層70之開口 71，印刷含有錫一鉛之錫鉛糊膏，並且，在其他面之銲錫阻劑層之開 口印刷含有錫一銻之錫鉛糊膏後，藉由在20(rc進行重熔而形成外部 2160-6825-PF;Ahddub 27 200529722 - 端子，製造具有錫錯凸塊之多層印刷電路板（圖8)。 _ 透過錫船凸塊76U而安裝1C晶片90,構襞晶片電容器98。接著， 透過外部端子76D而安裝至標點器板94(圖9)。 根據前述第1實施例一1而製作第1實施例_ 2〜第1實施例一 28 和第1比較例一 1〜第1比較例一3。但是，在各個實施例、比較例， 改變芯基板之導體層厚度、芯基板之導體層之層數目、不具有假接端 面之通孔數目、不具有假接端面之區域以及層間絕緣層上之導體層厚 度。在改變内層之導體層厚度之狀態下，在圖1(E)，改變銅箔之厚度。 在改變芯基板之表背面之導體層厚度之狀態下，改變圖2(b)之銅箔厚 度及圖2(D)、圖3(A)之電鍍厚度。在改變芯基板之導體層之層數目之 •狀態下，在圖2(B)之製程後，藉由重複地進行既定次數之電路形成、 電路表面之粗化、膠片和銅箔之層積而進行。在改變不具有假接端面 之通孔數目或不具有假接端面之區域之狀態下，在圖KF)之電路形成 (隆起法）時，藉由改變用以蝕刻銅箔之蝕刻阻劑形成時之曝光罩幕而 進行（參考圖19、圖38，在圖19，成為無假接端面之例子，在圖38， 成為全部假接端面之例子。）。在改變層間絕緣層上之導體層厚度之狀 態下，在圖6(B)，藉由改變電鍍厚度而進行。 在以下’顯示各個實施例和比較例之芯層數目、電源用導體層之 厚度、層間絕緣層上之導體層厚度、不具有假接端面之通孔數目及其 區域等。 籲（第1實施例一1) 4層怒基板之内層之電源用導體層之厚度·· 25//ΙΠ 4層芯基板表層之電源用導體層之厚度：15//Π1 芯基板之電源用導體層之厚度和：4〇# m 層間絕緣層上之導體層之厚度：20/zm (第1實施例一2) 4層芯基板之内層之電源用導體層之厚度：15/ΖΠ1 4層芯基板表層之電源用導體層之厚度：9 a ^ 芯基板之電源用導體層之厚度和：24 層間絕緣層上之導體層之厚度：2〇vm 2160-6825-PF；Ahddub 28 200529722 (第1實施例一 3) 4層芯基板之内層之電源用導體層之厚度：45# m 4層芯基板表層之電源用導體層之厚度：15//m 芯基板之電源用導體層之厚度和：60//m 層間絕緣層上之導體層之厚度：20//m (第1實施例一 4) 4層芯基板之内層之電源用導體層之厚度：60//m 4層芯基板表層之電源用導體層之厚度：15//m 芯基板之電源用導體層之厚度和：75#m 層間絕緣層上之導體層之厚度：20/zm φ (第1實施例一5) 14層芯基板之各個内層之電源用導體層之厚度：100//m 14層芯基板表層之電源用導體層之厚度：15//m 芯基板之電源用導體層之厚度和：615/zm 層間絕緣層上之導體層之厚度：20//m (第1實施例一 6) 18層芯基板之各個内層之電源用導體層之厚度：100/z m 18層芯基板表層之電源用導體層之厚度：15/zm 芯基板之電源用導體層之厚度和·· 815/zm 層間絕緣層上之導體層之厚度：20/zm •(第1實施例-7) 4層芯基板之内層之電源用導體層之厚度：15# m 4層芯基板表層之電源用導體層之厚度：45//m 芯基板之電源用導體層之厚度和：60//m 層間絕緣層上之導體層之厚度：20//in (第1實施例一 8) 4層芯基板之内層之電源用導體層之厚度：15//m 4層芯基板表層之電源用導體層之厚度：60//m 芯基板之電源用導體層之厚度和：75 // m 層間絕緣層上之導體層之厚度：20/zm 2160-6825-PF;Ahddub 29 200529722 (第1實施例一9) 4層芯基板之内層之電源用導體層之厚度： 4層芯基板表層之電源料體層之厚度：爪 芯基板之電源用導體層之厚度和：65“爪 層間絕緣層上之導體層之厚度：別以爪 (第1實施例一 10) 4層怒基板之内層之電源轉體層之厚度： 4層芯基板表層之電源科體層之厚度：15_ m 芯基板之電源用導體層之厚度和：l65&quot;m 層間絕緣層上之導體層之厚度：2〇以瓜 此外，在前述⑷之〈外層絕緣層 &quot;m厚度之膠片。 製程，使用300 (第1實施例一11) 4層芯基板之内層之電源用導體層之厚度：175_ 4層芯基板表層之電源料體層之厚度：15_ 芯基板之電源用導體層之厚度和：19〇&quot;瓜 層間絕緣層上之導體層之厚度：2q 此外，在前述⑷之 &lt; 外層絕緣層及=層之 &quot;m厚度之膠片。 表使用300 (第1實施例一 12) 4層芯基板之内層之電源用導體層之厚度：2〇〇_ 4層芯基板表層之電源用導體層之厚度· i5“m 芯基板之電源用導體層之厚度和：m 層間絕緣層上之導體層之厚度：20//m 此：’：前述⑷之〈外層絕緣層及導;層之形成〉製程使請 # m厚度之膠片。 (第1實施例一 13 ) 在第以關-3’使得電源用觀和㈣麟狀—部分，成為 在前述（3)之〈内層金&gt;1層之電路形成製程 &gt; 中之所顯示之不具有假接 端面之通孔。該區域係1C正下方部’不具有假接端面之電源用通孔數 2160-6825-PF；Ahddub 30 200529722 ；目係相對於全電源用通孔而成為50%，不具有假接端面之接地用通孔 數目係相對於全接地用通孔而成為50〇/〇。 (第1實施例一 14) 在第1實施例一3，使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不 具有假接端面之通孔。 (第1實施例一 15 ) 在第1實施例一9,使得電源用通孔和接地用通孔之一部分，成為 在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不具有假接 端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔數 Φ目係相對於全電源用通孔而成為50%，不具有假接端面之接地用通孔 數目係相對於全接地用通孔而成為50%。 (第1實施例一16) 在第9實施例一9，使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之&lt;内層金屬層之電路形成製程&gt;中之所顯示之不 具有假接端面之通孔。 (第1實施例一17) 在第1實施例一4’使得電源用通孔和接地用通孔之一部分，成為 在前述（3)之&lt;内層金屬層之電路形成製程〉中之所顯示之不具有假接 端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔數 騫目係相對於全電源用通孔而成為5〇%，不具有假接端面之接地用通孔 數目係相對於全接地用通孔而成為50%。 (第1實施例一18) 、在第1實施例一4，使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不 具有假接端面之通孔。 (第1實施例一19) 在第1實施例-10 ’使得電源料孔和接地用通孔之—部分，成 為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不具有假 接端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔 31 2160-6825-PF；Ahddub 200529722 數目係相對於全電源用通孔而成為50%，不具有假接端面之接地用通 孔數目係相對於全接地用通孔而成為50%。 (第1實施例一 20) 在第1實施例一 10,使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不 具有假接端面之通孔。 (第1實施例一21) 在第1實施例一 11，使得電源用通孔和接地用通孔之一部分，成 為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不具有假 接端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔 •數目係相對於全電源用通孔而成為5〇%，不具有假接端面之接地用通 孔數目係相對於全接地用通孔而成為5〇%。 (第1實施例一22) 在第1實施例一 11，使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不 具有假接端面之通孔。 (第1實施例一23) 在第1實施例一 12,使得電源用通孔和接地用通孔之一部分，成 為在前述（3)之&lt;内層金屬層之電路形成製程&gt;中之所顯示之不具有假 接端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔 響數目係相對於全電源用通孔而成為5〇%，不具有假接端面之接地用通 孔數目係相對於全接地用通孔而成為5〇%。 (第1實施例—24) 在第1實施例一 12,使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述（3)之&lt;内層金屬層之電路形成製程&gt;中之所顯示之不 具有假接端面之通孔。 (第1實施例一 25) 在第1實施例一7,使得電源用通孔和接地用通孔之一部分，成為 在前述（3)之&lt; 内層金屬層之電路形成製程 &gt; 中之所顯示之不具有假接 端面之通孔。該區域係1C正下方部，不具有假接端面之電源用通孔數 2160-6825-PF；Ahddub 32 200529722 目係相對於全電源用通孔而成為50%，不具有假接端面之接地用通孔 數目係相對於全接地用通孔而成為5〇%。 (第1實施例一 26) 在第、1實施例一 7，使得1C正下方部之全電源用通孔和全接地用 通孔’成為在刚述（3)之&lt;内層金屬層之電路形成製程&gt;中之所顯示之不 具有假接端面之通孔。 (第1實施例一 27) 6層芯基板之各個内層之電源用導體層之厚度： 6層芯基板表層之電源用導體層之厚度：15&quot;m 芯基板之電源用導體層之厚度和：8()^m φ 層間絕緣層上之導體層之厚度：20/zm (第1實施例一 28) 4層芯基板之内層之電源用導體層之厚度： 4層芯基板表層之電源用導體層之厚度：15vm 芯基板之電源用導體層之厚度和： 層間絕緣層上之導體層之厚度：2〇；/m (第1實施例一 29) 在第1實施例-27 ’使得電制通孔和接地用通孔之—部分，成 為在前述（3)之〈内層金屬層之電路形成製程〉中之所顯示之不具有假 接端面之通孔。該區域係IC正下方部，不具有假接端面之電源用通孔 數目躲對於全電源錢孔而成為咖，不具有假接端面之接地用通 孔數目係相對於全接地用通孔而成為5〇%。 (第1實施例一 30) 在第1實施例-29’使得1C正下方部之全電源用通孔和全接地用 通孔，成為在前述⑶之〈内層金屬層之電路形成製程〉中之所顯示之不 具有假接端面之通孔。 (第1比較例_ 1) 4層芯基板之内層之電源用導體層之厚度：1〇&quot;m 4層芯基板表層之電源用導體層之厚度· 1〇^m 芯基板之電源用導體層之厚度和·· 2160-6825-PF;Ahddub 33 200529722 層間絕緣層上之導體層之厚度：2〇 (第1比較例一2) m 18層芯基板之各個内層之電源用暮 a#使k主既 电体用导體層之厚度：100// 18層芯基板表層之電源用導體層之： 芯基板之電源用導體層之厚度和：料㈤’ 層間絕緣層上之導體層之厚度：2〇^m (第1比較例一 3) 22層芯基板之各個内層之電源料體層之厚度：⑽p 22層芯基板表層之電源用導體層之厚度：15 芯基板之電源用導體層之厚度和： 層間絕緣層上之導體層之厚度：2〇#m 此外，在第1實施例、帛！比較例之多層印刷電路板，並無關於 叙接端面之$己述者係全部通孔具有假接端面。 在第1實施例_1〜第1實施例一12、第丨實施例_27、28和第i 比杈例一1〜第1比杈例~3之多層印刷電路板，構裝頻率3· 1GHz之 1C晶片，供應相同量之電源，測定在啟動時之電壓之下降量（相當於 發生複數次之電壓下降中之第3次之下降量）。此外，在IC，無法直 接地測定1C之電壓，因此，在印刷電路板上，形成可測定之電路，測 定ic之電壓。將此時之電壓下降量之值，顯示在圖13、圖15。成為 在電源電壓1.0V時之變動之電壓下降量之值。 此外，在第1實施例一1〜第丨實施例_12、第丨實施例_28和 第1比較例一1〜第1比較例一 3之印刷電路板，進行HAST試驗（85〇c、 濕度85%、施加3. 3V)。此外，被評價圖案係形成於芯基板之絕緣電阻 評價用測試圖案。將該結果顯示在圖13。試驗時間係Π5小時，合格 係115小時後之絕緣電阻值成為i〇_7q以上，在低於這個時，成為不 良0 此外，第1實施例一 3、4、7、8係在印刷電路板之製作中， 最小線間、線幅寬形成能力評價圖案（參考第1實施例一 1之前 行 製程）之評價。使得該結果成為形成能力而顯示於圖14中。在圖 〇係表示無短路，X係表示在相鄰接之配線有短路存在。 ’ 2160-6825-PF；Ahddub 34 200529722 • 對於各種α 1/0:2而將電壓下降量和HAST後之絕緣電阻之結果， 顯示在圖13、圖15。HAST試驗後之結果係記載合格成為〇、不良成 為X。此外，將對於各種α 1/α 2之電壓下降量來進行圖形化者，顯 示在圖17。 在圖13、圖15之結果，如果在電源電壓1. 〇ν時而使得變動容許 範圍成為± 10%(第3次之電壓下降量）的話，則電壓之舉動變得穩定， 不引起1C晶片之錯誤動作等。也就是說，在該狀態下，如果電壓下降 量成為0· IV以内的話，則不引起由於電壓下降所造成之對於起ic晶 片之錯誤動作等。因此，如果是0· 09V以下的話，則增加穩定性。因 此，（多層芯基板之電源用導體層之厚度和/層間絕緣層上之導體層之 •厚度）之比值係可以超過1·〇。此外，如果是1.2$ (多層芯基板之電源 用導體層之厚度和/層間絕緣層上之導體層之厚度40之範圍的 話，則成為變動容許範圍内。 但是，在該值超過8. 25時，開始進行上升，在超過時，電壓 下降量係超過0· IV。推測這個係由於多層芯基板之導體層變厚，或者 是增加内層之層數目’使得通孔長度變長，在供應至Ic之電源供應， 需要時間之緣故。 但是，即使（多層芯基板之電源用導體層之厚度和/層間絕緣層上 之導體層之厚度）成為前述範圍，僅1層之導體層變厚之第丨實 U、12係也使得絲板之絕緣可靠性更加差於其他之實===不 良（參考圖13)。由於這樣而得知：不僅是僅i層變厚，也可以藉 於怎進行多層化，使得電源用導體層之厚度和成為前述範圍，; 是搭載高頻之1C，也不發生錯誤動作，成為絕緣可靠性良好之印 此外，在解析第1實施例-1卜12之芯基板之絕緣性評價用測試 圖案時’使得線間之間隔變得狹窄。推測這個係成為原因而 電阻低於規格。此外，也由圖14之第丨實施例一3、4和 一7、8之比較而得知：多層芯基板之表背面之導體層之厚产 : 更加薄於内層之導體層之厚度。由於這個係在表背面形：厚 ： 時，因為其影響而使得層間劑呈起伏，所以，在層間絕緣層上导= 2160-6825-PF;Ahddub 35 200529722 形成微細之配線之緣故。 28、第1比較例Ή所製造 之方法而確認在以之1C晶片 就按照第1實施例一 1〜12、27、 之多層印刷電路板而言，藉由以下說明 是否有錯誤動作。 作為1C晶片係將由以下之No. 1〜3所選出之任何一種 個多層印刷電路板，進行100次之同時開關，評價有無:誤: 將這些結果，顯示在圖15。Temperature 22 ± 2 ° C (18) In addition, after stripping and removing the plating resist by 5% of K0Η, the electroless electricity under the plating resist is mixed with a mixed solution of sulfuric acid and hydrogen peroxide. The film is plated, subjected to etching treatment, and dissolved and removed, and becomes an independent conductor circuit 58 and a via 60 (FIG. 6 (C)). (19) Next, the same processing as in the above (12) is performed to form the roughened surfaces 58α, 60α on the surfaces of the conductor circuit 58 and the via 60. The thickness of the conductor layer on the interlayer insulating layer in this embodiment is 20 / z m (Fig. 6 (D)). (20) A multilayer circuit board is obtained by repeatedly performing the above-mentioned processes (u) to (19) to form a conductor circuit of the upper layer (Fig. 7 (A)). (21) Next, apply a commercially available solder resist composition 70 on both sides of the multilayer circuit board to a thickness of 12 to 30, and at 70 ° C, 20 minutes, and 7 (rc, 30 minutes) After performing a drying process under conditions (FIG. 7 (B)), a mask with a thickness of 5 mm, which traces the pattern of the opening portion of the solder resist, is adhered to the solder resist layer 70, and the thickness is 1000 mJ / cm2. Exposure was performed with ultraviolet light, and development treatment was performed with a DMTG solution to form an opening 71 having a diameter of 2000 μm (FIG. 7 (C)). Then, the temperature was further measured at 80 ° C, 1 hour, and 10 (Tc, 1 hour). , At I20 ° C, • 1 hour, 150 ° C, 3 hours, individually heat treatment to harden the solder resist layer to form a solder resist pattern layer with an opening and a thickness of 10 to 25 / zm (22) Next, the substrate on which the solder resist layer 70 is formed is immersed in an electroless nickel plating solution, and a nickel plating layer 72 having a thickness of 5 // m is formed in the opening 71. In addition, the substrate is immersed On the electroless gold plating solution, a gold plating layer 74 (FIG. 7 (D)) having a thickness of 0.03 // m is formed on the nickel plating layer 72. In addition to nickel-metal, To form a single layer of tin, a precious metal layer (gold, silver, palladium, platinum, etc.) (23) Then, 'the opening 71 of the solder resist layer 70 on the surface of the IC wafer on which the substrate is placed, and printing tin-lead Tin-lead paste, and tin-antimony-containing tin-lead paste printed on the opening of the solder resist layer on the other side, and then remelted at 20 (rc) to form an exterior 2160-6825-PF; Ahddub 27 200529722 -Terminals to manufacture multilayer printed circuit boards with tin bumps (Figure 8). _ 1C chip 90 is mounted through tin boat bump 76U, and wafer capacitor 98 is constructed. Then, it is mounted to the marker board through external terminal 76D. 94 (Fig. 9). The first embodiment _ 2 to 1st embodiment 28 and the first comparative example 1 to 1st comparative example 1 3 were produced based on the first embodiment 1-1. However, in each embodiment Comparative example, changing the thickness of the conductor layer of the core substrate, the number of layers of the conductor layer of the core substrate, the number of through holes without the dummy end surface, the area without the dummy end surface, and the thickness of the conductor layer on the interlayer insulation layer. In the state of the thickness of the inner conductor layer, change the thickness of the copper foil in Figure 1 (E) In the state of changing the thickness of the conductor layer on the front and back surfaces of the core substrate, change the thickness of the copper foil in FIG. 2 (b) and the plating thickness in FIGS. 2 (D) and 3 (A). Under the state of the number of layers, after the process of FIG. 2 (B), it is performed by repeatedly performing a predetermined number of times of circuit formation, circuit surface roughening, and film and copper foil lamination. The change does not have a false end surface In the state of the number of through holes or the area without a dummy end surface, when the circuit (figure method) of FIG. KF is formed, it is performed by changing the exposure mask when the etching resist used to etch the copper foil is formed ( Referring to Figs. 19 and 38, Fig. 19 shows an example without a dummy end face, and Fig. 38 shows an example of a full dummy end face. ). In a state where the thickness of the conductor layer on the interlayer insulating layer is changed, FIG. 6 (B) is performed by changing the plating thickness. The number of core layers, the thickness of the conductor layer for power supply, the thickness of the conductor layer on the interlayer insulation layer, the number of through holes without dummy end faces, and their regions are shown in the following '. (1st Example 1) Thickness of the power supply conductor layer in the inner layer of the 4-layer substrate. 25 // ΙΠ Thickness of the power supply conductor layer in the surface layer of the 4-layer core substrate: 15 // Π1 for the power supply of the core substrate The thickness of the conductor layer: 4〇 # m The thickness of the conductor layer on the interlayer insulation layer: 20 / zm (the first embodiment 1) The thickness of the conductor layer for the power supply in the inner layer of the 4-layer core substrate: 15 / ZΠ1 4 layers The thickness of the power supply conductor layer on the surface of the core substrate: 9 a ^ The thickness of the power supply conductor layer on the core substrate and: 24 The thickness of the conductor layer on the interlayer insulation layer: 20vm 2160-6825-PF; Ahddub 28 200529722 (No. 1 Example 1 3) The thickness of the power supply conductor layer on the inner layer of the 4-layer core substrate: 45 # m The thickness of the power supply conductor layer on the surface layer of the 4-layer core substrate: 15 / m The thickness of the power supply conductor layer on the core substrate and : 60 // m thickness of the conductor layer on the interlayer insulation layer: 20 // m (the first embodiment 4) the thickness of the power conductor layer on the inner layer of the 4-layer core substrate: 60 // m 4-layer core substrate surface layer The thickness of the conductor layer for power supply: 15 // m The thickness of the conductor layer for power supply of the core substrate: 75 # m The thickness of the conductor layer on the interlayer insulation layer: 20 / zm φ (First Embodiment 5) Thickness of the power conductor layer of each inner layer of the 14-layer core substrate: 100 // m Thickness of the power conductor layer of the 14-layer core substrate surface layer: 15 // m power supply of the core substrate The thickness of the conductor layer is: 615 / zm The thickness of the conductor layer on the interlayer insulation layer: 20 // m (the first embodiment 1 to 6) The thickness of the conductor layer for the power supply of each inner layer of the 18-layer core substrate: 100 / zm The thickness of the power supply conductor layer on the surface of the 18-layer core substrate: 15 / zm The thickness of the power supply conductor layer on the core substrate and the thickness of the conductor layer on the interlayer insulation layer of 815 / zm: 20 / zm • (First embodiment -7) Thickness of the power supply conductor layer on the inner layer of the 4-layer core substrate: 15 # m Thickness of the power supply conductor layer on the surface layer of the 4-layer core substrate: 45 // m Thickness of the power supply conductor layer on the core substrate: 60 / / m Thickness of the conductor layer on the interlayer insulation layer: 20 // in (First Embodiment 8) Thickness of the conductor layer for the inner layer of the 4-layer core substrate: 15 // m For the power supply of the surface layer of the 4-layer core substrate Thickness of the conductor layer: 60 // m The thickness of the conductor layer for the power supply of the core substrate: 75 // m The thickness of the conductor layer on the interlayer insulation layer: 20 / zm 2160-6825-PF; Ahddub 29 200529722 (First Embodiment 9) Thickness of the power conductor layer in the inner layer of the 4-layer core substrate: Thickness of the power supply material layer in the surface layer of the 4-layer core substrate: Thickness of the power supply conductor layer in the claw core substrate: 65 "Thickness of the conductor layer on the insulation layer between claw layers: Do not use claws (First Embodiment 10). The thickness of the power supply turning layer on the inner layer of the four-layer substrate: the thickness of the power supply layer on the surface of the four-layer core substrate: 15_ m The thickness of the conductor layer for the power supply of the core substrate and the thickness of the conductor layer on the interlayer insulating layer: l65 &quot; m. In addition, the film of the "outer insulating layer &quot; m thickness in the foregoing. The manufacturing process uses 300 (first embodiment 11) the thickness of the power supply conductor layer on the inner layer of the 4-layer core substrate: 175_ the thickness of the power supply material layer on the surface layer of the 4-layer core substrate: 15_ the thickness of the power supply conductor layer of the core substrate and : The thickness of the conductor layer on the insulating layer between the layers of melons: 2q In addition, in the above-mentioned &lt; outer insulating layer and the layer &quot; m thickness film. The table uses 300 (first embodiment 1-12) the thickness of the power supply conductor layer on the inner layer of the 4-layer core substrate: 2000_ thickness of the power supply conductor layer on the surface layer of the 4-layer core substrate · i5 "m core substrate power supply The thickness of the conductor layer and: m The thickness of the conductor layer on the interlayer insulation layer: 20 // m This: ': The above-mentioned "outer insulation layer and guide; layer formation" process requires # m thickness of film. (第1 Embodiment 1 13) In the 3rd guan-3 ', the power supply and the shape of the power supply are partly the same as those shown in the <Inner layer gold> 1 layer circuit formation process> of the aforementioned (3) Through-holes with fake end faces. This area is the number of through-holes for power supplies without a fake end face directly below 1C 2160-6825-PF; Ahddub 30 200529722; the target is 50% of the through-holes for full power The number of through-holes for grounding without a dummy end surface is 50/0 relative to the through-holes for full grounding. (First Embodiment 1-14) In the first embodiment 1-3, the total number of parts directly below 1C Power supply through-holes and all-ground through-holes have been used in the above-mentioned (3) "Inner metal layer circuit formation process" (1st embodiment 15) In the first embodiment 1-9, a part of the power supply through-hole and the grounding through-hole becomes the <inner layer metal in (3) above. The layered circuit formation process> shows through-holes without dummy end faces. This area is directly below 1C, and the number of power supply through-holes without dummy end faces Φ is relative to the full-power supply through-holes. It is 50%, and the number of through-holes for grounding without a dummy end surface is 50% relative to the through-holes for full grounding. (First Embodiment 1-16) In 9th Embodiment 1-9, the portion directly below 1C is The through-hole for full power supply and the through-hole for full ground are the through-holes without dummy end faces shown in the above (3) Circuit formation process of the inner metal layer. (First Embodiment 1) 17) In the first embodiment 4 ′, a part of the through-hole for power supply and the through-hole for grounding is shown in the above (3) &lt; Inner layer metal layer circuit forming process> without having a false end face Through-holes. This area is directly below 1C, and the number of through-holes for power supplies without dummy end faces It is 50% with respect to the through hole for full power supply, and 50% of the number of through holes for grounding without a dummy end surface is 50% with respect to the through hole for full ground. (First Embodiment 18) In the first implementation Example 1 4 makes the through-holes for full power supply and the through-holes directly below 1C the through-holes without the dummy end face shown in the above (3) "Circuit Forming Process for the Inner Metal Layer" (First Embodiment 19) In the first embodiment -10, the part of the power supply hole and the grounding through-hole becomes the place described in (the circuit forming process of the inner metal layer) in the aforementioned (3). Shown are through-holes without dummy end faces. This area is directly below 1C, and there are no power supply through holes 31 2160-6825-PF; Ahddub 200529722 The number is 50% compared to the full power supply through holes. The number of holes is 50% with respect to the through-hole for full ground. (First embodiment 1-20) In the first embodiment 1-10, the through-holes for full power supply and through-holes directly below 1C are formed in the "circuit forming process for the inner metal layer" in the above (3). The through hole shown in the figure does not have a fake end face. (First Embodiment 21) In the first embodiment 11, a part of the power supply through-hole and the ground through-hole is shown in the above (3) "Circuit Forming Process of Inner Metal Layer" There is no through hole for the fake end face. This area is directly below 1C. The number of power supply through holes without dummy end faces is 50% of the total power supply through holes. The number of ground through holes without dummy end faces is relative to full ground. It is 50% with a through hole. (First embodiment 22) In the first embodiment 11, the through-holes for the entire power supply and the through-holes directly below the portion 1C are formed in the "circuit forming process for the inner metal layer" in (3) above. The through hole shown in the figure does not have a fake end face. (First embodiment 23) In the first embodiment 12, a part of the power supply via and the ground via is made a part of the &lt; inner-layer metal layer circuit forming process &gt; of the aforementioned (3) Shown are through-holes without dummy end faces. This area is directly below 1C. The number of through-holes for power supply without dummy end faces is 50% relative to the through-holes for full power supply. The number of through-holes for grounding without dummy end faces is relative to full ground. It is 50% with a through hole. (First Embodiment-24) In the first embodiment 12, the through-holes for the entire power supply and the through-holes directly below the 1C are formed in the circuit formation process of the &lt; inner metal layer of the above (3) &gt; The through hole shown in the figure does not have a dummy end surface. (First Embodiment 25) In the first embodiment 7, a part of the power supply through hole and the ground through hole becomes the place in the &lt; the inner metal layer circuit forming process &gt; of the above (3) Shown are through-holes without dummy end faces. This area is directly below 1C, and the number of through-holes for power supply without dummy end face is 2160-6825-PF; Ahddub 32 200529722 is 50% relative to the through-hole for full power supply, and for grounding without dummy end face The number of through holes is 50% with respect to the through holes for all grounding. (First embodiment 26) In the first and seventh embodiment 7, the through-holes for full power supply and the through-holes for full grounding immediately below 1C are the circuits of the inner metal layer described in (3) above. The through hole shown in the process &gt; is not provided with a dummy end surface. (First Embodiment 27) The thickness of the power conductor layer of each inner layer of the 6-layer core substrate: The thickness of the power conductor layer of the 6-layer core substrate surface: 15 &quot; m The thickness of the power conductor layer of the core substrate and: 8 () ^ m φ The thickness of the conductor layer on the interlayer insulation layer: 20 / zm (First Embodiment 28) The thickness of the conductor layer for the power supply on the inner layer of the 4-layer core substrate: The conductor for the power supply on the surface layer of the 4-layer core substrate The thickness of the layer: the thickness of the conductor layer for the power supply of the 15 vm core substrate and the thickness of the conductor layer on the interlayer insulation layer: 20; / m (First Embodiment 29) In the first embodiment -27 'Make electrical A part of the through hole and the through hole for grounding is a through hole without a dummy end surface shown in the above (3) "Circuit forming process of the inner metal layer". This area is directly below the IC, and the number of through-holes for power supply without dummy end faces is hidden from the full power supply hole, and the number of through-holes for grounding without dummy end faces is compared to the through-hole for full ground 50%. (First Embodiment 30) In the first embodiment -29 ′, the through-holes for full power supply and the through-holes directly below 1C are included in the “circuit forming process for the inner metal layer” in the aforementioned (3). Shown are through-holes without dummy end faces. (First Comparative Example _ 1) Thickness of the power supply conductor layer in the inner layer of the 4-layer core substrate: 10 &quot; m Thickness of the power supply conductor layer in the surface layer of the 4-layer core substrate · 10 ^ m Power conductor of the core substrate Layer thickness and 2160-6825-PF; Ahddub 33 200529722 Thickness of the conductor layer on the interlayer insulation layer: 20 (First Comparative Example 1) m 18 inner core substrates for power supply of each inner layer The thickness of the conductor layer for the main electrical body: 100 // 18 layers of the core substrate for the power supply conductor layer: the thickness of the core substrate for the power supply conductor layer and the thickness of the conductor layer on the interlayer insulation layer: 2 〇 ^ m (1st Comparative Example 1) The thickness of the power supply material layer of each inner layer of the 22-layer core substrate: ⑽p The thickness of the power supply conductor layer of the 22-layer core substrate surface layer: the thickness of the 15-core substrate's power conductor layer and : Thickness of the conductor layer on the interlayer insulating layer: 2〇 # m In addition, in the first embodiment, 帛! In the multilayer printed circuit board of the comparative example, there is no description about the connection end surface because all through holes have dummy connection end surfaces. The multilayer printed circuit board of the first embodiment _1 to the first embodiment 1-2, the first embodiment _27, 28, and the ith ratio example 1-1 to the first ratio example ~ 3 is constructed with a frequency of 3 · The 1C chip at 1GHz supplies the same amount of power and measures the voltage drop at startup (equivalent to the third drop of multiple voltage drops). In addition, the IC cannot measure the voltage of 1C directly. Therefore, a measurable circuit is formed on the printed circuit board to measure the voltage of ic. The value of the voltage drop amount at this time is shown in FIGS. 13 and 15. It is the value of the amount of voltage drop that fluctuates when the power supply voltage is 1.0V. In addition, the HAST test (85 ° C, 85 ° C, 1500 ° C) was performed on printed circuit boards of the first embodiment 1 to the first embodiment _12, the first embodiment _28 and the first comparative example 1 to the first comparative example 3. Humidity: 85%, 3.3V applied. In addition, the pattern to be evaluated is a test pattern for insulation resistance evaluation formed on the core substrate. The results are shown in FIG. 13. The test time is Π5 hours, and the insulation resistance value after 115 hours of pass is i0_7q or more. If it is lower than this, it becomes defective 0. In addition, the first, first, third, fourth, seventh, and eighth series are on the printed circuit board. In the production, the evaluation of the minimum line-to-line and line-width forming ability evaluation pattern (refer to the process before the first embodiment 1). This result is shown in FIG. 14 as a formation ability. In Fig. 0, there is no short circuit, and X indicates that there is a short circuit in adjacent wiring. ’2160-6825-PF; Ahddub 34 200529722 • The results of the voltage drop and insulation resistance after HAST for various α 1/0: 2 are shown in Figures 13 and 15. The results after the HAST test indicate that the pass is 0 and the defect is X. Fig. 17 shows the graphs of the voltage drop amounts of various α 1 / α 2 voltages. In the results of FIG. 13 and FIG. 15, if the allowable range of variation is ± 10% (the third voltage drop amount) at the power supply voltage of 1.0 ν, the behavior of the voltage becomes stable, and no 1C chip is caused. Wrong actions, etc. That is, in this state, if the amount of voltage drop is within 0 · IV, erroneous operation of the IC chip due to the voltage drop will not be caused. Therefore, if it is 0.09V or less, stability is increased. Therefore, the ratio (the thickness of the conductor layer for the power supply of the multilayer core substrate and the thickness of the conductor layer on the interlayer insulating layer) can exceed 1 · 0. In addition, if it is in the range of 1.2 $ (the thickness of the conductor layer for power supply of the multilayer core substrate and the thickness of the conductor layer on the interlayer insulating layer 40), it will be within the allowable range of variation. However, when the value exceeds 8.25 , Began to rise, when it is exceeded, the voltage drop is more than 0 · IV. It is speculated that this is because the conductor layer of the multilayer core substrate becomes thicker, or the number of layers in the inner layer is increased, which makes the length of the via hole longer. It takes time for power supply. However, even if (the thickness of the conductor layer for power supply of the multilayer core substrate and / or the thickness of the conductor layer on the interlayer insulation layer) falls within the aforementioned range, only one layer of the conductor layer becomes thicker. The real U and 12 series also make the insulation reliability of the wire board worse than other real === bad (refer to Figure 13). Because of this, we know that not only the i layer becomes thicker, but also how to make multiple layers. The thickness and the thickness of the conductor layer for power supply are within the aforementioned range; It is equipped with 1C at high frequency, and no erroneous operation occurs, which is a seal of good insulation reliability. In addition, the core substrate of the first embodiment-1 and 12 is analyzed. Absolutely The test pattern for evaluation of margins' narrows the interval between the lines. It is presumed that this is the cause and the resistance is lower than the specification. In addition, the comparison between the first and third embodiments of FIGS. 14 and 7 and 8 is also made. It is known that the thickness of the conductive layer on the front and back surfaces of the multilayer core substrate is thinner than the thickness of the inner layer. As this is on the front and back surfaces: thick:, the interlayer agent is undulating because of its influence, so Conduction on the interlayer insulation layer = 2160-6825-PF; Ahddub 35 200529722 The reason for the formation of fine wiring. 28. The first comparative example Ή manufacturing method confirms that the 1C chip is in accordance with the first embodiment 1 For multilayer printed circuit boards of ~ 12, 27, whether there is an error operation will be explained as follows. As a 1C chip, a multilayer printed circuit board selected by any of the following Nos. 1 to 3 will be performed 100 times simultaneously. Switch, whether or not the evaluation is correct: The results are shown in FIG. 15.

No· 1 ··驅動頻率：3. 06GHz、脈衝鎖（fsb) : 533MHz No. 2 ·驅動頻率：3· 2GHz、脈衝鎖（fsb) : 800MHz No· 3 ·驅動頻率·· 3. 46GHz、脈衝鎖（fsb) : 1 〇66MHz 由構裝No· 1之1C晶片之結果而得知：如果α 1/α 2之比率成為 1.2〜40之範圍的話，則在1C並無觀察到錯誤動作。推測這個係由於 電源層之導體電阻變低，因此，瞬間地進行對於IC之電源供應之緣 故。由構裝No· 2之1C晶片之結果而得知：在π之驅動頻率變得更加 咼速度時，必須在更短之短時間，供應電源至Ic，因此，存在更加適 當之範圍。作為在多層芯之内層之導體層變厚之第丨實施例_n、12 或内層之層數目變多之第1實施例—5、6而發生錯誤動作之理由係推 測除了在由於芯基板變厚所造成之電源之供應延遲以外，也可能在訊 號傳達至訊號用通孔（呈電氣地連接至IC訊號電路之通孔（並無圖示）） 之際，發生惡化。在訊號用通孔貫通4層芯之狀態下，該通孔係由上 面開始貫通絕緣層（圖9之表層之電源層和内層之接地層間之絕緣 層）、接地層、絕緣層（圖9之内層之接地層和内層之電源層間之絕緣 層）、電源層、絕緣層（圖9之内層之電源層和背面之接地層間之絕緣 層）。汛號配線係由於周圍之接地或電源之有無等而改變阻抗，因此， 例如以表層之電源層和接地層之間之絕緣層及接地層間之界面，作為 f界而使得阻抗值呈不同。因此，在該界面，引起訊號之反射。即使 是在其他界面，也引起同樣現象。推測此種阻抗之變化量係隨著訊號 用通孔和接地層、電源層間之距離越加接近，接地層、電源層之厚声 越加厚，界面之數目越加多，而變得越大，因此，在第丨實施例〜广 2160-6825-PF;Ahddub 36 200529722 • 6、11、12，發生錯誤動作（訊號用通孔及其周圍之電源層、接地層、 絕緣層之示意圖和訊號反射之界面（XI、X2、X3、X4)係也顯示於圖 39)。此外，推測第1實施例一1、2之錯誤動作之理由係由於電源層 之厚度和變少之緣故。 此外’由構裝N 〇 · 3之IC之結果而付知·在IC還更加進行高速度 化時，在内層具有厚導體層並且α 1/α 2成為3〜7之4層芯係變得有 效。推測這個係由於能夠同時達成在短時間之電源供應和訊號惡化之 防止之緣故。此外，由第1實施例一 3、4和第1實施例〜7、8之比較 而得知：呈電氣地在内層配置厚導體層者係變得有利。推測這個係由 於在内層具有厚導體層，因此，由於電源用通孔和内層之接地層間及 •接地用通孔和内層之電源層間之相互作用而使得電感變小之緣故。 就按照第1實施例一 13〜26所製造之多層印刷電路板而言，藉由 以下說明之方法而確認在搭載之1C晶片是否有錯誤動作。 作為1C晶片係將由以下之No. 1〜3所選出之任何一種ic晶片構 裝於各個多層印刷電路板，同時，進行100次之開關，評價有無錯誤 動作。 將這些結果，顯示在圖16。在圖中之所使用之TH係通孔之縮寫。No · 1 ·· Drive frequency: 3. 06GHz, pulse lock (fsb): 533MHz No. 2 · Drive frequency: 3. 2GHz, pulse lock (fsb): 800MHz No · 3 · Drive frequency · 3. 46GHz, pulse Lock (fsb): 1.066 MHz It is known from the result of constructing the No. 1 1C chip that if the ratio α 1 / α 2 is in the range of 1.2 to 40, no erroneous operation is observed at 1C. It is presumed that this is because the conductor resistance of the power supply layer becomes low, so that the power supply to the IC is performed instantaneously. From the results of constructing the No. 2 1C chip, it is known that when the driving frequency of π becomes faster, the power must be supplied to Ic in a shorter period of time. Therefore, there is a more appropriate range. The first embodiment, which is a thicker conductor layer in the inner layer of a multilayer core, _n, 12 or the first embodiment in which the number of inner layers is increased-5, 6, and the reason for the erroneous operation is presumed to be in addition to In addition to the delay in the power supply caused by the thickness, the signal may be deteriorated when the signal is transmitted to the signal via (which is electrically connected to the IC signal circuit via (not shown)). In the state where the signal uses a through-hole to penetrate the 4-layer core, the through-hole starts to penetrate the insulation layer (the insulation layer between the power layer on the surface layer and the ground layer on the inner layer), the ground layer, and the insulation layer (Figure 9). Insulation layer between inner ground layer and inner power supply layer), power layer, insulation layer (insulation layer between inner power layer and back ground layer in Figure 9). The flood number wiring system changes the impedance due to the surrounding ground or the presence or absence of a power source. Therefore, for example, the interface between the insulation layer between the power supply layer and the ground layer on the surface layer and the ground layer is used as the f-boundary to make the impedance values different. Therefore, reflection of the signal is caused at this interface. The same phenomenon occurs even at other interfaces. It is speculated that the amount of change in this impedance is as the distance between the signal via and the ground plane and the power plane gets closer, the thicker the sound of the ground plane and the power plane becomes thicker, the more the number of interfaces becomes, and the larger it becomes. Therefore, in the first embodiment ~ Guangdong 2160-6825-PF; Ahddub 36 200529722 • 6, 11, 12, erroneous operation (signal vias and the surrounding power supply layer, ground layer, insulation layer diagram and signal The reflection interfaces (XI, X2, X3, X4) are also shown in Figure 39). In addition, it is presumed that the reason for the erroneous operation of the first and second embodiments is that the thickness and the thickness of the power supply layer are reduced. In addition, it is known from the results of constructing ICs of No. 0.3. When the IC is further increased in speed, it becomes effective to have a thick conductor layer in the inner layer and α 1 / α 2 to become a 4-layer core system of 3 to 7 . It is speculated that this is because the power supply and the signal deterioration prevention in a short time can be achieved at the same time. In addition, it is known from the comparison of the first embodiment 3, 4 and the first embodiment to 7, 8 that it is advantageous to arrange a thick conductive layer electrically on the inner layer. It is presumed that this is because the inner layer has a thick conductor layer. Therefore, due to the interaction between the power supply via and the ground layer of the inner layer and the interaction between the ground via and the power layer of the inner layer, the inductance is reduced. With regard to the multilayer printed circuit boards manufactured in accordance with the first to thirteenth to twenty-sixth embodiments of the first embodiment, whether or not there is an erroneous operation on the mounted 1C chip is checked by the method described below. As the 1C chip, any one of the IC chips selected from the following Nos. 1 to 3 was mounted on each multilayer printed circuit board, and at the same time, it was switched 100 times to evaluate the presence or absence of erroneous operation. These results are shown in FIG. 16. The TH used in the figure is the abbreviation of the through hole.

No· 1 :驅動頻率：3. 06GHz、脈衝鎖（FSB) : 533MHz No· 2 :驅動頻率：3. 2GHz、脈衝鎖（FSB) : 800MHz No· 3 :驅動頻率：3· 46GHz、脈衝鎖（FSB) ·· 1066MHz 在比較第1實施例一10、27和第1實施例—19、20、29、30時而 得知：藉由成為不具有假接端面之通孔而不容易發生IC之錯誤動作。 推測這個係由於不具有假接端面之部分、電位相反之通孔和内層之導 體層呈接近，因此，減少相互電感之緣故。或者是推測這個係由於電 流容易流動在導體之表面，因此，無假接端面之部分、電氣流動之配 線長度變短之緣故。 將第1實施例-3、4、13、14、17、18、28之印刷電路板，放 在高溫.高濕度⑻度.85%)之環境下1〇〇小時。然後，在各 =路板，構裝前述Nq.3之K晶片，進行同時開關，確認有無錯誤動 作。除了帛！實施例-3以外，並無錯誤動作發生。由於高溫高渴 2160-6825-PF;Ahddub 37 200529722 度試驗而使得導體層之電阻變大，因此，推測在第1實施例一 3，發生 錯誤動作。推測也相同於其他實施例，電阻係上升，但是，相對於第 1實施例一3，其他係導體層之厚度變厚，或者是成為不具有假接端面 之通孔，因此，電感係更加低於第1實施例一3，所以，不發生錯誤動 作。因此，認為内層之導體層之厚度係還最好是60/zm〜125/zm。能 夠由以上而推測：在成為多層芯時，成為不具有内層之導體厚度和假 接端面之通孔者係相互地發生互相之影響。 B.第2實施例 參考圖18〜圖25而就本發明之第2實施例一1之多層印刷電路 板，來進行說明。 首先，就第2實施例一 1之多層印刷電路板10之構造而言，參考 圖22、圖23而進行說明。圖22係顯示該多層印刷電路板1〇之剖面 圖，圖23係顯示在圖22所示之多層印刷電路板10安裝ic晶片9〇 而載置至標點器板9 4之狀態。正如圖2 2所示’在多層印刷電路板1 〇， 使用多層芯基板30。在多層芯基板30之表背面，形成訊號電路ms、 電源電路34P、地線電路34E。此外，在多層芯基板30内部之表面側， 形成内層之地線電路16E及訊號電路16S1，在背面，形成電源電路16p 及訊號電路16S2。上側之地線電路16E係形成作為地線用平面層， 侧之電源電路16P係形成作為電源用平面層。平面層係可以僅 之單層，也可以配置成為2層以上。最好是藉由2層〜4層所則 在超過4層時，芯之厚度變厚，因此，並無確認電氣特性^ ^战。 以’即使是成為這個以上之多層，也使得其效果成為相同於:所 等程度。相反地，也有惡化之狀態發生。特別是由於藉著2 =问 者係在所㈣孔長度變短之方面和多層芯基板之剛㈣ 2形成 得基板之延伸率呈—致，因此，不容易出現f曲之緣故。此外使 在多層芯基板30之中央，收納呈電翕士 可以 發揮作為芯材之功能，但是’並無進行通孔或導通孔df也 主要提高對於綱曲之剛性。多層芯基板3。係透過呈二=。 1C訊號電路、地線電路和電源電路之 電虱地連接於 通孔观、電源用通孔36P而得到内層及S面側和背面側2之=用 2160-6825-PF;Ahddub 38 200529722 在多層芯基板30表面之導體電路34P、地線電路34E、訊號電路 34S之上面，配置形成導通孔60和導體電路58之層間樹脂絕緣層50 以及形成導通孔160和導體電路158之層間絕緣層150。在該導通孔 160和導體電路158之上層，形成銲錫阻劑層70，透過該銲錫阻劑層 70之開口部71，而在導通孔160及導體電路158,形成凸塊76U、76D。 正如在圖23中之所顯示的，多層印刷電路板1〇之上面側之錫船 凸塊76U係連接至1C晶片90之接端面92。此外，還構裝晶片電容器 98。另一方面，下側之外部端子76D係連接至標點器板94之接端面 96。該狀態下之所謂外部端子係指PGA、BGA、錫鉛凸塊等。 圖25(A)係顯示圖22中之X3 — X3橫剖面、也就是内層之地線用 •平面層16E之平面，圖25(B)係顯示X2 — X2橫剖面、也就是内層之電 源用平面層16P之平面。在此，圖22和圖25(A)、（B)係配置並無一 致者，圖22係用以呈示意地顯示多層印刷電路板之縱向構造。 正如圖25(A)所示，在多層印刷電路板30，在電源用通孔36P貫 通多層芯之内層之地線用平面層16E之時，在地線用平面層16E之内， 電源用通孔36P係不具有由該通孔開始延出之接端面等之導體電路。 電源用通孔36P係配置在地線用平面層i6E所設置之拉拔部35。正如 圖25(B)所示，該地線用通孔36E係也相同於貫通電源用平面層i6p 之地線用通孔36E，在地線用通孔36E貫通内層之電源用平面層16p 之時，在電源用平面層16P之内，使得地線用通孔36E配置在拉拔部 • 35内，不具有由該通孔開始延出之接端面等之導體電路。可以藉由成 為此種芯構造而使得電源用通孔和地線用通孔間、芯水平方向之電源 用通孔和地線用平面層間、以及芯水平方向之地線用通孔和電源用^ 面層間之間之間隔變得狹窄，可以減少相互電感。此外，通孔^不具 有假接端面，因此，可以使得電源用平面層和地線用平面層之導體^ 積變多。可以藉此而參考圖28、圖29,來減少前述第丨次^ 次之 電壓下降，因此，不容易引起電源不足，結果，即使是構裝=言 頻區域之1C晶片，也不引起初期啟動之錯誤動作或錯誤等。冋同 在圖25,多層芯基板之通孔係成為交互地配置電源用 地線用通孔36E：之構造。由於可以藉由成為此種交互 口 夏而減少相互 2160-6825-PF；Ahddub 39 200529722 電感，減少第1次和第2次之電壓下降之緣故。 但是，不一定需要全部交互地進行配置，不 _ 此如圖31(A)、圖31(B) 所示，一部分之電源用通孔和地線用通孔間传、 正如圖31(A)所示，在電源用通孔36P、36P相互^相互地進打鄰接。 々日互鄰接夕妝能下，可η 在地線用平面層16Ε内，藉由電源電路16Ρ1而連 a α 不連接兩者而在拉拔部35中形成通孔36Ρ。正；θ兩者’並且’能夠 如圖31 ( Β )所示，也相 同於地線用通孔36Ε間相互鄰接之狀態。形成於知κ ^ 拉拔部35者係增加平 面層之導體面積，因此，變得理想。 I⑸亦作曰刀口十 訊Μϋ孔係並無連接於電源用平_ 16p和地線用平No · 1: Driving frequency: 3.06 GHz, pulse lock (FSB): 533 MHz No · 2: Driving frequency: 3.2 GHz, pulse lock (FSB): 800 MHz No · 3: Driving frequency: 3. 46 GHz, pulse lock ( FSB) ····················································································· 1066 Wrong action. It is presumed that this is because the portion without the dummy end surface, the through hole with the opposite potential, and the conductor layer of the inner layer are close, so the mutual inductance is reduced. Or it is presumed that this is because the electric current easily flows on the surface of the conductor, and therefore, the length of the wiring for the electric flow is shortened in the part without the false end surface. The printed circuit boards of the first embodiment-3, 4, 13, 14, 17, 18, and 28 were placed in an environment of high temperature, high humidity, and 85%) for 100 hours. Then, the K wafer of Nq.3 is constructed on each circuit board, and the simultaneous switching is performed to check whether there is an error operation. Except 帛! Except for Example-3, no malfunction occurred. Due to the high temperature and high thirst 2160-6825-PF; Ahddub 37 200529722 degree test, the resistance of the conductor layer is increased. Therefore, it is presumed that in the first embodiment 1 to 3, an erroneous operation occurs. It is speculated that the resistance system is also the same as in the other embodiments. However, compared to the first embodiment 1 and 3, the thickness of the conductor layer of the other systems is thickened, or it is a through hole without a dummy end surface. Therefore, the inductance system is lower. Since the first embodiment is 3, no erroneous operation occurs. Therefore, it is considered that the thickness of the inner conductor layer is preferably 60 / zm to 125 / zm. It can be inferred from the above that when a multilayer core is used, the thickness of the conductor without the inner layer and the through-hole of the dummy end face mutually affect each other. B. Second Embodiment A multilayer printed circuit board according to a second embodiment of the present invention will be described with reference to Figs. 18 to 25. Figs. First, the structure of the multilayer printed wiring board 10 according to the first embodiment 1 will be described with reference to Figs. 22 and 23. 22 is a cross-sectional view showing the multilayer printed circuit board 10, and FIG. 23 is a view showing a state where the IC chip 90 is mounted on the multilayer printed circuit board 10 shown in FIG. As shown in FIG. 22, in a multilayer printed circuit board 10, a multilayer core substrate 30 is used. On the front and back surfaces of the multilayer core substrate 30, a signal circuit ms, a power supply circuit 34P, and a ground circuit 34E are formed. In addition, an inner layer ground circuit 16E and a signal circuit 16S1 are formed on the surface side inside the multilayer core substrate 30, and a power supply circuit 16p and a signal circuit 16S2 are formed on the back surface. The upper ground circuit 16E is formed as a plane layer for ground, and the power circuit 16P on the side is formed as a plane layer for power. The planar layer may be a single layer, or may be arranged in two or more layers. It is best to use two to four layers. When more than four layers are used, the thickness of the core becomes thicker. Therefore, the electrical characteristics are not confirmed. Even if 'is to become more than this multilayer, the effect is the same as: to the same degree. On the contrary, there is also a state of deterioration. In particular, since the length of the hole to be shortened is reduced by 2 = question, and the elongation of the substrate formed by the rigid core 2 of the multilayer core substrate is the same, it is not easy to cause f-curves. In addition, in the center of the multi-layered core substrate 30, an electrician can be accommodated to function as a core material. However, the absence of through holes or via holes df mainly improves rigidity with respect to the outline. Multi-layer core substrate 3. It is through two =. The electrical ground of the 1C signal circuit, ground circuit and power circuit is connected to the through hole view and the power supply through hole 36P to get the inner layer and the S side and the back side 2 = 2160-6825-PF; Ahddub 38 200529722 in multiple layers Above the conductor circuit 34P, the ground circuit 34E, and the signal circuit 34S on the surface of the core substrate 30, an interlayer resin insulation layer 50 forming a via 60 and a conductor circuit 58 and an interlayer insulation layer 150 forming a via 160 and a conductor circuit 158 are disposed. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76U and 76D are formed in the via hole 160 and the conductor circuit 158 through the opening portion 71 of the solder resist layer 70. As shown in FIG. 23, the tin boat bump 76U on the upper side of the multilayer printed circuit board 10 is connected to the connection end surface 92 of the 1C chip 90. In addition, a chip capacitor 98 is constructed. On the other hand, the external terminal 76D on the lower side is connected to the end face 96 of the marker plate 94. The so-called external terminals in this state refer to PGA, BGA, tin-lead bumps, and the like. Fig. 25 (A) shows the X3-X3 cross section in Fig. 22, which is the ground plane of the inner layer. The plane of the plane layer 16E. Fig. 25 (B) shows the X2- X2 cross section, which is the power supply of the inner layer. The plane of the plane layer 16P. Here, FIGS. 22 and 25 (A) and (B) are inconsistent in arrangement, and FIG. 22 is used to schematically show the vertical structure of the multilayer printed circuit board. As shown in FIG. 25 (A), in the multilayer printed circuit board 30, when the power supply through-hole 36P penetrates the ground plane layer 16E of the inner layer of the multilayer core, the power supply is routed through the ground plane layer 16E. The hole 36P does not have a conductor circuit such as a contact end surface extending from the through hole. The power supply through-hole 36P is arranged in the drawing portion 35 provided in the ground plane layer i6E. As shown in FIG. 25 (B), the through-hole 36E for the ground wire is also the same as the through-hole 36E for the ground wire penetrating through the power plane plane i6p, and the through-hole 36E for the ground wire penetrates the inner plane power plane plane 16p. In this case, the ground plane through-hole 36E is arranged in the drawing part 35 within the power plane layer 16P, and there is no conductor circuit such as a connection end surface extending from the through-hole. By forming such a core structure, it is possible to make the power supply through hole and the ground line through hole, the core horizontal direction through the power supply hole and the ground line between the ground layers, and the core horizontal direction the ground line through hole and the power supply. ^ The space between the surface layers becomes narrower, which can reduce mutual inductance. In addition, the through hole ^ does not have a dummy end surface, so that the conductor ^ product of the planar layer for power and the planar layer for ground can be increased. You can use this to refer to Figure 28 and Figure 29 to reduce the aforementioned voltage drop for the first ^ th time. Therefore, it is not easy to cause power shortage. As a result, even the 1C chip with the structure = speech frequency area does not cause the initial startup. Wrong actions or errors. Differently, in FIG. 25, the through-holes of the multilayer core substrate have a structure in which the through-holes 36E for power ground are alternately arranged. Because it can reduce the mutual 2160-6825-PF by becoming such an interface, the inductance of Ahddub 39 200529722 can reduce the first and second voltage drop. However, it is not necessary to configure all of them interactively. No_ This is shown in Figure 31 (A) and Figure 31 (B). Some of the power supply vias and ground wires are passed between them, as shown in Figure 31 (A). As shown, the power supply through-holes 36P, 36P are adjacent to each other. On the next day, under the condition of mutual makeup, the through-hole 36P can be formed in the drawing portion 35 in the ground plane layer 16E through the power supply circuit 16P1, but not connected to a α. Positive; both θ and θ can be in a state where the through-holes 36E for ground lines are adjacent to each other as shown in FIG. 31 (B). The formation of the kappa ^ drawing portion 35 is preferable because it increases the conductor area of the planar layer. I⑸ also said that the knife edge is not connected to the power supply flat _ 16p and ground

16E，因此’並不需要在電源用平面層16P和地線用平面層内，* 置由該通孔開始延出之導體電路，但是，如果有進行電路形成之空ς 的話，則即使是在任何-種平面層，也可以進行電路形成。在藉由芯 而配置訊號電路時，在藉㈣層之層來進行料時，有册微細化用。 此外，多層芯基板30之導體厚度係最好是内層之導體厚度成為表 層之導體厚度以上。多層芯基板30表層之電源電路34ρ、地線電路 34Ε、訊號電路34S係形成為厚度10〜60//m，内層之電源電路16f)、 地線電路16E、訊號電路16S1、16S2係形成為厚度1〇〜25〇#m，層間 絕緣層50上之導體電路58及層間樹脂絕緣層150上之導體電路 係形成為5〜25//m。多層芯基板内層之導體電路之厚度係更加理想是 多層芯基板表背面之導體電路之厚度之2倍以上。 &quot; 在第2實施例一1之多層印刷電路板，藉由使得多層芯基板3〇之 電源層（導體層）34P、地線電路34E、訊號電路34s、内層之電源電路 16P和地線電路16E變厚而增加多層芯基板之強度。即使是藉此而使 得多層芯基板本身變薄，也能夠藉由基板本身而緩和、彎曲或發生之靡 力。 此外，可以藉由使得訊號電路34S、電源電路34p、地線電路34E、 電源電路16P和地線電路16E變厚而增加導體本身之體積。可以藉由 增加其體積而減低在導體之電阻。 此外，可以藉由使用電源電路34P、16P來作為電源層而提高電源 對於1C晶片90之供應能力。因此’可以在該多層印刷基板上構裝π 2160-6825-PF;Ahddub 40 200529722 /晶f時，減低Ic晶片〜基板〜電源為止之迴路電感。因此，初期動作 3次之電源下降變小，所以，不容易引起電源不足，結果，即使 是，此而構裝高頻區域之IC晶片，也不引起初期啟動之錯誤動作或錯 誤=。此外)可以藉由使用地線電路34E、16E來作為地線層，而在 Ij晶片之訊2虎、電力供應，不重疊雜訊，防止錯誤動作或錯誤。可以 藉由構裝電容器而呈辅助地使用電容器内之所儲存之電源，因此，不 谷易、引起電源不足。特別是藉由配置於Ic晶片之正下方而使得其效果 (不谷易引起電源不足）顯著地變好。作為其理由係由於如果是IC晶片 之正下方的話，則能夠使得在多層印刷電路板之配線長度變短之緣故。 在第2實施例一1，多層芯基板30係在内層具有厚電源電路16P i和地線電路16E，在表面具有薄電源電路34P和地線電路34E，使用内 層之電源電路16P、地線電路16E和表面之電源電路34p和地線電路 34E，來作為電源層用之導體層和地線用導體層。也就是說，即使是在 内層側，配置厚電源電路16P和地線電路16E，也形成覆蓋導體電路 之絕緣層。因此，可以藉由導體電路成為起因，抵銷凹凸，而使得多 層怒基板30之表面變得平坦。因此，為了在層間絕緣層5〇、ι5〇之導 體層58、158不產生起伏，所以，即使是在多層芯基板3〇之表面，配 置薄電源電路34P和地線電路34E，也能夠以足夠於内層之電源電路 16P和地線電路16E之厚度，來確保作為芯導體層之充分之厚度。由 於不產生起伏，因此，在層間絕緣層上之導體層之阻抗，不引起意外。 •可以藉由使用電源電路16P、34P來作為電源層用導體層，使用地線電 路16E、34E來作為地線用導體層，而改善多層印刷電路板之電氣特 性。此外，正如圖34所示，由於增大電位相反之通孔和内層導體層之 對向面積（對向距離），因此，還可以更加改善電氣特性。 此外’使得多層芯基板内層之電源電路16P、地線電路之厚 度更加厚於層間絕緣層5〇、150上之導體電路58、158。可以藉此， 而即使是在多層芯基板30之表面配置薄地線電路34E、電源電路34p， 也足夠於内層之厚電源電路16P和地線電路16E，來確保作為芯導體 層之充分之厚度。其比率係最好是κ(芯内層之導體電路之厚度/層間 絕緣層之導體電路之厚度）$40。更加理想是1.2S(芯内層之導體電 2160-6825-PF；Ahddub 41 200529722 :路之厚度/層^絕緣層之導體電路之厚度）獨。 16P間之卜訊由在多層芯基板内，配置電源電路34&quot;口電源電路 電路16E&amp;㈣成微型帶構造。同樣地，可以藉由配置地線 16P)而步成微型34E間之訊號線（並無圖示、相同層於電源電路 到阻^整人Γ籌造。可以藉由形成微型帶構造而也降低電感，得 ΪΪ4二，，可以使得㈣特性也進行穩定化。 90之正下方:：第2實施例一1之變化例。在該變化例，在IC晶片 離變Γ接近τ己置電容器98。因此，IC晶片90和電容器98間之距 離灰仔，近：可以防止電源供應至1C晶片90之電壓下降。 赢圖18接tin22所示之多層印刷電路板1〇之製造方法而言，參考 •圖18〜圖23而進行說明。 C·多層印刷電路板之製造 多層芯基板之製作 物0·6_之玻璃環氧樹脂或Βτ(雙馬來酸肝縮亞胺三 ，泊基板10,來作為起始材料（圖18(A)) 30//m之銅箔。 甘罘z貫施例I优《 类面著1 ϋ由減法器法而在銅箱16，使得1C正下方，正如顯示 ί=θΓΓϋ所示，在拉拔部35内，形成不具有假接端面之導體 Ϊ:接端面之不背面側之圖19⑻所示’在拉拔部35，形成不具 制又在入邻之;^電路16P。作為參考係在圖38顯示習知例。在習知 例，在全部之拉拔部35，存在由假接端面⑽ 該電路16DD内，形成诵；ffl、S3I QR 丨傅风i电路π仙你 卹m m、S j 在形成通孔之位置，形成拉拔 巾作又接端面16D所構成之電路1_係相對於通孔直 t而以= 〜25〇&quot;m直徑所形成，因此，可以藉由成為不具有假接 知面之導體電路’而相對於具有假接端面之通常之構造，來使得通孔 間及電源用通孔和地線用導體層間（圖34中之χ)、地線用通孔和電源 用導體層間之間隔變得狹窄。像這樣，可以藉由不設置假接端面，而 減少相互電感或者是降低導體電阻。此外，増加能夠形成電源層、地 線層之區域。 2160-6825-PF;Ahddub 42 200529722 ； (3)然後，對於該基板，進行以包含NaOH(10g/l)、NaCl〇2(40gM) 和Na3P〇4(6g&gt;/l)之水溶液作為黑化浴（氧化浴）之黑化處理以及將包含 NaOH(10g/l)和NaBH4(6g/l)之水溶液作為還原浴之還原處理，在下層 導體電路16E、16S1、16P、16S2之表面，形成粗化面16α (圖18(c))。 (4)在如述基板之兩面’以200“ m厚度之膠片18和18//m厚度之 銅箔20之順序，來進行層積，然後，進行加熱及加壓沖裁而製作4 層之多層芯基板30(圖18(D))。膠片之厚度係配合於銅箔16之厚度而 進行變更。 (5)對於該多層芯基板30進行鑽孔削孔，穿設通孔用通孔36(圖 20(A))。然後，藉由施行無電解電鍍及電解電鍍，蝕刻成為圖案狀， 修而在多層芯基板之表背面，形成導體電路34S、34p、34E及25〇&quot;m 直徑之訊號用通孔36S(並未圖示）、電源用通孔36p、地線用通孔 36E(圖 20(B))。 (6)使得在多層芯基板之表背面形成導體電路34S、34p、34E及通 孔 36S、36P、36E 之基板，進行以包含 Na〇H(1〇g/1)、NaC1〇2(4〇g/1) 和Na3P〇4(6g/l)之水溶液作為黑化浴（氧化浴）之黑化處理以及將包含 NaOH(10g/l)和NaBH4(6g/l)之水溶液作為還原浴之還原處理，在上層 導體電路和通孔之表面，形成粗化面34点（圖2〇(c))。 (Ό接著’在使用擦乾器而將相同於前述第1實施例一1所作成之 通孔填充用樹脂組成物40填充於導體電路34S、34p、34E間及通孔 =、36P、36E内之後，以職、2〇分鐘之條件，來進行乾燥（圖 1 A))藉由對於該基板30之表面來進行研磨及平坦化露出導體電 μ面及通孔之接端面…m，崎在小時及露在出= 】時之加熱㈣成硬化通孔填充用樹脂組成物40之樹脂填充材料 層，成為通孔36S(並無顯示）、36ρ、36Ε(圖21(Β))。 、 ,4:2 =表：面之鋼厚度係形成為7.5〜7〇_。像這樣，多 面之銅厚度係適合比起内層之銅厚度還變得更加薄。 在第2實她例一 1，成為25 v m。 可以藉此，而使得表背層比起内層還形成更加 使得通孔接端面之小徑化和導體電路間或者是通孔接端二:路 2160-6825-PF;Ahddub 43 200529722 ==:窄:::?通孔接端面或導體電路係並不會成為 ⑻藉由在對於前述基板來騎錢及雜職後，崎㈣刻， 接著’利用«n，來隸刻液吹附在基板之兩面，對於4 34S、電源電路34P、地線電路34E之表面和通孔36之接端面之^面， 進行姓刻’而在導體電路之全表面，形成粗化面36召（圖2i(c))。作 為蝕刻液係使用由咪唑銅（Π)配位化合物1〇重量份、乙二醇酸7 3 重量份和氣化鉀5重量份所構成之蝕刻液（Mekkul&gt;/製' Mekkuetchbond)。 以後之製程係參考圖5〜圖7而相同於前述第！實施例，因 #此’省略說明。但是，導體電路58、158之厚度係調整電錢時間而成 為 15 // m 〇 [第2實施例一2] 第2實施例一1係使得存在不具有由通孔開始延出之導體電路之 通孔之區域，成為1C正下方，但是，在第2實施例一2，正如以下而 進行變更。除了這個以外之部分係相同於第2實施例一！。 圖26(A)係顯示4層芯之内層之代表性之地線層之橫剖面，圖26(幻 係顯示4層芯之内層之代表性之電源層之橫剖面。16E, therefore, 'It is not necessary to place the conductor circuit extending from the through hole in the power plane layer 16P and the ground plane layer. However, if there is a space for circuit formation, even Any kind of planar layer can also be used for circuit formation. When the signal circuit is configured by the core, there is a book for miniaturization when the material is borrowed from the layer of the tritium layer. In addition, the conductor thickness of the multilayer core substrate 30 is preferably such that the conductor thickness of the inner layer becomes the conductor thickness of the surface layer or more. The power circuit 34ρ, ground circuit 34E, and signal circuit 34S on the surface of the multilayer core substrate 30 are formed to a thickness of 10 to 60 // m, and the inner power circuit 16f), the ground circuit 16E, and the signal circuits 16S1 and 16S2 are formed to a thickness 10 ~ 25〇 # m, the conductor circuit 58 on the interlayer insulation layer 50 and the conductor circuit on the interlayer resin insulation layer 150 are formed to 5 ~ 25 // m. The thickness of the conductor circuit in the inner layer of the multilayer core substrate is more preferably more than twice the thickness of the conductor circuit on the front and back surfaces of the multilayer core substrate. &quot; In the multilayer printed circuit board of the first embodiment 1, the power supply layer (conductor layer) 34P, the ground circuit 34E, the signal circuit 34s, the inner power circuit 16P and the ground circuit of the multilayer core substrate 30 16E becomes thicker to increase the strength of the multilayer core substrate. Even if the multi-layer core substrate itself is made thin by this, the substrate itself can be used to ease, bend, or generate excessive forces. In addition, the volume of the conductor itself can be increased by making the signal circuit 34S, the power circuit 34p, the ground circuit 34E, the power circuit 16P, and the ground circuit 16E thick. The resistance in the conductor can be reduced by increasing its volume. In addition, by using the power supply circuits 34P and 16P as the power supply layer, the power supply capability of the 1C chip 90 can be improved. Therefore, when π 2160-6825-PF; Ahddub 40 200529722 / crystal f can be mounted on the multilayer printed circuit board, the loop inductance from the IC chip to the substrate to the power source can be reduced. Therefore, the power drop in the initial three operations becomes smaller, so it is not easy to cause power shortage. As a result, even if the IC chip is configured in the high-frequency region, it does not cause the wrong operation or error in the initial startup. In addition, by using the ground circuit 34E, 16E as the ground layer, the I2 chip and the power supply can be used without overlapping noise to prevent erroneous actions or errors. Since the power stored in the capacitor can be used auxiliaryly by constructing the capacitor, it is not easy to cause power shortage. In particular, the effect is significantly improved by arranging it directly below the IC chip. The reason for this is that if it is directly below the IC chip, the wiring length on the multilayer printed circuit board can be shortened. In the second embodiment 1, the multilayer core substrate 30 has a thick power circuit 16P i and a ground circuit 16E on the inner layer, and a thin power circuit 34P and a ground circuit 34E on the surface. The inner power circuit 16P and the ground circuit are used. 16E and the surface power circuit 34p and the ground circuit 34E serve as the conductor layer for the power layer and the conductor layer for the ground. That is, even if the thick power circuit 16P and the ground circuit 16E are arranged on the inner layer side, an insulating layer covering the conductor circuit is formed. Therefore, the surface of the multi-layered substrate 30 can be made flat by cancelling the unevenness by the cause of the conductor circuit. Therefore, in order to prevent undulations in the conductor layers 58 and 158 of the interlayer insulating layers 50 and 50, even if the thin power circuit 34P and the ground circuit 34E are arranged on the surface of the multilayer core substrate 30, it is possible to sufficiently The thicknesses of the power supply circuit 16P and the ground circuit 16E in the inner layer ensure a sufficient thickness as the core conductor layer. Since no undulation occurs, the impedance of the conductor layer on the interlayer insulation layer does not cause accidents. • The electrical characteristics of the multilayer printed circuit board can be improved by using the power supply circuits 16P and 34P as the conductor layer for the power supply layer and the ground circuit 16E and 34E as the conductor layer for the ground line. In addition, as shown in FIG. 34, since the opposing areas (opposite distances) of the through-holes and the inner conductor layers with opposite potentials are increased, the electrical characteristics can be further improved. In addition, the thickness of the power circuit 16P and the ground circuit in the inner layer of the multilayer core substrate is thicker than the conductor circuits 58 and 158 on the interlayer insulation layers 50 and 150. With this, even if the thin ground circuit 34E and the power supply circuit 34p are arranged on the surface of the multilayer core substrate 30, it is sufficient for the thick power supply circuit 16P and the ground circuit 16E of the inner layer to ensure a sufficient thickness as the core conductor layer. The ratio is preferably κ (thickness of the conductor circuit inside the core / thickness of the conductor circuit between the interlayer insulation layers) $ 40. More ideally, it is 1.2S (conductor of the inner layer of the core 2160-6825-PF; Ahddub 41 200529722: thickness of the road / thickness of the conductor circuit of the insulation layer) alone. The message between 16P is constructed by arranging a power supply circuit 34 &quot; port power supply circuit 16E & Similarly, the signal line between the miniature 34E (not shown, the same layer on the power circuit to the resistor) can be constructed by configuring the ground wire 16P). It can also be reduced by forming a micro-belt structure The inductance can be stabilized by ΪΪ42, which can stabilize the ㈣ characteristics. Right below 90: A modified example of the second embodiment-1. In this modified example, the capacitor Γ approaches the τ capacitor 98 in the IC chip. Therefore, the distance between the IC chip 90 and the capacitor 98 is gray, which is close: it can prevent the power supply from falling to the voltage of the 1C chip 90. For the manufacturing method of the multilayer printed circuit board 10 shown in FIG. 18 followed by tin22, refer to • Figure 18 to Figure 23. C. Multilayer Printed Circuit Board Manufacturing Multilayer Core Substrate Fabrication Product 0 · 6_ Glass Epoxy Resin or Βτ (bismaleate triimide III, Poise substrate 10, to As a starting material (Fig. 18 (A)) 30 // m copper foil. Ganzun z Guan Example I Excellent "Similar surface 1 ϋ by the subtractor method in the copper box 16, so that 1C is directly below, as shown As shown in ί = θΓΓϋ, a conductor without a dummy end face is formed in the drawing portion 35: the back face of the end face is not formed. As shown in FIG. 19 (a), in the drawing portion 35, an unregulated and adjacent neighbor is formed; circuit 16P. As a reference system, a conventional example is shown in FIG. 38. In the conventional example, in all the drawing portions 35, The circuit is formed by falsely connecting the end face to the circuit 16DD; ffl, S3I QR 丨 Fu Feng i circuit π centimeter mm, S j at the position where the through hole is formed, a drawing towel is formed and the end face 16D is formed. 1_ is formed with a diameter of ~~ 25〇 &quot; m with respect to the through hole straight t. Therefore, it can be compared with a normal structure having a dummy end surface by becoming a conductor circuit without a dummy contact surface. In order to narrow the gaps between the through-holes, the power supply through-holes and the ground conductor layer (χ in Figure 34), and the ground-line through-holes and the power conductor layer, the gaps can be narrowed. 2160-6825-PF; Ahddub 42 200529722; (3) Then, for the substrate, the NaOH ( 10g / l), NaClO2 (40gM) and Na3P〇4 (6g> / l) Blackening treatment of the bath (oxidation bath) and reduction treatment using an aqueous solution containing NaOH (10g / l) and NaBH4 (6g / l) as a reduction bath, forming rough surfaces on the lower conductor circuits 16E, 16S1, 16P, 16S2. Surface 16α (Fig. 18 (c)). (4) Lamination is performed on both sides of the substrate in the order of 200 "m film 18 and 18 // m copper foil 20, and then, A four-layer multilayer core substrate 30 is produced by heating and press punching (FIG. 18 (D)). The thickness of the film is changed in accordance with the thickness of the copper foil 16. (5) The multilayer core substrate 30 is drilled and drilled, and a through hole 36 for a through hole is drilled (Fig. 20 (A)). Then, by performing electroless plating and electrolytic plating, etching is performed into a pattern, and on the front and back surfaces of the multilayer core substrate, conductor circuits 34S, 34p, 34E, and 25m diameter signal through holes 36S (and (Not shown), power supply through hole 36p, and ground line through hole 36E (FIG. 20 (B)). (6) The substrates of the conductor circuits 34S, 34p, 34E and the through-holes 36S, 36P, 36E are formed on the front and back surfaces of the multilayer core substrate, and the substrates include NaOH (10 g / 1) and NaC102 (40). g / 1) and aqueous solution of Na3P04 (6g / l) as a blackening treatment of a blackening bath (oxidation bath) and reduction of an aqueous solution containing NaOH (10g / l) and NaBH4 (6g / l) as a reduction bath After processing, 34 points of roughened surface are formed on the surface of the upper layer conductor circuit and the through hole (Fig. 20 (c)). (ΌNext, using a wiper, the resin composition 40 for via hole filling, which is the same as that of the first embodiment 1 described above, is filled between the conductor circuits 34S, 34p, and 34E, and the via holes = 36P, 36E. After that, it is dried under the condition of 20 minutes (Fig. 1A)) By polishing and flattening the surface of the substrate 30, the conductive end surface of the conductor μ and the through-hole end surface are exposed ... The hours and exposure time are used to form the resin filling material layer of the hardened through-hole filling resin composition 40, and the through-holes 36S (not shown), 36ρ, and 36E are formed (FIG. 21 (B)). ,, 4: 2 = Table: The thickness of the steel is 7.5 ~ 70. As such, the thickness of multi-sided copper is suitable to be thinner than the thickness of copper in the inner layer. In case 2 of the first case, she became 25 v m. This can be used to make the front and back layers more formed than the inner layer, so that the diameter of the end surface of the through hole and the conductor circuit or the through hole connection are two: Road 2160-6825-PF; Ahddub 43 200529722 ==: narrow :::? The through-hole end face or the conductor circuit system will not become a rugged engraving after riding money and miscellaneous duties on the aforementioned substrate, and then 'using «n to blow the etching liquid on the substrate On both sides, the surface of 4 34S, the power circuit 34P, the ground circuit 34E, and the connection end face of the through-hole 36 is engraved to form a roughened surface 36 on the entire surface of the conductor circuit (Figure 2i (c )). As the etching solution, an etching solution (Mekkul &gt; / made by Mekkuetchbond) composed of 10 parts by weight of a copper (II) complex compound, 73 parts by weight of glycolic acid, and 5 parts by weight of potassium vaporization was used. The subsequent processes are the same as the aforementioned steps with reference to FIG. 5 to FIG. 7! In the embodiment, the description is omitted. However, the thickness of the conductor circuits 58 and 158 is 15 // m by adjusting the time of electricity. [Second Embodiment 1] [Second Embodiment 1] The existence of a conductor circuit that does not extend from a through hole exists. The area of the through hole is directly below 1C. However, in the second embodiment 1 and 2, it is changed as follows. Except this, it is the same as the second embodiment! . Fig. 26 (A) is a cross-sectional view showing a representative ground layer of the inner layer of the 4-layer core, and Fig. 26 (A magic line shows a cross-section of the representative power layer of the inner layer of the 4-layer core.

第2實施例一2之多層芯係也成為4層芯，在電源用通孔36p貫 通地線層16E之際，不具有由該通孔開始延出之導體電路16D之電源 用通孔係相對於連接在1C電源電路之全通孔而成為50%，並且，在地 線用通孔36E貫通電源層16P之際，不具有由該通孔開始延出之導體 電路之地線用通孔係相對於連接在1C地線電路之全通孔而成為。 不具有假接端面之通孔數目之調整係可以參考圖18(B)而在前述（2) 之製程，在銅箔16形成電路時，來改變曝光薄膜之圖案。 [第2實施例一 3 ] 第2實施例一3係除了在第2實施例一2,使得不具有由通孔開始 延出之導體電路之通孔成為70%以外，其餘相同於第2實施例一2。 [第2實施例一4] 第2實施例一4係除了在第2實施例一2,使得不具有由通孔開始 2160-6825-PF；Ahddub 44 200529722 延出之導體電路之通孔成為80%以外，其餘相同於第2實施例一2。 — [第2實施例一 5] 第2實施例一 5係除了在第2實施例一 2，使得不具有由通孔開始 延出之導體電路之通孔成為90%以外，其餘相同於第2實施例一2。 [第2實施例一6] 第2實施例一6係除了在第2實施例一1，使得内層之電源層和地 線層之導體層之厚度改變成為45/zm以外，其餘相同於第2實施例一 1。 [第2實施例一 7] 第2實施例一7係除了在第2實施例一1，使得内層之電源層和地 線層之導體層之厚度改變成為60//m以外，其餘相同於第2實施例一 1。 讀•[第2實施例一8 ] 第2實施例一8係除了在第2實施例一1，使得内層之電源層和地 線層之導體層之厚度改變成為75/zm以外，其餘相同於第2實施例一 1。 [第2實施例一 9 ] 第2實施例一9係除了在第2實施例一3，使得内層之電源層和地 線層之導體層之厚度改變成為75//m以外，其餘相同於第2實施例一3。 [第2實施例一 10] 參考圖27而就本發明之第2實施例一 10之多層印刷電路板，來 進行說明。 參考圖22，在前述第2實施例一 1之多層印刷電路板，使用在内 ®層配置2層之地線電路16E、16P之多層芯基板30。相對於此，在第2 實施例一10，使用設置4層之内層地線電路16E、116E、16P、116pp 之多層芯基板20。交互地配置地線電路和電源電路。 [第2實施例一 11〜19] 在第2實施例一 1〜9，改變起始材料之厚度和芯基板表背面之導 體層之厚度。具體地說，使得圖18(A)之銅猪基板10之厚度成為 0· 2mm，圖20(b)之芯基板表背面之導體層（34S、34P、34E)之厚度成 為10//m。這個以後之製程係按照第2實施例一1。 [第2實施例一 20] 第2實施例一20係在第2實施例一 16，使得不具有1C正下方之 2160-6825~PF；Ahddub 45 200529722 - 假接端面之電源用通孔數目相對於全電源用通孔數目而成為30%，同 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為30%。 [第2實施例一 21] 第2實施例一21係在第2實施例一20，使得多層芯基板之内層之 電源層和地線層之導體層之厚度成為60 // m。 [第2實施例一 22] 第2實施例一 22係在第2實施例一20，使得多層芯基板之内層之 電源層和地線層之導體層之厚度成為75 // m。 [第2實施例一23] φ 第2實施例一23係在第2實施例一20，使得多層芯基板之内層之 電源層和地線層之導體層之厚度成為150//m。使得圖18(D)之膠片之 厚度成為275 # m。 [第2實施例一2 4 ] 第2實施例一24係在第2實施例一 20,使得多層芯基板之内層之 電源層和地線層之導體層之厚度成為300 //m。使得圖18(D)之膠片之 厚度成為450 // m。 [第2實施例一25] 第2實施例一 25係在第2實施例一20，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為50%，同 •時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為50%。 [第2實施例一26] 第2實施例一 26係在第2實施例一21，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為50%，同 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為50%。 [第2實施例一27] 第2實施例一 27係在第2實施例一22，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為50%，同 2160-6825-PF;Ahddub 46 200529722 4 . 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為50%。 [第2實施例一28] 第2實施例一 28係在第2實施例一23，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為50%，同 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為50%。 [第2實施例一29] 第2實施例一29係在第2實施例一24，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為50%，同 B 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為50%。 [第2實施例一30] 第2實施例一30係在第2實施例一20，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為70%，同 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為70%。 [第2實施例一 31] 第2實施例一 31係在第2實施例一21，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為70%，同 •時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為70%。 [第2實施例一32] 第2實施例一32係在第2實施例一22，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為70%，同 時，使得不具有1C正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為70%。 [第2實施例一33] 第2實施例一33係在第2實施例一23，使得不具有1C正下方之 假接端面之電源用通孔數目相對於全電源用通孔數目而成為70%，同 2160-6825-PF;Ahddub 47 200529722 2 δ使不日Ί Κ正下方之假接端面之地線用通孔數目相對於全地線 用通孔數目而成為70%。 [第2實施例〜34] wΐ 1實列34係在第2實施例-24，使得不具有IC正下方之 且^通孔數目相對於全電源用通孔數目而成為㈣，同 時，使付不具有1C正下方之伽祕 丄u 用通孔數目而成為70%。饭接端面之地線用通孔數目相對於全地線 [第2實施例一35] 第2實施例一 35係在笛c&gt;总 u 電源層和地線層之導體層之第厚2产實=，卜12,使得多層芯基板之内層之 •[第2實施例-36] 又-、6〇/zm。 電为在第2實施例-25，使得多層怒基板之内層之 電源層和地線層之導體層之 第2實施例一2〜5:^成為3°，。 端面之通孔數目係由圖3〇和、丄9、35之不具有1C正下方之假接 字。 和圖33中之所顯示之％來減去10〜15%之數 (第2比較例〜1) 内層= = : =度相同於第2實施例…同樣厚度之 相關技術，將假接端面l6 sp層二旦是，參考圖36、圖38，相同於前述 鲁（第2比較例-2) b配置在全部之通孔。 以外，其餘係相同於第2 知多層芯基板之導體厚度成為15 (第2比較例一 3) ^ ?， 1。 在第2比較例一1，改變 之銅羯基板10之厚度成為材枓之厚度。具體地說，使得圖18(A) 之厚度成為5/zm。 ·則1。此外，在圖18(A)，使得鋼箔16 在第2實施例一 1〜9和第2 之1C晶片，供應相同量之電源，j例〜卜2之基板，構裝頻率3· 1GHz 無法直接地測定1C晶片之雷厭’須m定在啟動時之電壓之下降量。此外， ，因此，在印刷電路板上，形成可測定 2160-6825-PF;Ahddub 48 200529722 ;IC電壓之電路。顯示此時之電麼下降量之值。成為在電源電壓l ov 時之變動之電壓下降量之值。 · 此外，確認第2實施例一 1〜9和第2比較例―丨、2之初期動作。 將該結果顯示在圖3 3中之圖表。 此外，即使是就不具有假接端面之通孔數目，也進行驗證。在以 下，顯示這些結果。將在橫軸成為不具有假接端面之通孔數目並且在 縱轴成為電歷下降置之值之（V)、结果’顯不在圖32(a)、（b)。 由第2實施例-1和第2比杈例-1之比較而得知··藉由使得Ic 正下方之通孔成為不具有由通孔開始延出之導體電路之通孔，而改善 第1次和第2次之電壓下降，不產生1C之錯誤動作。 σ 由第2實施例-2〜5和第2比較例—i之結果而得知：在電源用 =地線用通孔成為*具有假接端面之通孔而使得其數目變多時，改盖 第1次和第2次之電壓下降（參考圖32(A)、（B)、圖33) ° 户之==1、6、7、8之比較而得知:藉由使得多層芯之内 ΓοΓ接著在\；&quot;還更加改4第1次和第2次之電壓下降（參考圖 4〇)接者’在内層之導體厚度成為増層之 時，其改善效果係變差。 *體厚度之3倍以上 由第2實施例一2〜5和第2比較例 由通孔開始延出之導體電路之通孔數目 =.藉由增加不具有 壓下降。接著，在成為70%以上時 改。第1次和第2次之電 不具有由通孔開始延出之導體電路生1誤動作。接著，在 善效果係變差。 通孔數目成為70%以上時，其改 由第2實施例一 i和第2比較 厚而改善第3次之電壓下降。 2而侍知：藉由使得導體厚度變 也由刚述試驗結果而得知··藉 初期啟動時之所發生之電源不足明之構造而使得1C晶片之 是構裝高頻區域之Ic晶片、特別是⑽下^)之程度變小，·得知：即使 地進:::動。因此，也能夠提升電‘=，也毫無問題 此外，比起習知之印刷基叔 &amp;運接r生 電阻變小。因此，即使是附加屬還在印刷基板之電路内之 娶進灯在向溫高濕度下之所進行之 2160-6825-PF；Ahddub 49 200529722 可靠性試驗（高溫高濕度偏壓試驗），也使得破壞之時間變長，所以， 也可以提高可靠性。 接著，就按照第2實施例一11〜36、第2比較例一3所製造之多 層印刷電路板而言，藉由以下說明之方法而測定1C晶片之電壓下降 量。 在構裝下列No. 3之1C晶片之各種多層印刷電路板，進行同時開 關，測定此時之1C晶片之電壓下降量。此外，無法直接地測定1C晶 片之電壓，因此，在印刷電路板上，形成可測定1C電壓之電路。成為 在電源電壓1.0V時之變動之電壓下降量之值。 此外，就按照第2實施例一 11〜36、第2比較例一 3所製造之多 φ 層印刷電路板而言，藉由以下說明之方法而確認在搭載之1C晶片是否 有錯誤動作。 作為1C晶片係將由以下之No. 1〜3所選出之任何一種1C晶片構 裝於各個多層印刷電路板，同時，進行100次之開關，評價有無錯誤 動作。 將這些結果，顯示在圖30。The multilayer core system of the second embodiment 1 also becomes a four-layer core. When the power supply through hole 36p penetrates the ground layer 16E, the power supply through hole system without the conductor circuit 16D extending from the through hole is opposed. When 50% of all through-holes connected to the 1C power circuit are connected, and when the ground-through hole 36E penetrates the power supply layer 16P, there is no ground-through hole system for the conductor circuit extending from the through-hole. It is relative to all through holes connected to the 1C ground circuit. The adjustment of the number of through-holes without a dummy end surface can be changed by referring to FIG. 18 (B) and in the aforementioned (2) process when the copper foil 16 forms a circuit to change the pattern of the exposure film. [Second Embodiment 1] The second embodiment 1 is the same as the second embodiment except that the through hole of the conductor circuit that does not extend from the through hole becomes 70% in the second embodiment 1. Example one 2. [Second Embodiment 1] The second embodiment 1 except the second embodiment 1 and 2 does not have a through hole starting from 2160-6825-PF; Ahddub 44 200529722 extends the through hole of the conductor circuit to 80 Except for%, the rest are the same as those in the second embodiment. — [Second Embodiment 1] The second embodiment 1-5 is the same as the second embodiment except that the through hole of the conductor circuit that does not extend from the through hole becomes 90% in the second embodiment 1.实施 例 一 2。 Example one 2. [Second Embodiment 1] The second embodiment 6 is the same as the second embodiment except that the thickness of the inner layer power layer and the conductor layer of the ground layer is changed to 45 / zm in the second embodiment 1.实施 例 一 1。 Example one 1. [Second Embodiment 1] The second embodiment 7 is the same as the second embodiment except that the thickness of the inner layer power layer and the conductor layer of the ground layer is changed to 60 // m in the second embodiment 1. 2 实施 例 1。 2 embodiment one. Read • [Second Embodiment 8] The second embodiment 8 is the same as the second embodiment 1 except that the thickness of the inner power supply layer and the conductor layer of the ground layer is changed to 75 / zm, and the rest is the same as Second Embodiment 1 [Second Embodiment 1] The second embodiment 1-9 is the same as the second embodiment except that the thickness of the inner layer power layer and the conductor layer of the ground layer is changed to 75 // m in the second embodiment 1. 2 实施 例 3。 2 Embodiment 1. [Second Embodiment 1] A multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG. Referring to FIG. 22, in the multilayer printed circuit board of the first embodiment 1 described above, a multilayer core substrate 30 in which two layers of ground circuit 16E, 16P are arranged on the inner layer is used. On the other hand, in the first embodiment 10, a multilayer core substrate 20 having four layers of inner layer ground circuits 16E, 116E, 16P, and 116pp is used. Configure ground and power circuits alternately. [Second embodiment 1-11 to 19] In the second embodiment 1 to 9, the thickness of the starting material and the thickness of the conductor layer on the front and back surfaces of the core substrate were changed. Specifically, the thickness of the copper pig substrate 10 in FIG. 18 (A) is 0.2 mm, and the thickness of the conductor layers (34S, 34P, 34E) on the front and back surfaces of the core substrate in FIG. 20 (b) is 10 // m. The subsequent processes are in accordance with the second embodiment-1. [Second Embodiment 1-20] The second embodiment 20 is the second embodiment 16 so that there is no 2160-6825 ~ PF directly below 1C; Ahddub 45 200529722-the number of through-holes for the power supply on the end face is relative The number of through-holes for all power supplies is 30%, and the number of through-holes for ground wires without a fake end face directly below 1C is 30% relative to the number of through-holes for all ground wires. [Second Embodiment 1 21] The second embodiment 21 is the second embodiment 20, so that the thickness of the power supply layer and the conductor layer of the ground layer of the inner layer of the multilayer core substrate is 60 // m. [Second Embodiment 1 22] The second embodiment 22 is the second embodiment 20, so that the thickness of the power supply layer and the conductor layer of the ground layer in the inner layer of the multilayer core substrate is 75 // m. [Second Embodiment No. 23] φ The second embodiment No. 23 is based on the second embodiment No. 20, so that the thickness of the power supply layer and the conductor layer of the ground layer of the inner layer of the multilayer core substrate is 150 // m. The thickness of the film in Fig. 18 (D) is 275 # m. [Second Embodiment 1 2] The second embodiment 24 is the second embodiment 20, so that the thickness of the power supply layer and the conductor layer of the ground layer of the inner layer of the multilayer core substrate is 300 // m. The thickness of the film in Fig. 18 (D) is 450 // m. [Second Embodiment No. 25] The second embodiment No. 25 is the second embodiment No. 20, so that the number of through-holes for power supply without a false end face directly below 1C is 50 relative to the number of through-holes for full power supply. %, At the same time, the number of through-holes for ground wires without a false end face directly below 1C is 50% relative to the number of through-holes for all ground wires. [Second Embodiment 1-26] The second embodiment 26 is the second embodiment 21, so that the number of through-holes for power supply without the false end face directly below 1C is 50 relative to the number of through-holes for full power supply. At the same time, the number of through-holes for ground wires without a false end face directly below 1C is made 50% relative to the number of through-holes for all ground wires. [Second embodiment 27] The second embodiment 27 is the second embodiment 22, so that the number of through-holes for power supply without the false end face directly below 1C is 50 relative to the number of through-holes for full power supply. %, The same as 2160-6825-PF; Ahddub 46 200529722 4. When the number of through-holes for ground wires without false end faces directly below 1C is 50% compared to the number of through-holes for all ground wires. [Second Embodiment 28] The second embodiment 28 is in the second embodiment 23, so that the number of through-holes for power supply without a false end face directly below 1C is 50 relative to the number of through-holes for full power supply. At the same time, the number of through-holes for ground wires without a false end face directly below 1C is made 50% relative to the number of through-holes for all ground wires. [Second Embodiment No. 29] The second embodiment No. 29 is the second embodiment No. 24, so that the number of through-holes for power supply without a false end face directly below 1C is 50 relative to the number of through-holes for full power supply. %, The same as B, so that the number of through-holes for ground wires without a false end face directly below 1C is 50% relative to the number of through-holes for all ground wires. [Second Embodiment 30] The second embodiment 30 is the second embodiment 20, so that the number of through-holes for power supply without the dummy end face directly below 1C is 70 relative to the number of through-holes for full power supply. At the same time, the number of through-holes for ground wires without a false end face directly below 1C is made 70% relative to the number of through-holes for all ground wires. [Second Embodiment No. 31] The second embodiment No. 31 is the second embodiment No. 21, so that the number of through-holes for power supply without the dummy end face directly below 1C is 70 relative to the number of through-holes for full power supply. %, At the same time, the number of through-holes for ground wires without a false end face directly below 1C is 70% relative to the number of through-holes for all ground wires. [Second Embodiment 32] The second embodiment 32 is the second embodiment 22, so that the number of through-holes for power supplies without a dummy end face directly below 1C is 70 relative to the number of through-holes for full power supply. At the same time, the number of through-holes for ground wires without a false end face directly below 1C is made 70% relative to the number of through-holes for all ground wires. [Second Embodiment No. 33] The second embodiment No. 33 is the second embodiment No. 23, so that the number of through-holes for power supply without the dummy end face directly below 1C is 70 relative to the number of through-holes for full power supply. %, The same as 2160-6825-PF; Ahddub 47 200529722 2 δ makes the number of through-holes for the ground wire at the end of the dummy joint directly below the sunken κ become 70% relative to the number of through-holes for the whole ground wire. [Second Embodiment to 34] wΐ1 is a solid line 34 in the second embodiment-24, so that the number of through holes is not equal to the number of through holes for the entire power supply without the IC directly below, and at the same time, It does not have the number of through holes for Gamma 丄 u directly below 1C and becomes 70%. The number of through holes for the ground wire at the end of the rice connection is relative to the all-earth wire [Second Embodiment 35] The second embodiment 35 is the second thickest product of the conductor layer of the power supply layer and the ground layer of the total u &gt; Real =, Bu 12, making the inner layer of the multi-layered core substrate [2nd Example -36] and-, 60 / zm. Electricity is in the second embodiment-25, so that the inner layer of the multilayer substrate has a power supply layer and a conductor layer of the ground layer in the second embodiment 2 ~ 5: ^ becomes 3 °. The number of through-holes on the end face is formed by the dummy hyphens not directly below 1C in Figs. Subtract from 10% to 15% as shown in Figure 33 (second comparative example ~ 1) Inner layer = =: = Degrees are the same as in the second embodiment ... The related technology of the same thickness will falsely connect the end face 16 Referring to FIG. 36 and FIG. 38, the sp layer is the same as the aforementioned Lu (Second Comparative Example-2) b, and is disposed in all through holes. Other than that, the thickness of the conductor is the same as that of the second known multilayer core substrate, which is 15 (second comparative example 3) ^ ?, 1. In the second comparative example 1, the thickness of the copper foil substrate 10 changed to the thickness of the material. Specifically, the thickness of FIG. 18 (A) is 5 / zm. · Then 1. In addition, in FIG. 18 (A), the steel foil 16 is supplied with the same amount of power on the 1st to 9th and 2nd 1C wafers of the second embodiment, and the substrates of j to 2 are installed at a frequency of 3.1 GHz. The direct measurement of the lightning stress of the 1C chip must be determined by the voltage drop at startup. In addition, therefore, a circuit capable of measuring 2160-6825-PF; Ahddub 48 200529722; IC voltage is formed on a printed circuit board. Shows the value of the electricity drop at this time. It is the value of the amount of voltage drop that fluctuates at the time of the power supply voltage l ov. In addition, confirm the initial operation of the second embodiment 1 to 9 and the second comparative example ― 丨, 2. The results are shown in the graph in Figure 33. In addition, verification is performed even if the number of through-holes does not have a dummy end surface. Below, these results are shown. (V) where the number of through-holes without a dummy end surface on the horizontal axis and the ephemeris reduction value on the vertical axis are shown. The results are not shown in Figs. 32 (a) and (b). It is known from the comparison between the second embodiment-1 and the second comparison example-1 that by improving the through-hole directly below Ic to be a through-hole that does not have a conductor circuit extending from the through-hole, the second embodiment is improved. The 1st and 2nd voltage drops will not cause 1C error operation. σ is known from the results of the second embodiment-2 to 5 and the second comparative example-i: when the power supply = ground wire through hole becomes * through hole with a dummy end surface and the number of the through hole increases, change Cover the first and second voltage drops (refer to Figure 32 (A), (B), and Figure 33) ° Comparison of household == 1, 6, 7, and 8 shows: By making the multilayer core The inner ΓοΓ is further changed when the voltage drop of the first and second times (refer to FIG. 4) is further increased. When the thickness of the inner conductor becomes a 増 layer, the improvement effect is worsened. * Three times or more the thickness of the body. The number of through-holes in the conductor circuit extending from the through-holes from the second embodiment 1 to 2 and the second comparative example =. There is no voltage drop by increasing. Then, change it to 70% or more. The 1st and 2nd power failures do not have a conductor circuit extending from the through hole, causing a malfunction. Then, the good effect becomes worse. When the number of through holes becomes 70% or more, it is changed to be thicker in the second embodiment 1 and the second one, and the voltage drop for the third time is improved. 2 And the attendant: By making the thickness of the conductor also known from the test results just described ... by the structure of the insufficient power supply that occurred at the initial start-up, the 1C chip is an Ic chip that configures the high frequency region, especially It is His Majesty ^), the degree becomes smaller, and it is learned that: even if it advances ::: to move. Therefore, it is also possible to raise the electric power ′ = without any problem. In addition, the resistance is smaller than the conventional printed base amplifier. Therefore, the reliability test (high temperature and high humidity bias test) of 2160-6825-PF; Ahddub 49 200529722, which is performed under the conditions of high temperature and high humidity, even if the lamp is still in the circuit of the printed circuit board, makes the The destruction time becomes longer, so reliability can also be improved. Next, for the multilayer printed circuit boards manufactured according to the second embodiment 11 to 36 and the second comparative example 3, the amount of voltage drop of the 1C wafer was measured by the method described below. Various multilayer printed circuit boards with the No. 3 1C wafers were constructed, and simultaneous switching was performed to measure the voltage drop of the 1C wafers at this time. In addition, since the voltage of the 1C wafer cannot be measured directly, a circuit capable of measuring the 1C voltage is formed on the printed circuit board. It is the value of the amount of voltage drop that fluctuates when the power supply voltage is 1.0V. In addition, for the φ-layer printed circuit boards manufactured in accordance with the first embodiment 11 to 36 and the second comparative example 3, it is confirmed whether the 1C chip mounted on the board has an erroneous operation by the method described below. As a 1C wafer, any one of the 1C wafers selected from the following Nos. 1 to 3 was mounted on each multilayer printed circuit board, and at the same time, it was switched 100 times to evaluate the presence or absence of erroneous operation. These results are shown in FIG. 30.

No. 1 :驅動頻率：3. 06GHz、脈衝鎖（FSB) : 533MHz No. 2 :驅動頻率：3. 2GHz、脈衝鎖（FSB) ·· 800MHz No. 3 :驅動頻率：3. 46GHz、脈衝鎖（FSB) ·· 1066MHz 由構裝No. 1之1C晶片之結果而得知：如果通孔之一部分成為不 #具有假接端面之通孔的話，則能夠抑制1C晶片之錯誤動作或電壓下 降。推測這個係由於根據在說明書内之所說明之第2發明之效果2〜4 之緣故。 由構裝No. 2之1C晶片之第2實施例一 12和第2實施例一 36之比 較而得知··形成不具有假接端面之通孔之區域係最好是1C正下方。 此外，由構裝No. 3之1C晶片之第2實施例一20〜24和第2實施 例一25〜29之比較而得知··在内層之導體厚度和不具有假接端面之通 孔數目，具有相互作用。可以在内層之導體厚度變薄之狀態下，必須 使得不具有假接端面之通孔變多，在内層之導體厚度變厚之狀態下， 必須使得不具有假接端面之通孔變少。推測這個係由於根據使用圖34 2160-6825-PF;Ahddub 50 200529722 - 所說明之效果之緣故 内層之接地層之導體厚度係相同於内厣 f ’芯基板背面之接地層之導體厚度係相同於表；之電源:；之導體厚 度。因此’接地層之導 係也成為 =之導體厚 所以，能夠減低雜訊，、4，不容易發生錯=原層之同樣厚度， 此外，在比較構裝No. 2之1C晶片之第2實施&amp; 194 ^ 例-料而得知:即使是多層㈣體層之厚2實施 面之通孔數目成為相同置不 j者疋不具有假接端 使得電壓下降量或錯誤動作】不同。推測通=區域而 孔，使得IC為止之連接配線長度變短，因此，方之通 置不具有假接端面 精由在1C正下方，設 〈通孔’而使付本案之特徵變得更加有效之緣故。 【圖式簡單說明] 圖 1(A)至圖 f 板之製造方法之製程圖。* 丁發明之第1實施例一1之多層印刷電路 圖2(A)至圖2(E)係顯示第i 方法之製程圖。 貫彳1之多層印刷電路板之製造 圖3(A)至圖3(〇係_ +楚Ί命^ 方法之製程圖。 ♦不第1實靶例一1之多層印刷電路板之製造 方法1製(程)4(Χ)係^第1實施例—1之多層印刷電路板之製造 方法圖5(D)係顯示第1實施例-1之多層印刷電路板之製造 方法圖6(D)係顯示第1實施例-1之多層印刷電路板之製造 圖=A)至圖7(1))係_示第1實施例-1之多層印刷電路板之製造 方法之製程圖。 系m例、1之多層印刷電路板之剖面圖。 糸”属不1實施例—1之多層印刷電路板載置1C晶片之狀 態之剖面圖。 2160-6825-PF;Ahddub 51 200529722 ； 圖10係顯示ic晶片之動作中之電壓變化之圖形。 圖11係顯示1C晶片之動作中之電壓變化之圖形。 圖12係顯示1C晶片之動作中之電壓變化之圖形。 圖13係顯示第1實施例和第1比較例間之試驗結果之圖表。 圖14係顯示第1實施例之最小線間距、線幅寬形成能力評價圖案 之評價結果之圖表。 圖15係顯示第1實施例和第1比較例間之試驗結果之圖表。 圖16係顯示第1實施例之試驗結果之圖表。 圖17係相對於αι/α2之電壓下降量之圖形。 圖18(A)至圖18(D)係顯示本發明之第2實施例一1之多層印刷電 •路板之製造方法之製程圖。 圖19(A)至圖19(B)係顯示第2實施例一1之多層印刷電路板之製 造方法之製程圖。 圖20(A)至圖20(C)係顯示第2實施例一 1之多層印刷電路板之製 造方法之製程圖。 圖21(A)至圖21(C)係顯示第2實施例一1之多層印刷電路板之製 造方法之製程圖。 圖22係第2實施例一1之多層印刷電路板之剖面圖。 圖23係顯示在第2實施例一 1之多層印刷電路板載置ic晶片之 狀態之剖面圖。 • 圖24係顯示在第2實施例一 1之變化例之多層印刷電路板載置ic 晶片之狀態之剖面圖。 圖25(A)係圖22中之内層之電源用平面層16ρ之俯視圖，圖25(Β) 係内層之地線用平面層16Ε之俯視圖。 夕圖26(Α)係圖22中之内層之電源用平面層16Ρ之俯視圖，圖26(B) 係内層之地線用平面層16Ε之俯視圖。 圖27係第2實施例一1〇之多層印刷電路板之剖面圖。 圖28係顯示1C晶片之動作中之電壓變化之圖形。 圖29係顯示1C晶片之動作中之電壓變化之圖形。 圖30係顯示第2實施例和第2比較例間之試驗結果之圖表。 2160-6825-PF;Ahddub 52 200529722 圖31(A)係圖22中之内層之其他例子之電源用平面層ι6Ρ之俯視 圖，圖31(B)係内層之地線用平面層16E之俯視圖。 圖32(A)至圖32(B)係就不具有假接端面之通孔數目而在橫軸顯 示不具有假接端面之通孔數目並且在縱軸顯示電壓下降量之值（¥)之 圖形。 圖33係顯示内層之導體厚度和第1次〜第3次之電壓下降之關係 之圖表。 圖34係顯示通孔和導體層間之關係之說明圖。 圖35係關於本案發明之相關技術之多層印刷電路板之剖面圖。 圖36(A)係圖35之多層印刷電路板之χ4一χ4橫刳面圖，圖36(B) 係X5 —X5剖面圖。 圖37(A)係内層之電源用平面層16P之俯視圖，圖37(B)係内層之 地線用平面層16E之俯視圖。 圖38係先前技術之多層印刷電路板之橫剖面圖。 圖39係貫通多層芯之訊號用通孔之示意圖。 圖40係顯示第1次和第2次之電壓下降量之圖形。 【主要元件符號說明】 X2〜界面； X4〜界面； 12〜金屬層（金屬板）； 14〜樹脂層； 16 α〜粗化面； 16D1〜假接端面； 16Ε〜導體層； 16Ρ1〜電源電路； 16S2〜訊號電路； 20〜銅箔； 23〜填充樹脂； 3 0〜基板； XI〜界面； X3〜界面； 10〜多層印刷電路板； 12a〜開口； 16〜導體電路； 16D〜假接端面； 16DD〜電路； 16P〜導體層； 16S1〜訊號電路； 18〜樹脂層； 22〜電鍍膜； 25〜蓋電鍍； 2160-6825-PF;Ahddub 53 200529722No. 1: Driving frequency: 3. 06GHz, pulse lock (FSB): 533MHz No. 2: Driving frequency: 3.2GHz, pulse lock (FSB) ·· 800MHz No. 3: Driving frequency: 3. 46GHz, pulse lock (FSB) ············································································································································································ It is presumed that this is because of the effects 2 to 4 of the second invention described in the description. It is known from the comparison between the second embodiment 12 and the second embodiment 36 of the 1C wafer of No. 2 that the area where the through hole without the dummy end surface is formed is preferably directly below 1C. In addition, it is known from the comparison between the second embodiment 20-20 of the 1C wafer of No. 3 and the second embodiment 25-29 that the thickness of the conductor in the inner layer and the through hole without the dummy end surface Number, with interaction. In the state where the thickness of the inner conductor is thin, it is necessary to increase the number of through-holes without a dummy end surface, and in the state where the thickness of the inner layer is thick, it is necessary to reduce the number of through-holes without a dummy end surface. Presumably this is because the conductor thickness of the ground layer of the inner layer is the same as the conductor thickness of the ground layer on the back of the inner core f 'core substrate according to the effect explained using Figure 34 2160-6825-PF; Ahddub 50 200529722- Table; the power :; the thickness of the conductor. Therefore, the conductive system of the 'ground layer' is also thick. Therefore, noise can be reduced, and 4. Errors are not easy to occur. = The same thickness as the original layer. In addition, the second implementation of No. 2 1C chip &amp; 194 ^ Example-It is known that even if the number of through-holes in the thickness of the implementation layer of the multilayer carcass layer is the same, it does not have a false terminal to make the voltage drop amount or wrong action] different. It is presumed that the via = the area and the hole makes the length of the connection wiring up to the IC shorter. Therefore, Fang Zhitong does not have a false connection end surface. It is directly below 1C, and the <through hole 'is set to make the features of this case more effective. The reason. [Brief description of the drawings] Figure 1 (A) to Figure f. * Multilayer printed circuit of the first embodiment of the first embodiment of the invention Fig. 2 (A) to Fig. 2 (E) are process diagrams showing the i-th method. Figure 3 (A) to Figure 3 (〇 系 _ + 楚 Ί 命 ^ 的 方法 的 制造 方法 的 方法 的 Manufacture process diagram of the multilayer printed circuit board 1) ♦ Manufacturing method of the multilayer printed circuit board 1 which is not the first real target example 1 Process (Process) 4 (X) is a method of manufacturing the multilayer printed circuit board according to the first embodiment-1. FIG. 5 (D) is a method of manufacturing the multilayer printed circuit board of the first embodiment-1. FIG. 6 (D) It shows the manufacturing diagram of the multilayer printed circuit board of the first embodiment-1 = A) to FIG. 7 (1)) _ shows the manufacturing process diagram of the manufacturing method of the multilayer printed circuit board of the first embodiment-1. This is a cross-sectional view of the multilayer printed circuit board of Example m. “糸” is a cross-sectional view of a state where a 1C chip is placed on a multilayer printed circuit board according to Example 1. 2160-6825-PF; Ahddub 51 200529722; Figure 10 is a graph showing the voltage change in the operation of the IC chip. Figure 11 is a graph showing the voltage change in the operation of the 1C wafer. Fig. 12 is a graph showing the voltage change in the operation of the 1C wafer. Fig. 13 is a graph showing the test results between the first embodiment and the first comparative example. 14 is a graph showing the evaluation results of the minimum line pitch and line width forming ability evaluation pattern of the first embodiment. FIG. 15 is a graph showing the test results between the first embodiment and the first comparative example. The graph of the test results of Example 1. Figure 17 is a graph of the voltage drop amount with respect to αι / α2. Figures 18 (A) to 18 (D) are multilayer printed circuits showing the second embodiment 1 of the present invention. • Process chart of the manufacturing method of the road board. Figures 19 (A) to 19 (B) are process charts showing the manufacturing method of the multilayer printed circuit board of the second embodiment-1. Figure 20 (A) to Figure 20 ( C) is a process drawing showing the method for manufacturing the multilayer printed circuit board of the second embodiment-1. 21 (A) to 21 (C) are process drawings showing a method for manufacturing a multilayer printed circuit board of the second embodiment-1. FIG. 22 is a sectional view of the multilayer printed circuit board of the second embodiment-1. 23 is a cross-sectional view showing a state where an IC chip is mounted on a multilayer printed circuit board of the second embodiment 1. 1. FIG. 24 is a diagram showing a state where an IC chip is mounted on a multilayer printed circuit board of a modified example of the second embodiment 1. A cross-sectional view of the state. Fig. 25 (A) is a top view of the inner power plane layer 16ρ in Fig. 22, and Fig. 25 (B) is a top view of the inner plane ground layer 16E. Fig. 26 (A) is a plan view The top view of the inner layer power supply plane layer 16P in Fig. 22, and Fig. 26 (B) is the top view of the inner layer ground plane plane layer 16E. Fig. 27 is a cross-sectional view of a multi-layer printed circuit board 10 of the second embodiment. 28 is a graph showing the voltage change in the operation of the 1C wafer. Fig. 29 is a graph showing the voltage change in the operation of the 1C wafer. Fig. 30 is a graph showing the test results between the second embodiment and the second comparative example. 2160 -6825-PF; Ahddub 52 200529722 Fig. 31 (A) is a plane for power supply according to other examples of the inner layer in Fig. 22 The top view of layer 6P, Figure 31 (B) is a top view of the plane layer 16E for the ground line of the inner layer. Figures 32 (A) to 32 (B) are the number of through holes without false end faces and are not shown on the horizontal axis. A graph showing the number of through holes with dummy end faces and the voltage drop value (¥) on the vertical axis. Figure 33 is a graph showing the relationship between the thickness of the inner layer conductor and the voltage drop from the first to third times. Figure 34 FIG. 35 is a cross-sectional view of a multilayer printed circuit board related to the related art of the present invention. Fig. 36 (A) is a χ4-x4 cross-sectional view of the multilayer printed circuit board of Fig. 35, and Fig. 36 (B) is a X5-X5 cross-sectional view. Fig. 37 (A) is a plan view of the inner plane power layer 16P, and Fig. 37 (B) is a plan view of the inner plane ground layer 16E. Fig. 38 is a cross-sectional view of a prior art multilayer printed circuit board. FIG. 39 is a schematic view of a through-hole for a signal passing through a multilayer core. Fig. 40 is a graph showing the amount of voltage drop at the first and second times. [Description of main component symbols] X2 ~ interface; X4 ~ interface; 12 ~ metal layer (metal plate); 14 ~ resin layer; 16α ~ roughened surface; 16D1 ~ fake end face; 16E ~ conductor layer; 16P1 ~ power circuit 16S2 ~ signal circuit; 20 ~ copper foil; 23 ~ filled resin; 30 ~ substrate; XI ~ interface; X3 ~ interface; 10 ~ multilayer printed circuit board; 12a ~ opening; 16 ~ conductor circuit; 16D ~ false end face 16DD ~ circuit; 16P ~ conductor layer; 16S1 ~ signal circuit; 18 ~ resin layer; 22 ~ plated film; 25 ~ cover plating; 2160-6825-PF; Ahddub 53 200529722

3 2〜銅猪； 34α〜最外導體層； 34Ε〜導體層； 3 4 S〜訊號電路， 3 6〜通孔； 3 6冷〜粗化面； 36Ρ〜電源用通孔； 36ΤΗΕ〜地線用通孔； 40〜樹脂填充層； 5 0 α〜粗化面； 52〜無電解銅電鍍膜； 56〜電解銅電鍍膜； 58 α〜粗化面； 6 0 α〜粗化面； 71〜開口； 74〜金電鍛層； 76U〜錫鉛凸塊； 92〜接端面； 96〜接端面； 34〜導體電路； 34冷〜粗化面； 34Ρ〜導體層； 35〜拉拔部； 36 α〜通孔用通孔； 36Ε〜地線用通孔； 36S〜訊號用通孔； 36ΤΗΡ〜電源用通孔； 50〜層間樹脂絕緣層 50a〜導通孔用開口； 54〜電鍍阻劑； 58〜導體電路； 60〜導通孔； 70〜銲錫阻劑層； 72〜鎳電鍍層； 76D〜錫鉛凸塊； 90〜1C晶片； 94〜標點板； 98〜晶片電容器；3 2 ~ copper pig; 34α ~ outer conductor layer; 34E ~ conductor layer; 3 4S ~ signal circuit, 36 ~ through hole; 36 cold ~ roughened surface; 36P ~ through hole for power supply; 36TΗΕ ~ ground wire With through holes; 40 ~ resin filling layer; 5 0α ~ roughened surface; 52 ~ electroless copper plated film; 56 ~ electrolytic copper plated film; 58α ~ roughened surface; 600 ~ roughened surface; 71 ~ Opening; 74 ~ Gold electro-forged layer; 76U ~ Sn-lead bump; 92 ~ Joint end face; 96 ~ Joint end face; 34 ~ Conductor circuit; 34 Cold ~ roughened surface; 34P ~ Conductor layer; 35 ~ Drawing part; 36 α ~ Through hole for via; 36E ~ Through hole for ground wire; 36S ~ Through hole for signal; 36THP ~ Through hole for power supply; 50 ~ Interlayer resin insulation layer 50a ~ Opening for via hole; 54 ~ Electroplating resist; 58 ~ Conductor circuit; 60 ~ Via; 70 ~ Solder resist layer; 72 ~ Nickel plating layer; 76D ~ Tin-lead bump; 90 ~ 1C wafer; 94 ~ Punctuation board; 98 ~ Wafer capacitor;

116E〜内層地線電路；116PP〜内層地線電路 150〜層間樹脂絕緣層；158〜導體電路； 160〜導通孔； 50 r〜層間樹脂絕緣層用樹脂薄膜。 2160-6825-PF;Ahddub 54116E ~ inner ground circuit; 116PP ~ inner ground circuit 150 ~ interlayer resin insulation layer; 158 ~ conductor circuit; 160 ~ through hole; 50r ~ resin film for interlayer resin insulation layer. 2160-6825-PF; Ahddub 54

Claims (1)

200529722 十、申請專利範圍： 1·種多層印刷電路板，在由表背面之導體層和至少丨層以上之 内層之導體層所構成之多層芯基板上形成層間絕緣層和導體層而透過 導通孔來進行電氣連接， 其特徵在於：200529722 10. Scope of patent application: 1. A multilayer printed circuit board, an interlayer insulation layer and a conductor layer are formed on a multilayer core substrate composed of a conductor layer on the front and back surfaces and an inner layer of at least one or more layers, and the through-holes are penetrated. For electrical connection, which is characterized by: 刖述夕層心基板之電源用導體層之厚度和或地線用導體層之厚度 彳中之至&gt;、種係更加厚於層間絕緣層上之導體層之厚度。 2.如申請專利範圍第！項之多層印刷電路板，其中，在前述多声 心土板之電源用導體層之厚度和成為^卜層間絕緣層上之導體層 度成為α 2時，α 1和α 2係α 2&lt; α 1 g 40 α 2。 如中凊專利H圍第！項之多層印刷電路板，其中，在前述多層 ’:：5之地線用導體層之厚度和成為6&quot;3、層間絕緣層上之導體層之^ 度成為α2時，α3和α2係α2&lt;α3$40α2。 ^如中請專利範圍第i項之多層印刷電路板，其中，在前述多層 =土:f之電源用導體層之厚度和成為α卜層間絕緣層上之導體層之厚 度成為α2 時，αΐ 和α2係 1·2α2&lt;α1^40α2。 :·如申請專利範圍第i項之多層印刷電路板，其中，在 ==用導f層之厚度和成為α3、層間絕緣層上之導艘層之厚 度成為 α2 時，α3 和 α2 係 1·2α2&lt;α3^40α2。The thickness of the conductor layer for power supply and the thickness of the conductor layer for ground wire of the core substrate is described in the following: &gt; The species is thicker than the thickness of the conductor layer on the interlayer insulation layer. 2. If the scope of patent application is the first! In the multilayer printed circuit board according to the item, when the thickness of the conductor layer for power supply and the conductor layer on the interlayer insulating layer of the multi-sound core soil board are α 2, α 1 and α 2 are α 2 &lt; α 1 g 40 α 2. Such as Zhongli patent H round! In the multilayer printed circuit board according to the item, in which the thickness of the above-mentioned multilayer ':: 5 ground conductor layer and the thickness of the conductor layer on the interlayer insulation layer become α2, α3 and α2 are α2 &lt; α3 $ 40α2. ^ The multilayer printed circuit board according to item i of the patent application, wherein when the thickness of the aforementioned multilayer = soil: f power conductor layer and the thickness of the conductor layer on the interlayer insulation layer becomes α2, αΐ and α2 is 1 · 2α2 &lt; α1 ^ 40α2. : · If the multilayer printed circuit board of item i in the scope of patent application, where == the thickness of the conductive layer f and the thickness of α3, and the thickness of the guide layer on the interlayer insulation layer become α2, α3 and α2 are 1 · 2α2 &lt; α3 ^ 40α2. #其L如1睛專職圍第1項之多層印刷電路板，其中，在前述多層 二Α之9 Γ用導體層之厚度和成為以、層間絕緣層上之導體層之厚 線用導體層之厚度和成為:3 ^ 7 為時 α3 和前述αΜα2&lt;α3$40α2。 ^其扣專利範^第1項之多層印刷電路板，其中，在前述多層 ΪΪ為Ϊ2電日ί用導】體層之厚度和成為“卜層間絕緣層上之導體層之厚 導體層之厚度和成為α3時，…和前述^係 &gt; 8如中請專利範圍第項中任―項之多層印刷電路板，立中， 刖述忍基板之表背面之導體層之凰 八 守瓶《之厚度係更加薄於内層之導體層之厚 2160-6825-PF；Ahddub 55 200529722 度。 且且9有：L多：在具備連接表面和背面之複數個通孔並 且具有表面和“之導體層及内層之導體層 上形成層㈣緣層和導體層而透過導通孔來進行^連^層〜基板 其特徵在於： 電路由ί:氣地連接於1C晶片之電源電路或地線 用、甬;L 之淬：s源用通孔和許多地線用通孔及許多訊號 用通孔所構成’前述電源用通孔係在貫通多 體層之際，使得許多電源用通孔内之至少丨「/減⑽之地線用導 Am播祕a 王夕比正下方之電源用通孔，在 地線用導體層，不具有由電源用通孔開始延出之導體電路。 且且^^7^!^^’在具備連接表面和背面之複數個通孔並 且具有表面和“之導體層及内層之導體層 上形成層間絕緣層和導體層而透過導通孔n增λ上之夕盾心基板 其特徵在於： 料軌來柄電氣連接， 前述複數個通㈣由呈電氣地連接於 ==號=之許多電源用通孔和許多地=== :Ϊ:Γ二用ΐ孔係在貫通多層芯基板内層之電源用導 體層之際，使得許多地線用通孔内之$ w ^ 雷调用逡辦JS，S 士丄说ra 正下方之地線用通孔’在 H H 通孔開始延出之導體電路。 且具有表面和背面之導體層及内層之導體層之复 上形層和導體層而透過導通孔來進行;氣 一起具有如申請專利範圍第9項所述之電 範圍第10項所述之地線用通孔。 〃 νη 日且L2.r種Λ層㈣電路板，在賤連接表叫背面之龍個通孔並 且具有表面和背面之導體層及内層之導體層之 上形成層間絕緣層和導體層而透過導通孔來進行^氣連接fs心基板 其特徵在於： ； 前述複數個通孔係由呈電氣地連接於IG晶片之電_路或地線 56 2160-6825-PF;Ahddub 200529722 - 電路或者是訊號電路之许多電源用通孔和許多地線用通孔及許多訊號 用通孔所構成，前述電源用通孔係在貫通多層芯基板内層之地線用導 體層之際，使得許多電源用通孔内之70%以上之電源用通孔，在地線 用導體層，不具有由電源用通孔開始延出之導體電路。 13· —種多層印刷電路板，在具備連接表面和背面之複數個通孔並 且具有表面和背面之導體層及内層之導體層之3層以上之多層芯基板 上形成層間絕緣層和導體層而透過導通孔來進行電氣連接， 其特徵在於： 前述複數個通孔係由呈電氣地連接於1C晶片之電源電路或地線 電路或者是訊號電路之許多電源用通孔和許多地線用通孔及許多訊號 Φ用通孔所構成，前述地線用通孔係在貫通多層芯基板内層之電源用導 體層之際，使得許多地線用通孔内之70%以上之地線用通孔，在電源 用導體層，不具有由地線用通孔開始延出之導體電路。 14. 一種多層印刷電路板，在具備連接表面和背面之複數個通孔並 且具有表面和背面之導體層及内層之導體層之4層以上之多層芯基板 上形成層間絕緣層和導體層而透過導通孔來進行電氣連接， 其特徵在於： 一起具有如申請專利範圍第12項所述之電源用通孔和如申請專 利範圍第13項所述之地線用通孔。 15. 如申請專利範圍第9至14項中任一項之多層印刷電路板，其 •中，前述多層芯基板之電源用導體層之厚度和α 1係相對於層間絕緣 層上之導體層之厚度α2而成為^^〈汉1^40012。 16. 如申請專利範圍第15項之多層印刷電路板，其中，前述α 1 係 1· 2α 2&lt;α 1$40α 2。 17·如申請專利範圍第9至16頊中任一項之多層印刷電路板，其 中，前述多層芯基板之表面及背面之導體層係電源層用導體層或地線 用導體層。 18·如申請專利範圍第9至16頊中任一項之多層印刷電路板，其 中，前述多層芯基板係在内層具備摩度變厚之導體層，在表面及背面 具備厚度變薄之導體層。 2160-6825-pp;Ahddub 57 200529722 ； 19·如申請專利範圍第9至16項中任一項之多層印刷電路板，其 中，前述多層芯基板之内層之導體層係2層以上。 20·如申請專利範圍第9至16項中任一項之多層印刷電路板，其 中，電容器係構裝於表面。 21· —種多層印刷電路板，在具備連接表面和背面之複數個通孔並 且具有表面和背面之導體層及内層之導體層之3層以上之多層芯基板 上开》成層間絕緣層和導體層而透過導通孔來進行電氣連接， 其特徵在於： ^ 前述複數個通孔係由呈電氣地連接於Ic晶片之電源電路或地線 電路或者是訊號電路之許多電源用通孔和許多地線用通孔及許多訊號 •用通孔所構成，前述電源用通孔係在貫通多層芯基板内層之地線用導 體層之際，使得許多電源用通孔内之Ic正下方之一部分之電源用通 孔，在地線用導體層，不具有由電源用通孔開始延出之導體電路。 22· —種多層印刷電路板，在具備連接表面和背面之複數個通孔並 且具有表面和背面之導體層及内層之導體層之3層以上之多層芯基板 上形成層間絕緣層和導體層而透過導通孔來進行電氣連接， 其特徵在於： 别述複數個通孔係由呈電氣地連接於IC晶片之電源電路或地線 電路或者是訊號電路之許多電源用通孔和許多地線用通孔及許多訊號 用通孔所構成，前述地線用通孔係在貫通多層芯基板内層之電源用導 •體層之際，使得許多地線用通孔内之IC正下方之一部分之地線用通 孔’在電源用導體層，不具有由地線用通孔開始延出之導體電路。 23· —種多層印刷電路板，在具備連接表面和背面之複數個通孔並 且具有表面和背面之導體層及内層之導體層之4層以上之多層芯基板 上形成層間絕緣層和導體層而透過導通孔來進行電氣連接， 其特徵在於： 一起具有如申請專利範圍第21項所述之電源用通孔和如申請專 利範圍第22項所述之地線用通孔。 24·如申請專利範圍第11項之多層印刷電路板，其中，1C正下方 之通孔係呈格子狀或千鳥狀地進行配置。 2160-6825-PF;Ahddub 58 200529722 - 25.如申請專利範圍第24項之多層印刷電路板，其中，1C正下方 之電源用通孔和地線用通孔係交互地進行配置。 26. 如申請專利範圍第14項之多層印刷電路板，其中，在地線用 導體層之不具有由電源用通孔開始延出之導體電路之電源用通孔和在 電源用導體層之不具有由地線用通孔開始延出之導體電路之地線用通 孔係在1C正下方之部分，呈格子狀或千鳥狀地進行配置。 27. 如申請專利範圍第26項之多層印刷電路板，其中，在地線用 導體層之不具有由電源用通孔開始延出之導體電路之電源用通孔和在 電源用導體層之不具有由地線用通孔開始延出之導體電路之地線用通 孔係交互地進行配置。 _ 28.如申請專利範圍第23項之多層印刷電路板，其中，在地線用 導體層之不具有由電源用通孔開始延出之導體電路之電源用通孔和在 電源用導體層之不具有由地線用通孔開始延出之導體電路之地線用通 孔係在1C正下方之部分，呈格子狀或千鳥狀地進行配置。 29.如申請專利範圍第28項之多層印刷電路板，其中，在地線用 導體層之不具有由電源用通孔開始延出之導體電路之電源用通孔和在 電源用導體層之不具有由地線用通孔開始延出之導體電路之地線用通 孔係交互地進行配置。# 其 L Such a multilayer printed circuit board as the first full-time perimeter item 1, wherein the thickness of the conductor layer for the above-mentioned multilayer two A to 9 and the thickness of the conductor layer for the thick wire to be the conductor layer on the interlayer insulation layer. The thickness sum becomes: 3 ^ 7 is α3 and the aforementioned αΜα2 &lt; α3 $ 40α2. ^ Its patent patent ^ The multilayer printed circuit board of item 1, wherein the thickness of the above-mentioned multilayer layer is the thickness of the bulk layer and the thickness of the thick conductor layer that becomes the "conductor layer on the interlayer insulation layer" When it becomes α3, ... and the aforementioned ^ series &gt; 8 as described in the patent scope of the first item of the multilayer printed circuit board, in the middle, describes the thickness of the conductive layer on the back surface of the substrate, the thickness of the phoenix eight guard bottle The thickness of the conductor layer is thinner than that of the inner layer 2160-6825-PF; Ahddub 55 200529722 degrees. And there are 9 more: L is more: there are a plurality of through holes connecting the surface and the back surface and the surface and the "conductor layer and the inner layer" A conductive layer is formed on the conductor layer and a conductive layer is formed through the vias. The substrate is characterized by: The circuit is connected to the power supply circuit or ground wire of the 1C chip by gas ground. Quenching: S-source vias, many ground vias, and many signal vias are formed. 'The aforementioned power-supply vias are connected to multiple body layers, so that at least 丨 / The ground line guide Am broadcast the secret a Wang Xibi directly below The source through hole does not have a conductor circuit extending from the power supply through hole in the ground conductor layer. And ^^ 7 ^! ^^ 'has a plurality of through holes with a connection surface and a back surface and has a surface The interlayer insulation layer and the conductor layer are formed on the conductor layer of the inner layer and the conductor layer of the inner layer, and the Shield Shield substrate on the λ is increased through the via n through the through hole n. Ground is connected to many through-holes for power supplies and many grounds ===: Ϊ: Γ two-use through-holes are connected to the power supply conductor layer that penetrates the inner layer of the multilayer core substrate, so that many ground wires are used in the through-holes. The $ w ^ Lei calls the JS, S said that the ground line directly below the ra is a conductor circuit that extends from the HH through hole. And it has the upper and lower conductive layers on the front and back, and the overlying layer and the conductive layer on the inner layer, which are conducted through the through holes; together, the gas has the land as described in the electric scope item 10 described in the patent application scope item 9 Through-hole for wire. 〃 νη and L2.r kinds of Λ-layer㈣ circuit boards, which form an interlayer insulation layer and a conductor layer on the base connection table called a dragon through hole on the back and have a conductor layer on the front and back and a conductor layer on the inner layer to pass through. The above-mentioned plurality of through-holes are electrically connected to the IG chip by an electric circuit or a ground wire 56 2160-6825-PF; Ahddub 200529722-circuit or signal circuit. Many power supply through holes, many ground line through holes, and many signal through holes are formed. The aforementioned power supply through holes are in the ground wire conductor layer penetrating the inner layer of the multi-layered core substrate. More than 70% of the power supply through-holes do not have a conductor circuit extending from the power supply through-holes in the ground conductor layer. 13. · A multilayer printed circuit board having an interlayer insulation layer and a conductor layer formed on a multilayer core substrate having a plurality of through holes connecting a front surface and a back surface, and having three or more conductor layers on the front and back surfaces and an inner conductor layer. Electrical connection is made through vias, which is characterized in that the aforementioned plurality of vias are a plurality of power supply vias and a plurality of ground vias which are electrically connected to a 1C chip power circuit or a ground circuit or a signal circuit And many signals Φ are formed with through holes. The aforementioned ground wire through holes are used to penetrate the inner conductor layer of the multilayer core substrate, so that more than 70% of the ground wire through holes are used in the ground wires. The power supply conductor layer does not have a conductor circuit extending from the ground via. 14. A multilayer printed circuit board having an interlayer insulation layer and a conductor layer formed on a multilayer core substrate having a plurality of through holes connecting a front surface and a back surface, and having at least four layers of a conductive layer on the front and back surfaces and a conductive layer on the inner layer, and transmitted therethrough. A via is used for electrical connection, and is characterized in that: a through-hole for power supply as described in item 12 of the scope of patent application and a through-hole for ground wire as described in item 13 of the scope of patent application are provided together. 15. For a multilayer printed circuit board according to any one of claims 9 to 14, in which the thickness and α 1 of the conductor layer for power supply of the aforementioned multilayer core substrate are relative to the conductor layer on the interlayer insulation layer The thickness α2 becomes ^^ <汉 1 ^ 40012. 16. The multilayer printed circuit board according to item 15 of the scope of patent application, wherein the aforementioned α 1 is 1 · 2α 2 &lt; α 1 $ 40α 2. 17. The multilayer printed circuit board according to any one of claims 9 to 16 (1), wherein the conductor layers on the front and back surfaces of the multilayer core substrate are conductor layers for power supply layers or conductor layers for ground wires. 18. The multilayer printed circuit board according to any one of claims 9 to 16 (1), wherein the multilayer core substrate is provided with a conductive layer having a thickened inner layer and a conductive layer having a thinner thickness on the front and back surfaces. . 2160-6825-pp; Ahddub 57 200529722; 19. The multilayer printed circuit board according to any one of claims 9 to 16, in which the inner layer of the multilayer core substrate has two or more conductor layers. 20. The multilayer printed circuit board according to any one of claims 9 to 16, wherein the capacitor is mounted on the surface. 21 · —A multilayer printed circuit board is formed on a multi-layered core substrate having a plurality of through holes connecting the front and back surfaces and having a conductive layer on the front and back surfaces and a conductive layer on the inner layer to form an interlayer insulating layer and a conductor It is electrically connected through the vias on the layer, and is characterized by: ^ The aforementioned plurality of vias are formed by a plurality of power supply vias and a plurality of ground wires which are electrically connected to the IC circuit or the ground circuit or the signal circuit. It consists of through-holes and many signals. Through-holes are used. The aforementioned power-supply through-holes pass through the ground wire conductor layer of the inner layer of the multilayer core substrate. Through-holes do not have conductor circuits extending from the through-holes for power supplies in the conductor layer for ground wires. 22 · —A multilayer printed circuit board having an interlayer insulation layer and a conductor layer formed on a multilayer core substrate having a plurality of through holes connecting the front and back surfaces and having three or more conductor layers on the front and back surfaces and an inner conductor layer. Electrical connection is performed through vias, and is characterized in that the plurality of vias are formed by a plurality of power supply vias and a plurality of ground vias which are electrically connected to a power circuit or a ground circuit of an IC chip or a signal circuit. Holes and many signal vias are formed. The aforementioned ground vias are used for power conductors and body layers that penetrate the inner layer of the multi-layer core substrate, so that many of the ground vias are directly below the IC in the vias. The through-holes' do not have a conductor circuit extending from the through-holes for ground wires on the power-conductor layer. 23 · —a multilayer printed circuit board having an interlayer insulation layer and a conductor layer formed on a multilayer core substrate having a plurality of through holes connecting the front and back surfaces, and having four or more conductor layers on the front and back surfaces and an inner conductor layer, and The electrical connection is performed through a via hole, and is characterized in that: a power supply through hole as described in the scope of patent application item 21 and a ground line through hole as described in the scope of patent application item 22 are provided together. 24. The multilayer printed circuit board according to item 11 of the scope of patent application, wherein the through holes directly below 1C are arranged in a grid or a thousand bird shape. 2160-6825-PF; Ahddub 58 200529722-25. For the multilayer printed circuit board under the scope of application for patent No. 24, the power supply vias and ground vias directly below 1C are configured alternately. 26. For example, the multilayer printed circuit board of the scope of application for patent No. 14, in which the conductor layer for the ground wire does not have a through hole for the power source of the conductor circuit extending from the through hole for the power source and the conductor layer for the power supply does not have The ground wire through hole having a conductor circuit extending from the ground wire through hole is a portion directly below 1C, and is arranged in a lattice or a thousand bird shape. 27. For example, the multilayer printed circuit board of the scope of application for patent No. 26, wherein the conductor layer for the ground wire does not have a power supply through hole for the conductor circuit extending from the power supply through hole and the conductor layer for the power supply does not have The through-holes for ground wires having conductor circuits extending from the through-holes for ground wires are arranged alternately. _ 28. The multilayer printed circuit board according to item 23 of the scope of patent application, wherein the conductor layer for the ground wire does not have a power supply through hole for the conductor circuit extending from the power supply through hole and a conductor layer for the power supply. The ground wire through-holes, which do not have a conductor circuit extending from the ground wire through-holes, are located directly below 1C, and are arranged in a grid or thousand-bird shape. 29. The multilayer printed circuit board according to item 28 of the scope of patent application, wherein the conductor layer for the ground wire does not have a through hole for the power source of the conductor circuit extending from the through hole for the power source and the conductor layer for the power supply does not have The through-holes for ground wires having conductor circuits extending from the through-holes for ground wires are arranged alternately. 2160-6825-PF;Ahddub 592160-6825-PF; Ahddub 59
TW094103371A 2004-02-04 2005-02-03 Multilayer printed wiring board TW200529722A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004028073 2004-02-04
JP2004029201 2004-02-05

Publications (2)

Publication Number Publication Date
TW200529722A true TW200529722A (en) 2005-09-01
TWI341704B TWI341704B (en) 2011-05-01

Family

ID=34840141

Family Applications (2)

Application Number Title Priority Date Filing Date
TW099135471A TW201106828A (en) 2004-02-04 2005-02-03 Multilayer printed wiring board
TW094103371A TW200529722A (en) 2004-02-04 2005-02-03 Multilayer printed wiring board

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW099135471A TW201106828A (en) 2004-02-04 2005-02-03 Multilayer printed wiring board

Country Status (7)

Country Link
US (2) US7800216B2 (en)
EP (1) EP1713313A4 (en)
JP (2) JP4722706B2 (en)
KR (5) KR20090036152A (en)
CN (3) CN101840898A (en)
TW (2) TW201106828A (en)
WO (1) WO2005076682A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI770287B (en) * 2017-10-13 2022-07-11 日商瑞薩電子股份有限公司 Semiconductor device

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1744606A3 (en) * 1999-09-02 2007-04-11 Ibiden Co., Ltd. Printed circuit board and method for producing the printed circuit board
KR100890475B1 (en) * 1999-09-02 2009-03-26 이비덴 가부시키가이샤 Printed circuit board and method of manufacturing printed circuit board
JP4488684B2 (en) 2002-08-09 2010-06-23 イビデン株式会社 Multilayer printed wiring board
KR101199285B1 (en) 2004-02-04 2012-11-12 이비덴 가부시키가이샤 Multilayer printed wiring board
JP4770514B2 (en) * 2006-02-27 2011-09-14 株式会社デンソー Electronic equipment
JP2008016630A (en) * 2006-07-06 2008-01-24 Matsushita Electric Ind Co Ltd Printed circuit board, and its manufacturing method
US7450396B2 (en) * 2006-09-28 2008-11-11 Intel Corporation Skew compensation by changing ground parasitic for traces
RU2009127537A (en) * 2006-12-28 2011-02-10 НТТ ДоСоМо, Инк. (JP) SENDING DEVICE, RECEIVING DEVICE, MOBILE STATION, BASIC RADIO STATION, MOBILE COMMUNICATION SYSTEM AND MOBILE COMMUNICATION METHOD
JPWO2008093757A1 (en) * 2007-01-31 2010-05-20 京セラ株式会社 Prepreg sheet manufacturing method and apparatus, and prepreg sheet
US8072732B2 (en) * 2007-04-10 2011-12-06 Ngk Spark Plug Co., Ltd. Capacitor and wiring board including the capacitor
US8440916B2 (en) * 2007-06-28 2013-05-14 Intel Corporation Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method
JP5085266B2 (en) * 2007-10-12 2012-11-28 富士通株式会社 Wiring board and manufacturing method thereof
US8130507B2 (en) * 2008-03-24 2012-03-06 Ngk Spark Plug Co., Ltd. Component built-in wiring board
US8186053B2 (en) * 2008-11-14 2012-05-29 Fujitsu Limited Circuit board and method of manufacturing the same
KR101018109B1 (en) * 2009-08-24 2011-02-25 삼성전기주식회사 Multilayer circuit board and manufacturing method thereof
KR101089959B1 (en) 2009-09-15 2011-12-05 삼성전기주식회사 Printed circuit board and fabricating method of the same
EP2542041B1 (en) 2010-02-26 2016-04-27 Mitsubishi Electric Corporation Method of manufacturing printed circuit board
TW201217809A (en) * 2010-10-27 2012-05-01 Hon Hai Prec Ind Co Ltd Memory load adapter board
KR101107589B1 (en) * 2011-09-16 2012-01-25 안치욱 Multi layer printed circuit board enhanced adhesive of the thick copper, and manufacturing method of it
TW201347051A (en) * 2012-01-27 2013-11-16 Mosaid Technologies Inc Method and apparatus for connecting memory dies to form a memory system
US8987602B2 (en) * 2012-06-14 2015-03-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Multilayer electronic support structure with cofabricated metal core
CN103517583B (en) * 2012-06-27 2016-09-28 富葵精密组件(深圳)有限公司 Multilayer circuit board and preparation method thereof
WO2014024754A1 (en) * 2012-08-07 2014-02-13 三菱瓦斯化学株式会社 Circuit board for semiconductor package and method for producing same
JP2014086651A (en) * 2012-10-26 2014-05-12 Ibiden Co Ltd Printed wiring board and manufacturing method for printed wiring board
US20140115886A1 (en) * 2012-10-26 2014-05-01 Volex Plc Method and system for marking substrate and placing components for high accuracy
JP2014093332A (en) * 2012-10-31 2014-05-19 Ibiden Co Ltd Printed-wiring board and method for manufacturing the same
KR101420520B1 (en) * 2012-11-07 2014-07-17 삼성전기주식회사 A printed circuit board and a method of manufacturing the same
US20140262440A1 (en) * 2013-03-14 2014-09-18 Xilinx, Inc. Multi-layer core organic package substrate
CN104806987B (en) 2014-01-28 2018-09-18 台达电子企业管理（上海）有限公司 Supply unit and its assemble method
JP2015213124A (en) * 2014-05-02 2015-11-26 イビデン株式会社 Package substrate
TWI663895B (en) * 2014-06-03 2019-06-21 日商三菱瓦斯化學股份有限公司 Resin laminate for printed circuit board for forming fine via hole, multilayer printed circuit board with fine via hole in resin insulating layer and manufacturing method thereof
KR101605172B1 (en) * 2015-04-07 2016-03-22 삼성전자주식회사 Package substrate and methods for fabricating the same
JP2018085384A (en) * 2016-11-21 2018-05-31 オムロン株式会社 Electronic device and manufacturing method thereof
KR102542594B1 (en) * 2016-12-16 2023-06-14 삼성전자 주식회사 Multilayer printed circuit board and electronic apparatus including the same
US10157832B2 (en) * 2017-03-08 2018-12-18 Globalfoundries Inc. Integrated circuit structure including via interconnect structure abutting lateral ends of metal lines and methods of forming same
CN110710118B (en) * 2017-06-02 2021-08-20 株式会社村田制作所 High-frequency module and communication device
AT520105B1 (en) * 2017-06-16 2019-10-15 Zkw Group Gmbh circuit board
JP2019062092A (en) * 2017-09-27 2019-04-18 イビデン株式会社 Printed wiring board
KR20190041215A (en) * 2017-10-12 2019-04-22 주식회사 아모그린텍 Method for manufacturing flexible circuit board and flexible circuit board manufactured by the method
CN111123065B (en) * 2018-10-30 2022-05-10 浙江宇视科技有限公司 Method and device for inspecting printed circuit board wiring
JP7055109B2 (en) * 2019-01-17 2022-04-15 三菱電機株式会社 Semiconductor device
CN110398680B (en) * 2019-08-14 2021-07-20 华芯电子(天津)有限责任公司 PCB reliability test method
US20210392758A1 (en) * 2019-10-31 2021-12-16 Avary Holding (Shenzhen) Co., Limited. Thin circuit board and method of manufacturing the same
JP6819803B2 (en) * 2020-01-16 2021-01-27 株式会社ニコン Substrate, imaging unit and imaging device
US11948918B2 (en) * 2020-06-15 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Redistribution structure for semiconductor device and method of forming same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260756A (en) 1993-03-04 1994-09-16 Ibiden Co Ltd Manufacture of printed wiring board
JPH06275959A (en) 1993-03-22 1994-09-30 Hitachi Ltd Multilayer wiring substrate, manufacture thereof, and manufacture of double side printed wiring board
US5509200A (en) * 1994-11-21 1996-04-23 International Business Machines Corporation Method of making laminar stackable circuit board structure
US6165892A (en) * 1998-07-31 2000-12-26 Kulicke & Soffa Holdings, Inc. Method of planarizing thin film layers deposited over a common circuit base
JP4117951B2 (en) * 1998-11-20 2008-07-16 イビデン株式会社 Multilayer printed wiring board manufacturing method and multilayer printed wiring board
MY144574A (en) * 1998-09-14 2011-10-14 Ibiden Co Ltd Printed circuit board and method for its production
JP2000101245A (en) * 1998-09-24 2000-04-07 Ngk Spark Plug Co Ltd Multilayer resin wiring board and its manufacture
JP2000244130A (en) 1998-12-25 2000-09-08 Ngk Spark Plug Co Ltd Wiring board, core board, and their manufacture
US6333857B1 (en) * 1998-12-25 2001-12-25 Ngk Spark Plug Co., Ltd. Printing wiring board, core substrate, and method for fabricating the core substrate
JP2000261147A (en) 1999-03-10 2000-09-22 Shinko Electric Ind Co Ltd Multilayer wiring board and manufacture thereof
JP2001044591A (en) 1999-08-03 2001-02-16 Ngk Spark Plug Co Ltd Wiring board
EP1744606A3 (en) 1999-09-02 2007-04-11 Ibiden Co., Ltd. Printed circuit board and method for producing the printed circuit board
KR100890475B1 (en) 1999-09-02 2009-03-26 이비덴 가부시키가이샤 Printed circuit board and method of manufacturing printed circuit board
JP2002064272A (en) * 2000-08-16 2002-02-28 Ibiden Co Ltd Multilayered printed wiring board and manufacturing method therefor
JP2002111222A (en) * 2000-10-02 2002-04-12 Matsushita Electric Ind Co Ltd Multilayer substrate
JP2002261455A (en) 2001-02-27 2002-09-13 Kyocera Corp Multilayer interconnection board and electronic device using it
JP4863564B2 (en) 2001-03-13 2012-01-25 イビデン株式会社 Printed wiring board and printed wiring board manufacturing method
JP4129717B2 (en) * 2001-05-30 2008-08-06 株式会社ルネサステクノロジ Semiconductor device
US6847527B2 (en) * 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
JP2003264253A (en) 2002-03-12 2003-09-19 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP4488684B2 (en) * 2002-08-09 2010-06-23 イビデン株式会社 Multilayer printed wiring board
US6995322B2 (en) * 2003-01-30 2006-02-07 Endicott Interconnect Technologies, Inc. High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same
JP2004253738A (en) * 2003-02-21 2004-09-09 Toshiba Corp Package substrate and flip chip type semiconductor device
US6885541B2 (en) * 2003-06-20 2005-04-26 Ngk Spark Plug Co., Ltd. Capacitor, and capacitor manufacturing process
KR101199285B1 (en) * 2004-02-04 2012-11-12 이비덴 가부시키가이샤 Multilayer printed wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI770287B (en) * 2017-10-13 2022-07-11 日商瑞薩電子股份有限公司 Semiconductor device

Also Published As

Publication number Publication date
US7800216B2 (en) 2010-09-21
JP5158179B2 (en) 2013-03-06
KR20080088670A (en) 2008-10-02
JP4722706B2 (en) 2011-07-13
EP1713313A4 (en) 2010-06-02
TWI352565B (en) 2011-11-11
KR20100080634A (en) 2010-07-09
CN101848597A (en) 2010-09-29
KR20080089528A (en) 2008-10-06
WO2005076682A1 (en) 2005-08-18
KR101137749B1 (en) 2012-04-25
KR20060118578A (en) 2006-11-23
CN1771771A (en) 2006-05-10
TWI341704B (en) 2011-05-01
KR20090036152A (en) 2009-04-13
TW201106828A (en) 2011-02-16
CN101840898A (en) 2010-09-22
CN1771771B (en) 2014-09-24
US20100321914A1 (en) 2010-12-23
US8569880B2 (en) 2013-10-29
JP2011044739A (en) 2011-03-03
EP1713313A1 (en) 2006-10-18
US20060244134A1 (en) 2006-11-02
KR101088338B1 (en) 2011-11-30
JPWO2005076682A1 (en) 2007-10-18

Similar Documents

Publication Publication Date Title
TW200529722A (en) Multilayer printed wiring board
KR101131759B1 (en) Multilayer printed wiring board
US8237060B2 (en) Method for manufacturing multilayer printed wiring board
KR101709959B1 (en) Bump structure, semiconductor package having the bump structure, and method of manufacturing the semiconductor package
KR101199285B1 (en) Multilayer printed wiring board
US7185429B2 (en) Manufacture method of a flexible multilayer wiring board
JP2004134724A (en) Multilayer printed wiring board
US20060273816A1 (en) Circuit board having a reverse build-up structure
US20040124535A1 (en) Substrate with stacked vias and fine circuits thereon, and method for fabricating the same
JP2010034578A (en) Multilayer printed wiring board
JP2005183466A (en) Multilayer printed wiring board
JP2023530107A (en) circuit board
JP2023525360A (en) circuit board