JP5588419B2 - パッケージ - Google Patents
パッケージ Download PDFInfo
- Publication number
- JP5588419B2 JP5588419B2 JP2011235385A JP2011235385A JP5588419B2 JP 5588419 B2 JP5588419 B2 JP 5588419B2 JP 2011235385 A JP2011235385 A JP 2011235385A JP 2011235385 A JP2011235385 A JP 2011235385A JP 5588419 B2 JP5588419 B2 JP 5588419B2
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- JP
- Japan
- Prior art keywords
- substrate
- metal layer
- frame
- copper
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/48155—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48157—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12458—All metal or with adjacent metals having composition, density, or hardness gradient
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
図1は、第1の実施形態に係るパッケージ10を示す模式図である。図1(a)は、パッケージ10の平面図であり、図1(b)は、図1(a)におけるIb−Ib線に沿った断面図である。パッケージ10は、例えば、半導体素子、光半導体素子、圧電素子などの電子部品をその内部に収容する。
図4は、実施形態の第1の変形例に係る接合構造を模式的に示す部分断面図である。図4(a)に示すように、本変形例では、接合金属層21と、枠体5と、の間に接合金属層25が設けられている点で、図3に示す接合構造と相違する。接合金属層25は、銅を含む金属である。また、接合金属層25と枠体5との間に、例えば、チタンまたはニッケルなどを含む接着層を設けても良い。
図5は、実施形態の第2の変形例に係る接合構造を模式的に示す部分断面図である。図5(a)に示すように、本変形例では、基板31の表面に接合金属層23が設けられず、接合金属層21と枠体5との間に接合金属層25が設けられている点で、図3に示す接合構造と相違する。基板31は、例えば、銅板、もしくは、銅を主成分とする合金からなる。
図6は、実施形態の第3の変形例に係る接合構造を模式的に示す部分断面図である。図6(a)に示すように、本変形例では、接合金属層21と、枠体5と、の間に接合金属層25が設けられる。さらに、基板3の銅を含む表面(接合金属層23の表面)、および、接合金属層21の表面に、保護金属層33および35が設けられた点で、図3に示す接合構造と相違する。
図8は、第2の実施形態に係る半導体装置100を示す模式図である。図8(a)は、半導体装置100の平面図であり、図8(b)は、図8(a)に示すVIIIb‐VIIIb線に沿った断面図である。
Claims (5)
- 電子部品が固着される基板と、
前記電子部品が固着される部分を囲む枠体であって、錫(Sn)、インジウム(In)および亜鉛(Zn)のうちの少なくとも1つの金属と、銅(Cu)と、を含む接合部を介して前記基板に接合された枠体と、
前記基板と、前記枠体と、の間に設けられたフィードスルー端子であって、前記基板および前記枠体に前記接合部を介して接合されたフィードスルー端子と、
を備え、
前記接合部は、750℃以上の融点を有し、
前記接合部において、前記金属の含有量は、前記基板および前記枠体の少なくともいずれか一方の側に向けて減少し、同じ方向に前記銅の含有量は、増加するパッケージ。 - 前記接合部は、前記基板側、および、前記枠体側の少なくともいずれか一方に設けられた銅を含む層を有する請求項1記載の部材のパッケージ。
- 前記接合部は、金(Au)および白金(Pt)の少なくともいずれかを含有する請求項1または2に記載のパッケージ。
- 前記基板は、銅または銅合金からなり、
前記枠体は、鉄(Fe)を含む合金からなる請求項1〜3のいずれか1つに記載のパッケージ。 - 前記基板および前記枠体の少なくともいずれかは、セラミック材を含む請求項1〜3のいずれか1つに記載のパッケージ。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011235385A JP5588419B2 (ja) | 2011-10-26 | 2011-10-26 | パッケージ |
US13/558,765 US20130105205A1 (en) | 2011-10-26 | 2012-07-26 | Joined structural body of members, joining method of members, and package for containing an electronic component |
EP12178910.1A EP2587532A3 (en) | 2011-10-26 | 2012-08-01 | Joined structural body of members, joining method of members, and package for containing an electronic component |
TW101127981A TWI471986B (zh) | 2011-10-26 | 2012-08-03 | 構件之接合構造體、構件之接合方法、以及封裝 |
KR1020120086056A KR101476504B1 (ko) | 2011-10-26 | 2012-08-07 | 부재의 접합 구조체, 부재의 접합 방법, 및 패키지 |
CN201210279989.5A CN103077934B (zh) | 2011-10-26 | 2012-08-08 | 部件的接合结构体、部件的接合方法以及封装体 |
US14/524,282 US9357644B2 (en) | 2011-10-26 | 2014-10-27 | Joined structural body of members, joining method of members, and package for containing an electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011235385A JP5588419B2 (ja) | 2011-10-26 | 2011-10-26 | パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013093472A JP2013093472A (ja) | 2013-05-16 |
JP5588419B2 true JP5588419B2 (ja) | 2014-09-10 |
Family
ID=47002542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011235385A Expired - Fee Related JP5588419B2 (ja) | 2011-10-26 | 2011-10-26 | パッケージ |
Country Status (6)
Country | Link |
---|---|
US (2) | US20130105205A1 (ja) |
EP (1) | EP2587532A3 (ja) |
JP (1) | JP5588419B2 (ja) |
KR (1) | KR101476504B1 (ja) |
CN (1) | CN103077934B (ja) |
TW (1) | TWI471986B (ja) |
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JP2014207388A (ja) | 2013-04-15 | 2014-10-30 | 株式会社東芝 | 半導体パッケージ |
JP2014207389A (ja) | 2013-04-15 | 2014-10-30 | 株式会社東芝 | 半導体パッケージ |
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JP5450313B2 (ja) * | 2010-08-06 | 2014-03-26 | 株式会社東芝 | 高周波半導体用パッケージおよびその作製方法 |
JP5269864B2 (ja) * | 2010-12-07 | 2013-08-21 | 株式会社東芝 | 半導体装置 |
JP2013038330A (ja) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
JP2014049700A (ja) * | 2012-09-03 | 2014-03-17 | Toshiba Corp | 部材の接合構造およびその接合方法、パッケージ |
JP2014207389A (ja) * | 2013-04-15 | 2014-10-30 | 株式会社東芝 | 半導体パッケージ |
JP2014207388A (ja) * | 2013-04-15 | 2014-10-30 | 株式会社東芝 | 半導体パッケージ |
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EP2587532A2 (en) | 2013-05-01 |
US9357644B2 (en) | 2016-05-31 |
KR101476504B1 (ko) | 2014-12-24 |
EP2587532A3 (en) | 2014-02-19 |
US20150043186A1 (en) | 2015-02-12 |
US20130105205A1 (en) | 2013-05-02 |
CN103077934A (zh) | 2013-05-01 |
CN103077934B (zh) | 2016-05-18 |
JP2013093472A (ja) | 2013-05-16 |
TW201330192A (zh) | 2013-07-16 |
TWI471986B (zh) | 2015-02-01 |
KR20130045797A (ko) | 2013-05-06 |
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