US20130105205A1 - Joined structural body of members, joining method of members, and package for containing an electronic component - Google Patents

Joined structural body of members, joining method of members, and package for containing an electronic component Download PDF

Info

Publication number
US20130105205A1
US20130105205A1 US13/558,765 US201213558765A US2013105205A1 US 20130105205 A1 US20130105205 A1 US 20130105205A1 US 201213558765 A US201213558765 A US 201213558765A US 2013105205 A1 US2013105205 A1 US 2013105205A1
Authority
US
United States
Prior art keywords
joining
copper
joining portion
metal
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/558,765
Inventor
Kazutaka Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAKAGI, KAZUTAKA
Publication of US20130105205A1 publication Critical patent/US20130105205A1/en
Priority to US14/524,282 priority Critical patent/US9357644B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13062Junction field-effect transistor [JFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12458All metal or with adjacent metals having composition, density, or hardness gradient

Definitions

  • Embodiments described herein relate generally to a joined structural body of members, a method of joining members, and a package for containing an electronic component.
  • An electronic component which is represented by a semiconductor element, is bonded to a substrate which supports the electronic component.
  • the electronic component bonded to the substrate is mounted on another substrate such as a mounting board.
  • Many of the electronic components are hermetically sealed within a package provided with a substrate in order to enhance the reliability of the electronic components.
  • Such a substrate or a package needs to be stable against a temperature during bonding or operation of the electronic component. Accordingly, a plurality of members which constitute such a substrate or a package is joined using a silver solder having a melting point higher than a bonding temperature of the electronic component normally, for example.
  • the substrate or the package is a complex which includes a circuit element for use of input/output of a signal or power supply from a power source, and a heat radiation element for radiating heat from an electronic component to outside.
  • Members constituting such a complex may have different linear expansion coefficients.
  • a warp or a strain is generated in the members due to the difference of the linear expansion coefficients of the members.
  • the warp or strain deteriorates a characteristic of an electronic component, and lowers the reliability of the electronic component.
  • FIG. 1A is a schematic plan view illustrating a package according to a first embodiment.
  • FIG. 1B is an enlarged cross-sectional view illustrating the package according to the first embodiment schematically.
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating a forming process of the package according to the first embodiment.
  • FIGS. 3A to 3C are schematic cross-sectional views illustrating a forming process of a joining portion of a joined structural body provided in the first embodiment.
  • FIGS. 4A to 4C are schematic cross-sectional views illustrating a first modification of the forming process of the joining portion of the joined structural body.
  • FIGS. 5A to 5C are schematic cross-sectional views illustrating a second modification of the forming process of the joining portion.
  • FIGS. 6A and 6B are schematic views illustrating a third modification of the forming process of the joining portion.
  • FIG. 7A is a schematic plan view illustrating a first modification of the package according to the first embodiment.
  • FIG. 7B is an enlarged cross-sectional view illustrating the first modification of the package according to the first embodiment schematically.
  • FIG. 8A is a schematic plan view illustrating a package according to a second embodiment.
  • FIG. 8B is an enlarged cross-sectional view illustrating the package according to the second embodiment schematically.
  • FIG. 9 is a two-element equilibrium diagram of copper and tin.
  • a joined structural body for mounting an electronic component on the body which is provided with a first member, a second member and a joining portion.
  • the joining portion is provided between the first member and the second member so as to connect the first member and the second member with each other mechanically.
  • the joining portion contains at least one metal of a tin, an indium or a zinc, and a copper.
  • the content of the metal in the joining portion decreases toward a side of at least one of the first member and the second member, and the content of the copper in the joining portion increases in the same direction as the decreasing direction of the content of the metal.
  • FIGS. 1A and 1B A first embodiment will be described with reference to FIGS. 1A and 1B .
  • FIGS. 1A and 1B are schematic views illustrating a package according to the first embodiment.
  • FIG. 1A is a plan view of the package
  • FIG. 1B is a cross-sectional view taken along Ib-Ib line in FIG. 1A .
  • the package contains an electronic element such as a semiconductor element, an optical semiconductor element or a piezo-electric element.
  • a package 10 is provided with a substrate 3 as a first member, a frame body 5 as a second member, two feed through terminals 7 .
  • the substrate 3 has a component mounting portion 12 and flange portions 14 .
  • the component mounting portion 12 is provided to mount an electronic component and a circuit element around the electronic component fixedly.
  • the flange portions 14 are provided to fix the substrate 3 to a mount board using screws.
  • a frame body 5 is arranged on the substrate 3 fixedly so as to surround the component mounting portion 12 .
  • the frame body 5 defines a boundary between the flange portions 14 and the component mounting portion 12 .
  • the feed through terminals 7 are arranged between the substrate 3 and the frame body 5 in an up-and-down direction.
  • the feed through terminals 7 are provided so as to connect an electronic component which is mounted on the component mounting portion 12 and is hermetically sealed in the package 10 with an external circuit electrically.
  • Two leads 9 which are connected with the external circuit are respectively connected to the feed through terminals 7 .
  • An electronic component and strip lines 7 b of the feed through terminals 7 can be respectively connected via wires (or conductive plates or ribbons).
  • the substrate 3 and the frame body 5 are connected via a joining portion 13 .
  • the substrate 3 , the frame body 5 , and the joining portion 13 constitute a joined structural body.
  • a package containing a power field effect transistor (power FET) for amplifying an electric power performs good heat dissipation.
  • the substrate 3 is made of a metal having a high heat conductivity, such as copper (Cu) or an alloy of copper and molybdenum (Mo).
  • the frame body 5 is required to have stiffness. Accordingly, the frame body 5 is made of a material such as a kovar i.e. an alloy which is produced by combining nickel (Ni) and cobalt (Co) with iron (Fe).
  • an electronic component is bonded to a surface 3 a (a component mounting portion 12 ) of the substrate 3 by using a solder of gold (Au) and tin (Sn), for example. Further, a lid is fixed to an upper surface of the frame body 5 so as to seal the inside hermetically, if required.
  • the package 10 is heated to about 280 to 300° C. Accordingly, the remelting temperature of the joining portion 13 is desired to be more than or equal to 300° C. As the temperature difference between a bonding temperature and the remelting temperature (melting point) of the joining portion 13 becomes larger, the manufacture is stable more.
  • the melting point of the silver solder is more than or equal to 780° C.
  • the frame body 5 is made of a kovar, and the substrate 3 and the frame body 5 are joined using a silver solder, warp or strain is large due to the difference between the linear thermal expansion coefficients of the substrate 3 and the frame body 5 during the cooling process of the silver solder, the substrate 3 and the frame body 5 . It is because the melting point of the sliver solder is high,
  • the joining portion 13 can be formed by a liquid phase diffusion of copper and tin.
  • the liquid phase diffusion of copper and tin is caused within a temperature range of 250 to 300° C., which allows forming the joining portion 13 at a temperature lower than that of the silver solder.
  • warp or strain of the substrate 3 and the frame body 5 can be suppressed.
  • the melting point of a chemical compound formed by a liquid phase diffusion of copper and tin is 750° C., for example, which is substantially the same as the melting point of a silver solder. Accordingly, the chemical compound is stable against a bonding temperature for an electronic component and an operating temperature of the electronic component.
  • FIGS. 2A and 2B are cross-sectional views schematically illustrating an example of forming process of the package 10 .
  • FIGS. 3A to 3C , FIGS. 4A to 4C , FIGS. 5A to 5C , and FIGS. 6A to 6C are schematic cross-sectional views respectively illustrating examples of forming process of the joining portion 13 .
  • the substrate 3 as the first member and the frame body 5 as the second member are prepared.
  • a joining metal layer 21 is provided on a joining surface 5 a of the frame body 5 .
  • the joining metal layer 21 is a metal layer of at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn).
  • a second joining metal layer 23 containing copper is provided on the surface 3 a of the substrate 3 .
  • the substrate 3 is made of a copper, or a copper alloy containing copper as a main component, the joining metal layer 23 may be omitted.
  • the surface portion of the substrate 3 containing copper or the second joining metal layer 23 is brought into contact with a surface of the joining metal layer 21 formed on the frame body 5 .
  • a load is applied between the substrate 3 and the frame body 5 while maintaining contact of the substrate 3 and the frame body 5 with each other. Under this state, the substrate 3 and the frame body 5 are heated and maintained within a temperature range of 250 to 300° C.
  • the metal of the low melting point contained in the joining metal layer 21 is melted by the heating so that the metal is diffused from the joining metal layer 21 in liquid phase state to a surface portion of the second joining metal layer 23 containing copper. In the example illustrated in FIG. 2B , the metal of the low melting point is diffused into the joining metal layer 23 .
  • the joining metal layer 21 may be formed using a vacuum deposition, a sputtering, or plating.
  • the joining metal layer 23 may be formed by sputtering copper on a surface of the substrate 3 and patterning a deposited copper layer to a predetermined shape.
  • adhesion layers containing titanium or nickel may be provided, respectively, between the joining metal layer 21 and the frame body 5 , and between the joining metal layer 23 and the substrate 3 , in order to strengthen adhesion.
  • FIGS. 3A to 3C are enlarged partial and cross-sectional views illustrating a process of forming the joining portion which constitutes the joined structural body between the substrate 3 and the frame body 5 .
  • a surface of the joining metal layer 21 is brought into contact with a surface of the joining metal layer 23 , and a load is applied so as to maintain the contact of the joining metal layers 21 , 23 with each other.
  • the substrate 3 is heated, and the temperature of the joining metal layers 21 , 23 is maintained within a range of 250 to 300° C., for example.
  • the metal of the low melting point contained in the joining metal layer 21 is diffused into the joining metal layer 23 so that a diffusion region 23 a is formed.
  • the contact state is further maintained for a predetermined period under the temperature of 250 to 300° C. so that the joining portion 13 is formed by fusion of the joining metal layers 21 , 23 .
  • the substrate 3 and the frame body 5 are joined with each other via the joining portion 13 .
  • all of the metal of the low melting point is diffused into the joining metal layer 23 so that any solid phase metal does not remain.
  • the joining portion 13 contains at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn), and copper (Cu).
  • the content of the metal of the low melting point decreases toward a side of the substrate 3 , and the content of copper increases toward the side of the substrate 3 .
  • the joining metal layer 21 is made of a tin layer having a thickness of 4 ⁇ m
  • the joining metal layer 23 is made of a copper layer having a thickness of 4 ⁇ m.
  • the joining metal layers 21 , 23 are brought into contact with each other.
  • the joining metal layers 21 , 23 are heated and maintained at 250° C. for about 30 minutes, for example. Under such a temperature, the joining portion 13 can be formed by diffusing tin into the joining metal layer 23 (a copper layer).
  • FIG. 9 shows a two-element equilibrium diagram of copper and tin.
  • the vertical axis shows a temperature (° C.)
  • the horizontal axis shows a weight percentage (wt %) of tin.
  • tin becomes a liquid phase state so that tin is diffused into the copper layer of a solid phase.
  • copper is diffused into the tin layer.
  • copper and tin form a solid solution containing an a solid solution whose tin is less than or equal to about 15 wt %.
  • the solid solution is a composition containing copper of 90 wt % and tin of 10 wt % that is a composition indicated by a broken line extending vertically in FIG. 9
  • a large joining strength can be obtained without causing a phase change within a temperature range of about 330 to 820° C.
  • a solid solution which is formed under the temperature range does not contain an inter-metallic compound ( ⁇ layer) of Cu 6 Sn 5 or an inter-metallic compound ( ⁇ layer) of Cu 3 Sn, a juncture having a resistance against a shock can be formed.
  • the thicknesses of the joining metal layers 21 , 23 are set in consideration of a joining time and a joining strength. For example, when the thickness of the joining metal layer 21 is small, the unevenness of the joining surface cannot be sufficiently suppressed so that voids may be created, resulting in weakening the joining strength. In contrast, when the thickness is too large, the joining process needs a long time, resulting in lowering the manufacturing efficiency. Desirably, the thickness of the joining metal layer 21 is less than or equal to 10 ⁇ m, and more than or equal to 2 ⁇ m.
  • FIGS. 4A to 4C are enlarged partial and cross-sectional views illustrating a first modification of the forming process of the joining portion of the joined structural body according to the first embodiment.
  • the modification is different from the joined structure illustrated in FIGS. 3A and 4B in the point that a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5 .
  • the joining metal layer 25 is a metal containing copper.
  • an adhesion layer containing titanium or nickel may be provided between the joining metal layer 25 and the frame body 5 .
  • a surface of the joining metal layer 21 and a surface of a joining metal layer 23 are brought into contact with each other, and maintained within a range of 250 to 300° C., for example.
  • This step results in forming a region 23 a where a metal of a low melting point is diffused from a front surface of the joining metal layer 21 into a side of a substrate 3 , and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 into a side of a frame body 5 .
  • a joining portion 13 is formed by fusing the joining metal layer 21 and the joining metal layers 23 , 25 .
  • a region containing a high proportion of the metal of the low melting point is formed at an intermediate position between the substrate 3 and the frame body 5 .
  • the proportion of the metal of the low melting point decreases toward both sides of the substrate 3 and the frame body 5
  • the proportion of copper increases toward both sides of the substrate 3 and the frame body 5 .
  • the metal of the low melting point contained in the joining metal layer 21 is desired to be completely diffused so as to be integral with the joining metal layer 23 and the joining metal layer 25 .
  • the joined structure may be configured by a first layer containing copper provided on a side of the substrate 3 , and a second layer containing copper provided on a side of the frame body 5 .
  • FIGS. 5A to 5C are enlarged partial and cross-sectional views illustrating a second modification of the forming process of the joining portion of the joined structural body according to the first embodiment.
  • the modification is different from the forming process illustrated in FIGS. 3A to 3C in that any layer as the joining metal layer 23 is not provided on a surface of a substrate 31 , and in that a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5 as illustrated in FIG. 5A .
  • the substrate 31 is made of copper or an alloy containing copper as a main component.
  • a surface of the joining metal layer 21 and a surface of the substrate 31 are brought into contact with each other, and maintained within a range of 250 to 300° C., for example.
  • the step results in forming a region 31 a where a metal of a low melting point is diffused from a front surface of the joining metal layer 21 into the substrate 31 , and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 into a side of the frame body 5 .
  • a joining portion 13 is formed by fusing the joining metal layer 21 , the substrate 31 and the joining metal layer 25 .
  • the joining portion 13 becomes to have a region 31 a which is formed by diffusing the metal of the low melting point into the substrate 31 .
  • a region containing a high proportion of the metal of the low melting point is formed at an intermediate position between the substrate 31 and the frame body 5 .
  • the proportion of the metal of the low melting point decreases toward both sides of the substrate 31 and the frame body 5 , and the proportion of copper increases toward both sides of the substrate 31 and the frame body 5 .
  • the joining metal layer 25 to be provided on the frame body 5 may be omitted.
  • the joining portion 13 becomes to have a diffusion region 31 a formed on the substrate 31 , and the proportion of the metal of the low melting point decreases in the direction from the frame body 5 to the substrate 31 , and the proportion of copper increases in the same direction.
  • FIGS. 6A and 6B are enlarged partial and cross-sectional views illustrating a third modification of the forming process of the joining portion of the joined structural body according to the first embodiment.
  • a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5 .
  • the modification is different from the forming process illustrated in FIGS. 3A to 3C in that protective metal layers 33 , 35 are respectively provided on a surface portion of a substrate 3 containing copper i.e. a surface of a joining metal layer 23 , and on a surface of the joining metal layer 21 .
  • the metal of the low melting point contained in the joining metal layer 21 and the copper contained in the joining metal layer 23 are metals which are easy to be oxidized.
  • the oxidized layers prevents diffusion of the metal of the low melting point from the joining metal layer 21 to the joining metal layer 23 .
  • the protective metal layers 35 , 33 are formed on the respective surfaces of the joining metal layer 21 and the joining metal layer 23 in order to enhance the diffusion.
  • the protective metal layers 33 , 35 may be made using gold (Au), or platinum (Pt).
  • Au gold
  • Pt platinum
  • the protective metal layers 33 , 35 are introduced into the liquid phase.
  • the step results in forming a region 23 a where the metal of the low melting point is diffused from the surface i.e. a front surface of the joining metal layer 21 into the substrate 3 , and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 to a side of the frame body 5 .
  • the joining metal layers 23 , 25 are maintained in a state of contacting with each other via the joining metal layer 21 so that a joining portion as the joining portion 13 shown in FIG. 4C can be formed by fusion of the joining metal layers 21 , 23 and the joining metal layer 25 .
  • the joining portion 13 contains a high proportion of the metal of the low melting point at an intermediate position between the substrate 3 and the frame body 5 .
  • the proportion of the metal of the low melting point decreases toward both sides of the substrate 3 and the frame body 5
  • the proportion of copper increases toward both sides of the substrate 3 and the frame body 5 .
  • the joining portion becomes to contain at least one of gold (Au) or platinum (Pt) which are introduced from the protective metal layers 33 , 35 .
  • FIG. 7A is a schematic view illustrating a first modification of the package 10 according to the first embodiment.
  • FIG. 7A is a plan view of the package 10
  • FIG. 7B is an enlarged cross-sectional view taken along a VIIb-VIIb line in FIG. 7A .
  • FIG. 7B illustrates a cross section which includes feed through terminals 7 .
  • the feed through terminals 7 input signals into an electronic component (not shown) mounted to a component mounting portion 12 fixedly, and output signals from the electronic component.
  • the electronic component and leads 9 are connected by conductive plates (not shown), for example.
  • strip lines 7 b are formed on insulating material layers 7 a respectively, and the leads 9 are connected with the strip lines 7 b respectively.
  • the electronic component and the strip lines 7 b are connected by via wires (or conductive plates or ribbons).
  • the insulating material layers 7 a are formed using ceramics such as alumina (Al 2 O 3 ), for example.
  • the characteristic impedance of the strip lines 7 b is set to be 50 ⁇ so as to be matched with an external circuit. The matching can decrease transmission loss of high frequency signals between the electronic component and the external circuit.
  • an insulating material layer 7 c is formed on the insulating material layers 7 a via the strip lines 7 b.
  • the insulating material layer 7 c insulates the strip lines 7 b from the frame body 5 electrically.
  • the substrate 3 and the feed through terminals 7 are connected via a joining portion 13 a, and the frame body 5 and the feed through terminals 7 are joined via a joining portion 13 b.
  • the insulating material layers 7 a of the feed through terminals 7 and the substrate 3 are joined via the joining portion 13 a, and the insulating material layer 7 c and the frame body 5 are joined via the joining portion 13 b.
  • conductive layers 13 c are sandwiched between the strip lines 7 b provided in the feed through terminals 7 and the leads 9 .
  • a lid (not shown) may be fixed to an upper surface of the frame body 5 so as to sealing the inside hermetically.
  • the joining portions 13 a, 13 b contain at least one metal of a low melting point among tin (Sn), indium (In), and zinc (Zn), and copper (Cu), respectively.
  • the proportion of the metal of the low melting point decreases, and the proportion of copper increases, toward at least one of the insulating material layers 7 a and the substrate 3 .
  • the proportion of the metal of the low melting point decreases, and the proportion of copper increases, toward at least one side of the insulating material layer 7 c and the frame body 5 .
  • the joined structural body described in the first embodiment is provided with a joining portion produced by diffusing at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn) into a joining metal layer containing copper.
  • the structure present a package which can suppress warp and strain.
  • the temperature for diffusing the metal of the low melting point is not limited to the range of 250 to 300° C., and may be different depending on the kind of the metal of the low melting point. For example, when indium is used, diffusion can be performed under a range of lower temperature, and in a case of using zinc, diffusion can be performed under a range of higher temperature.
  • a package which contains an electronic component is described as an example, but the package is not limited to such a package.
  • the invention can be applied to a so-called carrier of a structure that members having strip lines are joined to a substrate.
  • At least one of the first member and the second member may be ceramics such as alumina (Al 2 O 3 ) or aluminum nitride (AlN).
  • FIGS. 8A and 8B are schematic views illustrating a package according to a second embodiment which is a semiconductor package.
  • FIG. 8A is a plan view of the package
  • FIG. 8B is an enlarged cross-sectional view taken along a VIIIb-VIIIb line illustrated in FIG. 8A .
  • a package 100 which is a semiconductor package contains a power transistor 41 for amplifying a high frequency signal as an electronic component.
  • the power transistor may be a Hetero Junction Field Effect Transistor (HFET) which uses GaN or SiC as a constituent material, or a Lateral Double Diffuse MOS Transistor (LDMOSFET) which uses silicon as a constituent material.
  • HFET Hetero Junction Field Effect Transistor
  • LDMOSFET Lateral Double Diffuse MOS Transistor
  • Both of the power transistors are power amplification elements, and operate with a large amount of heat generation. Accordingly, for the substrate 3 of the package 10 on which such an element mounted, a copper plate or a copper alloy which performs good heat dissipation is employed.
  • a power transistor 41 and two circuit boards 43 are mounted on a component mounting portion 12 of the package 100 .
  • Patterned conductive layers 43 a are formed on surfaces of the circuit boards 43 respectively.
  • the patterned conductive layers 43 a are electrically connected with a plurality of gate electrodes and a plurality of source electrodes (or drain electrodes) of the power transistor 41 via conductive wires 45 .
  • the patterned conductive layers 43 a and strip lines 7 b are electrically connected via wires 50 illustrated in FIG. 8B (or conductive plates or ribbons), respectively.
  • the circuit boards 43 are made of alumina (Al 2 O 3 ), for example.
  • the power transistor 41 and the circuit boards 43 are bonded to the substrate 3 .
  • the bonding may be carried out by using an AuSn solder.
  • the power transistor 41 and the substrate 3 are electrically connected with each other so as to enhance heat dissipation.
  • the power transistor 41 may be grounded via the substrate 3 .
  • a lid 49 is fixed on an upper surface of a frame body 5 so as to seal the transistor 41 hermetically.
  • a nitrogen gas or a similar gas is filled in the inside of the package 100 so as to make the operation of the transistor 41 stable and to enhance the reliability of the transistor 41 .
  • the lid 49 is soldered to the frame body 5 using AuSn, for example.
  • insulating material layers 7 a and an insulating material layer 7 c are provided.
  • the insulating material layers 7 a are formed on the substrate 3 .
  • the insulating material layers 7 a and the insulating material layer 7 c sandwich strip lines 7 b respectively.
  • the insulating material layer 7 c and the frame body 5 are joined via a joining portion 13 b.
  • the joining portion 13 b may be formed by a liquid phase diffusion of tin and copper. Such a joining process is performed under a temperature lower than a temperature of silver soldering so that warp or strain of the substrate 3 and the frame body 5 can be suppressed.
  • An operation temperature of a transistor which uses a wide-gap semiconductor material such as GaN or SiC reaches 600° C. Even in such a case, the melting point of the joining portion where tin is diffused into copper is above the operation temperature so that the transistor can be stably operated.
  • the package 100 according to the embodiment is not limited to using the transistor mentioned above.
  • a photo semiconductor element such as a LED or a laser element, or a piezo-electric element such as a SAW filter can be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

According to one embodiment, a joined structural body for mounting an electronic component on the body which is provided with a first member, a second member and a joining portion. The joining portion is provided between the first member and the second member so as to connect the first member and the second member with each other mechanically. The joining portion contains at least one metal of a tin, an indium or a zinc, and a copper. The content of the metal in the joining portion decreases toward a side of at least one of the first member and the second member, and the content of the copper in the joining portion increases in the same direction as the decreasing direction of the content of the metal.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-235385, filed on Oct. 26, 2011, the entire contents of which are incorporated herein by reference.
  • FIELD
  • Embodiments described herein relate generally to a joined structural body of members, a method of joining members, and a package for containing an electronic component.
  • BACKGROUND
  • An electronic component, which is represented by a semiconductor element, is bonded to a substrate which supports the electronic component. The electronic component bonded to the substrate is mounted on another substrate such as a mounting board. Many of the electronic components are hermetically sealed within a package provided with a substrate in order to enhance the reliability of the electronic components. Such a substrate or a package needs to be stable against a temperature during bonding or operation of the electronic component. Accordingly, a plurality of members which constitute such a substrate or a package is joined using a silver solder having a melting point higher than a bonding temperature of the electronic component normally, for example.
  • In general, the substrate or the package is a complex which includes a circuit element for use of input/output of a signal or power supply from a power source, and a heat radiation element for radiating heat from an electronic component to outside. Members constituting such a complex may have different linear expansion coefficients. When the members are assembled by a silver solder under a high temperature, a warp or a strain is generated in the members due to the difference of the linear expansion coefficients of the members. The warp or strain deteriorates a characteristic of an electronic component, and lowers the reliability of the electronic component. Thus, it is needed to present a joined structural body of members and a method of joining members which are stable against a temperature during bonding or operation of an electronic component and can suppress warp and strain.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a schematic plan view illustrating a package according to a first embodiment.
  • FIG. 1B is an enlarged cross-sectional view illustrating the package according to the first embodiment schematically.
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating a forming process of the package according to the first embodiment.
  • FIGS. 3A to 3C are schematic cross-sectional views illustrating a forming process of a joining portion of a joined structural body provided in the first embodiment.
  • FIGS. 4A to 4C are schematic cross-sectional views illustrating a first modification of the forming process of the joining portion of the joined structural body.
  • FIGS. 5A to 5C are schematic cross-sectional views illustrating a second modification of the forming process of the joining portion.
  • FIGS. 6A and 6B are schematic views illustrating a third modification of the forming process of the joining portion.
  • FIG. 7A is a schematic plan view illustrating a first modification of the package according to the first embodiment.
  • FIG. 7B is an enlarged cross-sectional view illustrating the first modification of the package according to the first embodiment schematically.
  • FIG. 8A is a schematic plan view illustrating a package according to a second embodiment.
  • FIG. 8B is an enlarged cross-sectional view illustrating the package according to the second embodiment schematically.
  • FIG. 9 is a two-element equilibrium diagram of copper and tin.
  • DETAILED DESCRIPTION
  • According to one embodiment, a joined structural body for mounting an electronic component on the body which is provided with a first member, a second member and a joining portion. The joining portion is provided between the first member and the second member so as to connect the first member and the second member with each other mechanically. The joining portion contains at least one metal of a tin, an indium or a zinc, and a copper. The content of the metal in the joining portion decreases toward a side of at least one of the first member and the second member, and the content of the copper in the joining portion increases in the same direction as the decreasing direction of the content of the metal.
  • Hereinafter, further embodiments will be described with reference to the drawings.
  • In the drawings, the same reference numerals denote the same or similar portions respectively.
  • A first embodiment will be described with reference to FIGS. 1A and 1B.
  • FIGS. 1A and 1B are schematic views illustrating a package according to the first embodiment. FIG. 1A is a plan view of the package, and FIG. 1B is a cross-sectional view taken along Ib-Ib line in FIG. 1A. The package contains an electronic element such as a semiconductor element, an optical semiconductor element or a piezo-electric element.
  • In FIG. 1A, a package 10 is provided with a substrate 3 as a first member, a frame body 5 as a second member, two feed through terminals 7. The substrate 3 has a component mounting portion 12 and flange portions 14. The component mounting portion 12 is provided to mount an electronic component and a circuit element around the electronic component fixedly. The flange portions 14 are provided to fix the substrate 3 to a mount board using screws. A frame body 5 is arranged on the substrate 3 fixedly so as to surround the component mounting portion 12. The frame body 5 defines a boundary between the flange portions 14 and the component mounting portion 12.
  • The feed through terminals 7 are arranged between the substrate 3 and the frame body 5 in an up-and-down direction. The feed through terminals 7 are provided so as to connect an electronic component which is mounted on the component mounting portion 12 and is hermetically sealed in the package 10 with an external circuit electrically. Two leads 9 which are connected with the external circuit are respectively connected to the feed through terminals 7. An electronic component and strip lines 7 b of the feed through terminals 7 can be respectively connected via wires (or conductive plates or ribbons).
  • As illustrated in FIG. 1B, the substrate 3 and the frame body 5 are connected via a joining portion 13. The substrate 3, the frame body 5, and the joining portion 13 constitute a joined structural body. It is emphasized that a package containing a power field effect transistor (power FET) for amplifying an electric power performs good heat dissipation. In consideration of heat dissipation, the substrate 3 is made of a metal having a high heat conductivity, such as copper (Cu) or an alloy of copper and molybdenum (Mo). On the other hand, the frame body 5 is required to have stiffness. Accordingly, the frame body 5 is made of a material such as a kovar i.e. an alloy which is produced by combining nickel (Ni) and cobalt (Co) with iron (Fe).
  • In manufacturing the package 10, an electronic component is bonded to a surface 3 a (a component mounting portion 12) of the substrate 3 by using a solder of gold (Au) and tin (Sn), for example. Further, a lid is fixed to an upper surface of the frame body 5 so as to seal the inside hermetically, if required. In the bonding process, the package 10 is heated to about 280 to 300° C. Accordingly, the remelting temperature of the joining portion 13 is desired to be more than or equal to 300° C. As the temperature difference between a bonding temperature and the remelting temperature (melting point) of the joining portion 13 becomes larger, the manufacture is stable more.
  • When a silver solder which is widely used as a joining material is employed, for example, bonding of an electronic component can be carried out stably against a bonding temperature since the melting point of the silver solder is more than or equal to 780° C. However, when the substrate 3 is made of a copper alloy, the frame body 5 is made of a kovar, and the substrate 3 and the frame body 5 are joined using a silver solder, warp or strain is large due to the difference between the linear thermal expansion coefficients of the substrate 3 and the frame body 5 during the cooling process of the silver solder, the substrate 3 and the frame body 5. It is because the melting point of the sliver solder is high,
  • As a result, when the package 10 which contains a semiconductor element is attached to a mount board, a gap is created between the rear surface 3 b of the substrate 3 and the mount board, which lowers performance of heat dissipation. Further, when one of the substrate 3 and the frame body 5 is formed of ceramics, a crack may be produced.
  • According to the embodiment, the joining portion 13 can be formed by a liquid phase diffusion of copper and tin. The liquid phase diffusion of copper and tin is caused within a temperature range of 250 to 300° C., which allows forming the joining portion 13 at a temperature lower than that of the silver solder. When the joining portion 13 is formed by such a method, warp or strain of the substrate 3 and the frame body 5 can be suppressed. The melting point of a chemical compound formed by a liquid phase diffusion of copper and tin is 750° C., for example, which is substantially the same as the melting point of a silver solder. Accordingly, the chemical compound is stable against a bonding temperature for an electronic component and an operating temperature of the electronic component.
  • Hereinafter, examples of forming process of the joining portion 13 and examples of the structure of the joining portion 13 will be described in detail. FIGS. 2A and 2B are cross-sectional views schematically illustrating an example of forming process of the package 10. FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, and FIGS. 6A to 6C are schematic cross-sectional views respectively illustrating examples of forming process of the joining portion 13.
  • In a manufacturing process of the package 10, the substrate 3 as the first member and the frame body 5 as the second member are prepared. As illustrated in FIG. 2A, a joining metal layer 21 is provided on a joining surface 5 a of the frame body 5. The joining metal layer 21 is a metal layer of at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn). On the other hand, a second joining metal layer 23 containing copper is provided on the surface 3 a of the substrate 3. When the substrate 3 is made of a copper, or a copper alloy containing copper as a main component, the joining metal layer 23 may be omitted.
  • As illustrated in FIG. 2B, the surface portion of the substrate 3 containing copper or the second joining metal layer 23 is brought into contact with a surface of the joining metal layer 21 formed on the frame body 5. A load is applied between the substrate 3 and the frame body 5 while maintaining contact of the substrate 3 and the frame body 5 with each other. Under this state, the substrate 3 and the frame body 5 are heated and maintained within a temperature range of 250 to 300° C. The metal of the low melting point contained in the joining metal layer 21 is melted by the heating so that the metal is diffused from the joining metal layer 21 in liquid phase state to a surface portion of the second joining metal layer 23 containing copper. In the example illustrated in FIG. 2B, the metal of the low melting point is diffused into the joining metal layer 23.
  • The joining metal layer 21 may be formed using a vacuum deposition, a sputtering, or plating. On the other hand, the joining metal layer 23 may be formed by sputtering copper on a surface of the substrate 3 and patterning a deposited copper layer to a predetermined shape. Further, adhesion layers containing titanium or nickel may be provided, respectively, between the joining metal layer 21 and the frame body 5, and between the joining metal layer 23 and the substrate 3, in order to strengthen adhesion.
  • FIGS. 3A to 3C are enlarged partial and cross-sectional views illustrating a process of forming the joining portion which constitutes the joined structural body between the substrate 3 and the frame body 5. As illustrated in FIG. 3A, a surface of the joining metal layer 21 is brought into contact with a surface of the joining metal layer 23, and a load is applied so as to maintain the contact of the joining metal layers 21, 23 with each other.
  • Then, the substrate 3 is heated, and the temperature of the joining metal layers 21, 23 is maintained within a range of 250 to 300° C., for example. As a result, as illustrated in FIG. 3B, the metal of the low melting point contained in the joining metal layer 21 is diffused into the joining metal layer 23 so that a diffusion region 23 a is formed.
  • As illustrated in FIG. 3C, the contact state is further maintained for a predetermined period under the temperature of 250 to 300° C. so that the joining portion 13 is formed by fusion of the joining metal layers 21, 23. As a result, the substrate 3 and the frame body 5 are joined with each other via the joining portion 13. Desirably, all of the metal of the low melting point is diffused into the joining metal layer 23 so that any solid phase metal does not remain.
  • The joining portion 13 contains at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn), and copper (Cu). The content of the metal of the low melting point decreases toward a side of the substrate 3, and the content of copper increases toward the side of the substrate 3.
  • For example, the joining metal layer 21 is made of a tin layer having a thickness of 4 μm, and the joining metal layer 23 is made of a copper layer having a thickness of 4 μm. The joining metal layers 21, 23 are brought into contact with each other. The joining metal layers 21, 23 are heated and maintained at 250° C. for about 30 minutes, for example. Under such a temperature, the joining portion 13 can be formed by diffusing tin into the joining metal layer 23 (a copper layer).
  • FIG. 9 shows a two-element equilibrium diagram of copper and tin. In FIG. 9, the vertical axis shows a temperature (° C.), and the horizontal axis shows a weight percentage (wt %) of tin. When the temperature of the joining metal layers 21, 23 is set to 250° C. which is higher than the melting point of tin i.e. 232° C., tin becomes a liquid phase state so that tin is diffused into the copper layer of a solid phase. Simultaneously, copper is diffused into the tin layer. As a result, copper and tin form a solid solution containing an a solid solution whose tin is less than or equal to about 15 wt %.
  • For example, when the solid solution is a composition containing copper of 90 wt % and tin of 10 wt % that is a composition indicated by a broken line extending vertically in FIG. 9, a large joining strength can be obtained without causing a phase change within a temperature range of about 330 to 820° C. Further, since a solid solution which is formed under the temperature range does not contain an inter-metallic compound (η layer) of Cu6Sn5 or an inter-metallic compound (ε layer) of Cu3Sn, a juncture having a resistance against a shock can be formed.
  • The thicknesses of the joining metal layers 21, 23 are set in consideration of a joining time and a joining strength. For example, when the thickness of the joining metal layer 21 is small, the unevenness of the joining surface cannot be sufficiently suppressed so that voids may be created, resulting in weakening the joining strength. In contrast, when the thickness is too large, the joining process needs a long time, resulting in lowering the manufacturing efficiency. Desirably, the thickness of the joining metal layer 21 is less than or equal to 10 μm, and more than or equal to 2 μm.
  • FIGS. 4A to 4C are enlarged partial and cross-sectional views illustrating a first modification of the forming process of the joining portion of the joined structural body according to the first embodiment. As illustrated in FIGS. 4A and 4B, the modification is different from the joined structure illustrated in FIGS. 3A and 4B in the point that a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5. The joining metal layer 25 is a metal containing copper. Further, an adhesion layer containing titanium or nickel may be provided between the joining metal layer 25 and the frame body 5.
  • As illustrated in FIG. 4B, a surface of the joining metal layer 21 and a surface of a joining metal layer 23 are brought into contact with each other, and maintained within a range of 250 to 300° C., for example. This step results in forming a region 23 a where a metal of a low melting point is diffused from a front surface of the joining metal layer 21 into a side of a substrate 3, and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 into a side of a frame body 5.
  • Subsequently, as illustrated in FIG. 4C, a joining portion 13 is formed by fusing the joining metal layer 21 and the joining metal layers 23, 25. In the joining portion 13, a region containing a high proportion of the metal of the low melting point is formed at an intermediate position between the substrate 3 and the frame body 5. The proportion of the metal of the low melting point decreases toward both sides of the substrate 3 and the frame body 5, and the proportion of copper increases toward both sides of the substrate 3 and the frame body 5.
  • As schematically illustrated in FIG. 4C, the metal of the low melting point contained in the joining metal layer 21 is desired to be completely diffused so as to be integral with the joining metal layer 23 and the joining metal layer 25. However, the joined structure may be configured by a first layer containing copper provided on a side of the substrate 3, and a second layer containing copper provided on a side of the frame body 5.
  • FIGS. 5A to 5C are enlarged partial and cross-sectional views illustrating a second modification of the forming process of the joining portion of the joined structural body according to the first embodiment. The modification is different from the forming process illustrated in FIGS. 3A to 3C in that any layer as the joining metal layer 23 is not provided on a surface of a substrate 31, and in that a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5 as illustrated in FIG. 5A. The substrate 31 is made of copper or an alloy containing copper as a main component.
  • As illustrated in FIG. 5B, a surface of the joining metal layer 21 and a surface of the substrate 31 are brought into contact with each other, and maintained within a range of 250 to 300° C., for example. The step results in forming a region 31 a where a metal of a low melting point is diffused from a front surface of the joining metal layer 21 into the substrate 31, and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 into a side of the frame body 5.
  • Then, as illustrated in FIG. 5C, a joining portion 13 is formed by fusing the joining metal layer 21, the substrate 31 and the joining metal layer 25. In this case, the joining portion 13 becomes to have a region 31 a which is formed by diffusing the metal of the low melting point into the substrate 31. In the joining portion 13, a region containing a high proportion of the metal of the low melting point is formed at an intermediate position between the substrate 31 and the frame body 5. The proportion of the metal of the low melting point decreases toward both sides of the substrate 31 and the frame body 5, and the proportion of copper increases toward both sides of the substrate 31 and the frame body 5.
  • In the modification, the joining metal layer 25 to be provided on the frame body 5 may be omitted. In this case, the joining portion 13 becomes to have a diffusion region 31 a formed on the substrate 31, and the proportion of the metal of the low melting point decreases in the direction from the frame body 5 to the substrate 31, and the proportion of copper increases in the same direction.
  • FIGS. 6A and 6B are enlarged partial and cross-sectional views illustrating a third modification of the forming process of the joining portion of the joined structural body according to the first embodiment. As illustrated in FIG. 6A, in the modification, a joining metal layer 25 is provided between a joining metal layer 21 and a frame body 5. Further, the modification is different from the forming process illustrated in FIGS. 3A to 3C in that protective metal layers 33, 35 are respectively provided on a surface portion of a substrate 3 containing copper i.e. a surface of a joining metal layer 23, and on a surface of the joining metal layer 21.
  • The metal of the low melting point contained in the joining metal layer 21 and the copper contained in the joining metal layer 23 are metals which are easy to be oxidized. When oxidized layers are formed on the surface of the joining metal layer 21 and the surface of the joining metal layer 23, the oxidized layers prevents diffusion of the metal of the low melting point from the joining metal layer 21 to the joining metal layer 23. The protective metal layers 35, 33 are formed on the respective surfaces of the joining metal layer 21 and the joining metal layer 23 in order to enhance the diffusion.
  • The protective metal layers 33, 35 may be made using gold (Au), or platinum (Pt). The protective metal layer 35 provided on the surface of the joining metal layer 21 and the protective metal layer 33 provided on the surface of the joining metal layer 23 are brought into contact with each other, and maintained in a range of 250 to 300° C., for example.
  • Under the temperature range, when the metal of the low melting point contained in the joining metal layer 21 is melted, the protective metal layers 33, 35 are introduced into the liquid phase. As illustrated in FIG. 6B, the step results in forming a region 23 a where the metal of the low melting point is diffused from the surface i.e. a front surface of the joining metal layer 21 into the substrate 3, and results in forming a region 25 a where the metal of the low melting point is diffused from a rear surface of the joining metal layer 21 to a side of the frame body 5.
  • The joining metal layers 23, 25 are maintained in a state of contacting with each other via the joining metal layer 21 so that a joining portion as the joining portion 13 shown in FIG. 4C can be formed by fusion of the joining metal layers 21, 23 and the joining metal layer 25.
  • The joining portion 13 contains a high proportion of the metal of the low melting point at an intermediate position between the substrate 3 and the frame body 5. The proportion of the metal of the low melting point decreases toward both sides of the substrate 3 and the frame body 5, and the proportion of copper increases toward both sides of the substrate 3 and the frame body 5. Further, the joining portion becomes to contain at least one of gold (Au) or platinum (Pt) which are introduced from the protective metal layers 33, 35.
  • FIG. 7A is a schematic view illustrating a first modification of the package 10 according to the first embodiment. FIG. 7A is a plan view of the package 10, and FIG. 7B is an enlarged cross-sectional view taken along a VIIb-VIIb line in FIG. 7A. FIG. 7B illustrates a cross section which includes feed through terminals 7. As described above for the first embodiment with reference to FIGS. 1A and 1B, the feed through terminals 7 input signals into an electronic component (not shown) mounted to a component mounting portion 12 fixedly, and output signals from the electronic component. The electronic component and leads 9 are connected by conductive plates (not shown), for example.
  • As illustrated in FIG. 7A, in the feed through terminals 7, strip lines 7 b are formed on insulating material layers 7 a respectively, and the leads 9 are connected with the strip lines 7 b respectively. The electronic component and the strip lines 7 b are connected by via wires (or conductive plates or ribbons). The insulating material layers 7 a are formed using ceramics such as alumina (Al2O3), for example. Further, the characteristic impedance of the strip lines 7 b is set to be 50 Ω so as to be matched with an external circuit. The matching can decrease transmission loss of high frequency signals between the electronic component and the external circuit.
  • Further, as illustrated in FIG. 7B, in the feed through terminals 7, an insulating material layer 7 c is formed on the insulating material layers 7 a via the strip lines 7 b. The insulating material layer 7 c insulates the strip lines 7 b from the frame body 5 electrically.
  • In order to fix the feed through terminals 7 having the above-mentioned structure between the substrate 3 and the frame body 5, the substrate 3 and the feed through terminals 7 are connected via a joining portion 13 a, and the frame body 5 and the feed through terminals 7 are joined via a joining portion 13 b. As illustrated in FIG. 7B, the insulating material layers 7 a of the feed through terminals 7 and the substrate 3 are joined via the joining portion 13 a, and the insulating material layer 7 c and the frame body 5 are joined via the joining portion 13 b.
  • Further, conductive layers 13 c are sandwiched between the strip lines 7 b provided in the feed through terminals 7 and the leads 9. A lid (not shown) may be fixed to an upper surface of the frame body 5 so as to sealing the inside hermetically.
  • The joining portions 13 a, 13 b contain at least one metal of a low melting point among tin (Sn), indium (In), and zinc (Zn), and copper (Cu), respectively. In the joining portion 13 a, the proportion of the metal of the low melting point decreases, and the proportion of copper increases, toward at least one of the insulating material layers 7 a and the substrate 3. In the joining portion 13 b, the proportion of the metal of the low melting point decreases, and the proportion of copper increases, toward at least one side of the insulating material layer 7 c and the frame body 5.
  • As described above, the joined structural body described in the first embodiment is provided with a joining portion produced by diffusing at least one metal of a low melting point among tin (Sn), indium (In) or zinc (Zn) into a joining metal layer containing copper. The structure present a package which can suppress warp and strain.
  • The temperature for diffusing the metal of the low melting point is not limited to the range of 250 to 300° C., and may be different depending on the kind of the metal of the low melting point. For example, when indium is used, diffusion can be performed under a range of lower temperature, and in a case of using zinc, diffusion can be performed under a range of higher temperature.
  • Further, in the first embodiment mentioned above, a package which contains an electronic component is described as an example, but the package is not limited to such a package. For example, the invention can be applied to a so-called carrier of a structure that members having strip lines are joined to a substrate.
  • Further, in the first embodiment, at least one of the first member and the second member may be ceramics such as alumina (Al2O3) or aluminum nitride (AlN).
  • FIGS. 8A and 8B are schematic views illustrating a package according to a second embodiment which is a semiconductor package. FIG. 8A is a plan view of the package, and FIG. 8B is an enlarged cross-sectional view taken along a VIIIb-VIIIb line illustrated in FIG. 8A.
  • In FIGS. 8A and 8B, a package 100 which is a semiconductor package contains a power transistor 41 for amplifying a high frequency signal as an electronic component. The power transistor may be a Hetero Junction Field Effect Transistor (HFET) which uses GaN or SiC as a constituent material, or a Lateral Double Diffuse MOS Transistor (LDMOSFET) which uses silicon as a constituent material. Both of the power transistors are power amplification elements, and operate with a large amount of heat generation. Accordingly, for the substrate 3 of the package 10 on which such an element mounted, a copper plate or a copper alloy which performs good heat dissipation is employed.
  • As illustrated in FIG. 8A, a power transistor 41 and two circuit boards 43 are mounted on a component mounting portion 12 of the package 100. Patterned conductive layers 43 a are formed on surfaces of the circuit boards 43 respectively. The patterned conductive layers 43 a are electrically connected with a plurality of gate electrodes and a plurality of source electrodes (or drain electrodes) of the power transistor 41 via conductive wires 45. The patterned conductive layers 43 a and strip lines 7 b are electrically connected via wires 50 illustrated in FIG. 8B (or conductive plates or ribbons), respectively. The circuit boards 43 are made of alumina (Al2O3), for example.
  • As illustrated in FIG. 8B, the power transistor 41 and the circuit boards 43 are bonded to the substrate 3. The bonding may be carried out by using an AuSn solder. By the bonding, the power transistor 41 and the substrate 3 are electrically connected with each other so as to enhance heat dissipation. The power transistor 41 may be grounded via the substrate 3.
  • Further, a lid 49 is fixed on an upper surface of a frame body 5 so as to seal the transistor 41 hermetically. A nitrogen gas or a similar gas is filled in the inside of the package 100 so as to make the operation of the transistor 41 stable and to enhance the reliability of the transistor 41. The lid 49 is soldered to the frame body 5 using AuSn, for example.
  • In the package 100, insulating material layers 7 a and an insulating material layer 7 c are provided. The insulating material layers 7 a are formed on the substrate 3. The insulating material layers 7 a and the insulating material layer 7 c sandwich strip lines 7 b respectively. The insulating material layer 7 c and the frame body 5 are joined via a joining portion 13 b. The joining portion 13 b may be formed by a liquid phase diffusion of tin and copper. Such a joining process is performed under a temperature lower than a temperature of silver soldering so that warp or strain of the substrate 3 and the frame body 5 can be suppressed. As a result, when a rear surface of the substrate 3 is adhered to a mount board or a heat sink, heat which is generated in the power transistor 41 can be efficiently dissipated. Accordingly, the operation of the power transistor can be stable, and the reliability of the power transistor can be enhanced.
  • An operation temperature of a transistor which uses a wide-gap semiconductor material such as GaN or SiC reaches 600° C. Even in such a case, the melting point of the joining portion where tin is diffused into copper is above the operation temperature so that the transistor can be stably operated.
  • The package 100 according to the embodiment is not limited to using the transistor mentioned above. A photo semiconductor element such as a LED or a laser element, or a piezo-electric element such as a SAW filter can be used.
  • While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims (19)

What is claimed is:
1. A joined structural body for mounting an electronic component on the body, comprising:
a first member;
a second member; and
a joining portion provided between the first member and the second member so as to connect the first member and the second member with each other mechanically, the joining portion containing at least one metal of a tin, an indium or a zinc, and a copper, the content of the metal in the joining portion decreasing toward a side of at least one of the first member and the second member, the content of the copper in the joining portion increasing in the same direction as the decreasing direction of the content of the metal.
2. The joined structural body according to claim 1, wherein the content of the metal decreases toward both sides of the first member and the second member, and the content of the copper increases toward both sides of the first member and the second member.
3. The joined structural body according to claim 2, wherein the joining portion includes a first layer containing copper which is provided on a side of the first member, and a second layer containing copper which is provided on a side of the second member.
4. The joined structural body according to claim 1, wherein the joining portion contains at least one of a gold or a platinum.
5. The joined structural body according to claim 2, wherein the joining portion contains at least one of a gold or a platinum.
6. The joined structural body according to claim 3, wherein the joining portion contains at least one of a gold or a platinum.
7. The joined structural body according to claim 1, wherein the first member is made of one of a copper or a copper alloy, and the second member is made of an alloy containing an iron.
8. The joined structural body according to claim 1, wherein at least one of the first member and the second member contains a ceramic material.
9. A method of joining members which forms a joined structural body for mounting an electronic component on the body, comprising:
bringing a surface of a first member containing a copper into contact with a surface of a first joining metal layer of at least one metal of a tin (Sn), an indium (In) or a zinc (Zn) which is formed on a second member, and
heating the first member and the second member so as to diffuse the at least one metal from the surface of the first member containing the copper into an inside of the first member while maintaining the contact between the first member and the first joining metal layer.
10. The method of joining members according to claim 9, wherein a second joining metal layer containing a copper is formed on the surface of the first member, and a surface of the second joining metal layer and the surface of the first joining metal layer are brought into contact with each other.
11. The method of joining members according to claim 9, wherein a third joining metal layer containing a copper is formed between the first member and the first joining metal layer.
12. The method of joining members according to claim 10, wherein a third joining metal layer containing a copper is formed between the first member and the first joining metal layer.
13. The method of joining members according to claim 9, wherein protective metal layers are provided on the surface of the first member and the surface of the first joining metal layer respectively.
14. The method of joining members according to claim 13, wherein the protective metal layers contains at least one of a gold or a platinum.
15. A package comprising:
a substrate on which an electronic component is mounted; and
a frame body which surrounds a portion on which the electronic component is mounted, the frame body being joined mechanically with the substrate via a joining portion containing at least one metal of a tin, an indium or a zinc, and a copper,
wherein the content of the at least one metal in the joining portion decreases toward a side of at least one of the substrate or the fame body, and the content of the copper in the joining portion increases in the same direction as the decreasing direction of the content of the at least one metal.
16. The package according to claim 15, further comprising a feed through terminals for inputting a signal into the electronic component and for outputting a signal from the electronic component respectively, wherein
the joining portion includes a first joining portion and a second joining portion, and
the substrate and the feed through terminals are joined via the first joining portion, and the frame body and the feed through terminals are joined via the second joining portion.
17. The package according to claim 15, wherein
the content of the metal decreases toward both sides of the substrate and the frame body, and
the content of the copper increases toward both sides of the substrate and the frame body.
18. The package according to claim 15, wherein the joining portion has a first layer containing a copper which is provided on a side of the substrate, and a second layer containing a copper which is provided on a side of the frame body.
19. The package according to claim 15, wherein the joining portion contains at least one of a gold or a platinum.
US13/558,765 2011-10-26 2012-07-26 Joined structural body of members, joining method of members, and package for containing an electronic component Abandoned US20130105205A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/524,282 US9357644B2 (en) 2011-10-26 2014-10-27 Joined structural body of members, joining method of members, and package for containing an electronic component

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011235385A JP5588419B2 (en) 2011-10-26 2011-10-26 package
JP2011-235385 2011-10-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14/524,282 Division US9357644B2 (en) 2011-10-26 2014-10-27 Joined structural body of members, joining method of members, and package for containing an electronic component

Publications (1)

Publication Number Publication Date
US20130105205A1 true US20130105205A1 (en) 2013-05-02

Family

ID=47002542

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/558,765 Abandoned US20130105205A1 (en) 2011-10-26 2012-07-26 Joined structural body of members, joining method of members, and package for containing an electronic component
US14/524,282 Expired - Fee Related US9357644B2 (en) 2011-10-26 2014-10-27 Joined structural body of members, joining method of members, and package for containing an electronic component

Family Applications After (1)

Application Number Title Priority Date Filing Date
US14/524,282 Expired - Fee Related US9357644B2 (en) 2011-10-26 2014-10-27 Joined structural body of members, joining method of members, and package for containing an electronic component

Country Status (6)

Country Link
US (2) US20130105205A1 (en)
EP (1) EP2587532A3 (en)
JP (1) JP5588419B2 (en)
KR (1) KR101476504B1 (en)
CN (1) CN103077934B (en)
TW (1) TWI471986B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130286566A1 (en) * 2012-04-27 2013-10-31 Canon Kabushiki Kaisha Electronic component, mounting member, electronic apparatus, and their manufacturing methods
US9013034B2 (en) 2013-04-15 2015-04-21 Kabushiki Kaisha Toshiba Semiconductor package
US9041190B2 (en) 2013-04-15 2015-05-26 Kabushiki Kaisha Toshiba Semiconductor package
US20150249046A1 (en) * 2014-02-28 2015-09-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9220172B2 (en) 2012-04-27 2015-12-22 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
US9253922B2 (en) 2012-04-27 2016-02-02 Canon Kabushiki Kaisha Electronic component and electronic apparatus
US20160105984A1 (en) * 2014-10-09 2016-04-14 International Rectifier Corporation Power Unit with Conductive Slats
US20170162525A1 (en) * 2015-12-03 2017-06-08 Kabushiki Kaisha Toshiba High frequency semiconductor amplifier
US20190006254A1 (en) * 2017-06-30 2019-01-03 Kyocera International, Inc. Microelectronic package construction enabled through ceramic insulator strengthening and design
US10224291B2 (en) * 2016-06-23 2019-03-05 Kabushiki Kaisha Toshiba Semiconductor device package with strip line structure and high frequency semiconductor device thereof

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10568213B2 (en) 2014-07-31 2020-02-18 Skyworks Solutions, Inc. Multilayered transient liquid phase bonding
JP6365215B2 (en) * 2014-10-15 2018-08-01 三菱電機株式会社 Manufacturing method of semiconductor device
CN105537756B (en) * 2016-01-29 2018-06-26 山东大学 A kind of cryogenic vacuum diffusion connection method of copper and zinc-containing alloy
CN106252422A (en) * 2016-08-23 2016-12-21 太仓市威士达电子有限公司 A kind of metal shell for packaging of photoelectric device
US20180159502A1 (en) * 2016-12-02 2018-06-07 Skyworks Solutions, Inc. Methods of manufacturing electronic devices to prevent water ingress during manufacture
EP3560304B1 (en) 2016-12-23 2021-02-03 ATOTECH Deutschland GmbH Method of forming a solderable solder deposit on a contact pad
CN108366500A (en) * 2018-01-03 2018-08-03 佛山杰致信息科技有限公司 A kind of electronic component protection structure
KR102325114B1 (en) * 2019-12-06 2021-11-11 제엠제코(주) Manufacturing method of semiconductor package

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6241145B1 (en) * 1999-04-22 2001-06-05 Mitsubishi Denki Kabushiki Kaisha Lead-free solder joining method and electronic module manufactured by using the method
US20020045330A1 (en) * 1998-11-20 2002-04-18 Angst David L. Kinetically controlled solder bonding
US20020090756A1 (en) * 2000-10-04 2002-07-11 Masamoto Tago Semiconductor device and method of manufacturing the same
US6755958B2 (en) * 2000-12-11 2004-06-29 Handy & Harman Barrier layer for electrical connectors and methods of applying the layer
US20040266048A1 (en) * 2002-02-27 2004-12-30 Honeywell International Inc. Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices
US20050218525A1 (en) * 2004-03-31 2005-10-06 Kabushiki Kaisha Toshiba Soldered material, semiconductor device, method of soldering, and method of manufacturing semiconductor device
US20050242419A1 (en) * 2004-04-30 2005-11-03 Philliber Joel A Method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method
US20080176096A1 (en) * 2007-01-22 2008-07-24 Yen-Hang Cheng Solderable layer and a method for manufacturing the same
US20100193801A1 (en) * 2007-11-20 2010-08-05 Toyota Jidosha Kabushiki Kaisha Solder material, method for manufacturing the same, joined body, method for manufacturing the same, power semiconductor module, and method for manufacturing the same
US20100247955A1 (en) * 2006-09-29 2010-09-30 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same
US20100276039A1 (en) * 2009-04-29 2010-11-04 Golden Dragon Precise Copper Tube Group Inc. Copper alloy, method of producing the same, and copper tube
US20110132656A1 (en) * 2008-08-21 2011-06-09 Murata Manufacturing, Co., Ltd. Electronic Component Device and Method for Manufacturing the Same
US20110223718A1 (en) * 2005-08-31 2011-09-15 Osamu Ikeda Semiconductor device and automotive ac generator
US20110233792A1 (en) * 2008-09-18 2011-09-29 Imec Methods and systems for material bonding
US20110233750A1 (en) * 2008-12-09 2011-09-29 Robert Bosch Gmbh Arrangement of Two Substrates having an SLID Bond and Method for Producing such an Arrangement
US20110291282A1 (en) * 2009-02-05 2011-12-01 Toyota Jidosha Kabushiki Kaisha Junction body, semiconductor module, and manufacturing method for junction body
US20120321907A1 (en) * 2010-03-02 2012-12-20 Sensonor Technologies As Bonding process for sensitive micro- and nano-systems
US20130043594A1 (en) * 2011-08-10 2013-02-21 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and semiconductor device
US8381964B2 (en) * 2009-01-22 2013-02-26 National Central University Tin-silver bonding and method thereof

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784974A (en) * 1982-08-05 1988-11-15 Olin Corporation Method of making a hermetically sealed semiconductor casing
US5155299A (en) * 1988-10-05 1992-10-13 Olin Corporation Aluminum alloy semiconductor packages
JPH0766949B2 (en) * 1990-09-28 1995-07-19 富士通株式会社 IC package
US6271579B1 (en) * 1993-10-08 2001-08-07 Stratedge Corporation High-frequency passband microelectronics package
JP3500268B2 (en) * 1997-02-27 2004-02-23 京セラ株式会社 High frequency input / output terminal and high frequency semiconductor element storage package using the same
KR19990069950A (en) * 1998-02-16 1999-09-06 윤종용 Flip chip bonding structure and manufacturing method of solder bump using same
JP2005032834A (en) * 2003-07-08 2005-02-03 Toshiba Corp Joining method of semiconductor chip and substrate
JP2005274560A (en) * 2004-02-27 2005-10-06 Fuji Electric Holdings Co Ltd Method for mounting filter for radiation detector
JP2006013241A (en) * 2004-06-28 2006-01-12 Matsushita Electric Ind Co Ltd Semiconductor device and package therefor
JP4519637B2 (en) * 2004-12-28 2010-08-04 株式会社東芝 Semiconductor device
US7754343B2 (en) * 2005-08-17 2010-07-13 Oracle America, Inc. Ternary alloy column grid array
WO2008149584A1 (en) * 2007-06-04 2008-12-11 Murata Manufacturing Co., Ltd. Electronic part apparatus and process for manufacturing the same
JP5376356B2 (en) * 2008-08-19 2013-12-25 国立大学法人大阪大学 Electronic element mounting method and electronic component mounted by the mounting method
US20100091477A1 (en) * 2008-10-14 2010-04-15 Kabushiki Kaisha Toshiba Package, and fabrication method for the package
EP2259307B1 (en) * 2009-06-02 2019-07-03 Napra Co., Ltd. Electronic device
JP5450313B2 (en) * 2010-08-06 2014-03-26 株式会社東芝 High frequency semiconductor package and manufacturing method thereof
JP5269864B2 (en) * 2010-12-07 2013-08-21 株式会社東芝 Semiconductor device
JP2014049700A (en) * 2012-09-03 2014-03-17 Toshiba Corp Junction structure of member, method of joining the same, and package
JP2014207389A (en) * 2013-04-15 2014-10-30 株式会社東芝 Semiconductor package
JP2014207388A (en) * 2013-04-15 2014-10-30 株式会社東芝 Semiconductor package

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020045330A1 (en) * 1998-11-20 2002-04-18 Angst David L. Kinetically controlled solder bonding
US6241145B1 (en) * 1999-04-22 2001-06-05 Mitsubishi Denki Kabushiki Kaisha Lead-free solder joining method and electronic module manufactured by using the method
US20020090756A1 (en) * 2000-10-04 2002-07-11 Masamoto Tago Semiconductor device and method of manufacturing the same
US6755958B2 (en) * 2000-12-11 2004-06-29 Handy & Harman Barrier layer for electrical connectors and methods of applying the layer
US20040266048A1 (en) * 2002-02-27 2004-12-30 Honeywell International Inc. Bonding for a micro-electro-mechanical system (MEMS) and MEMS based devices
US20050218525A1 (en) * 2004-03-31 2005-10-06 Kabushiki Kaisha Toshiba Soldered material, semiconductor device, method of soldering, and method of manufacturing semiconductor device
US20050242419A1 (en) * 2004-04-30 2005-11-03 Philliber Joel A Method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method
US20110223718A1 (en) * 2005-08-31 2011-09-15 Osamu Ikeda Semiconductor device and automotive ac generator
US20100247955A1 (en) * 2006-09-29 2010-09-30 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same
US20080176096A1 (en) * 2007-01-22 2008-07-24 Yen-Hang Cheng Solderable layer and a method for manufacturing the same
US20100193801A1 (en) * 2007-11-20 2010-08-05 Toyota Jidosha Kabushiki Kaisha Solder material, method for manufacturing the same, joined body, method for manufacturing the same, power semiconductor module, and method for manufacturing the same
US20110132656A1 (en) * 2008-08-21 2011-06-09 Murata Manufacturing, Co., Ltd. Electronic Component Device and Method for Manufacturing the Same
US20110233792A1 (en) * 2008-09-18 2011-09-29 Imec Methods and systems for material bonding
US20110233750A1 (en) * 2008-12-09 2011-09-29 Robert Bosch Gmbh Arrangement of Two Substrates having an SLID Bond and Method for Producing such an Arrangement
US8381964B2 (en) * 2009-01-22 2013-02-26 National Central University Tin-silver bonding and method thereof
US20110291282A1 (en) * 2009-02-05 2011-12-01 Toyota Jidosha Kabushiki Kaisha Junction body, semiconductor module, and manufacturing method for junction body
US20100276039A1 (en) * 2009-04-29 2010-11-04 Golden Dragon Precise Copper Tube Group Inc. Copper alloy, method of producing the same, and copper tube
US20120321907A1 (en) * 2010-03-02 2012-12-20 Sensonor Technologies As Bonding process for sensitive micro- and nano-systems
US20130043594A1 (en) * 2011-08-10 2013-02-21 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Yibo Rong et al: "Low temperature Cu-Sn bonding by isothermal solidification technology", Electronic Packaging Technology&High Density Packaging, 2009, ICEPT-HDP '09. International Conference on, IEEE, Piscataway, N J, USA, 10 August 2009 (2009-08-10), pages 96-98, XP031533513, ISBN: 978-1-4244-4658-2 *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9253922B2 (en) 2012-04-27 2016-02-02 Canon Kabushiki Kaisha Electronic component and electronic apparatus
US20130286566A1 (en) * 2012-04-27 2013-10-31 Canon Kabushiki Kaisha Electronic component, mounting member, electronic apparatus, and their manufacturing methods
US9155212B2 (en) * 2012-04-27 2015-10-06 Canon Kabushiki Kaisha Electronic component, mounting member, electronic apparatus, and their manufacturing methods
US9220172B2 (en) 2012-04-27 2015-12-22 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
US9013034B2 (en) 2013-04-15 2015-04-21 Kabushiki Kaisha Toshiba Semiconductor package
US9041190B2 (en) 2013-04-15 2015-05-26 Kabushiki Kaisha Toshiba Semiconductor package
US20150249046A1 (en) * 2014-02-28 2015-09-03 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9466558B2 (en) * 2014-02-28 2016-10-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20160105984A1 (en) * 2014-10-09 2016-04-14 International Rectifier Corporation Power Unit with Conductive Slats
US20170162525A1 (en) * 2015-12-03 2017-06-08 Kabushiki Kaisha Toshiba High frequency semiconductor amplifier
US9947628B2 (en) * 2015-12-03 2018-04-17 Kabushiki Kaisha Toshiba High frequency semiconductor amplifier
US10224291B2 (en) * 2016-06-23 2019-03-05 Kabushiki Kaisha Toshiba Semiconductor device package with strip line structure and high frequency semiconductor device thereof
US20190006254A1 (en) * 2017-06-30 2019-01-03 Kyocera International, Inc. Microelectronic package construction enabled through ceramic insulator strengthening and design

Also Published As

Publication number Publication date
JP5588419B2 (en) 2014-09-10
EP2587532A2 (en) 2013-05-01
US9357644B2 (en) 2016-05-31
KR101476504B1 (en) 2014-12-24
EP2587532A3 (en) 2014-02-19
US20150043186A1 (en) 2015-02-12
CN103077934A (en) 2013-05-01
CN103077934B (en) 2016-05-18
JP2013093472A (en) 2013-05-16
TW201330192A (en) 2013-07-16
TWI471986B (en) 2015-02-01
KR20130045797A (en) 2013-05-06

Similar Documents

Publication Publication Date Title
US9357644B2 (en) Joined structural body of members, joining method of members, and package for containing an electronic component
US7446411B2 (en) Semiconductor structure and method of assembly
JP6128448B2 (en) Semiconductor light emitting device
JP4610414B2 (en) Electronic component storage package, electronic device, and electronic device mounting structure
US20140063757A1 (en) Joint structure of package members, method for joining same, and package
JP6788044B2 (en) Package with built-in thermoelectric element
US12040301B2 (en) Semiconductor device
US9013034B2 (en) Semiconductor package
CN102593081A (en) Semiconductor device including a heat spreader
US20130112993A1 (en) Semiconductor device and wiring substrate
JP2014053384A (en) Semiconductor device and method of manufacturing the same
JP2006190728A (en) Electric power semiconductor device
JP5479667B2 (en) Semiconductor power module
JP2013187303A (en) Semiconductor device, manufacturing method of the same and mounting member
JP4608409B2 (en) High heat dissipation type electronic component storage package
JP2013187418A (en) Semiconductor device, manufacturing method of the same and mounting member
JP2015026667A (en) Semiconductor module
JP2010010345A (en) Semiconductor package and semiconductor light-emitting apparatus
US8946885B2 (en) Semiconductor arrangement and method for producing a semiconductor arrangement
JP2019110280A (en) Method of manufacturing semiconductor device
JP2013077741A (en) Semiconductor device, semiconductor element with joint metal layer, mounting member, and method of manufacturing semiconductor device
JP2014036165A (en) Semiconductor device
WO2021172015A1 (en) Semiconductor device
JP2010098144A (en) Lead frame and semiconductor device
JP2008117841A (en) Semiconductor power module, and method for manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TAKAGI, KAZUTAKA;REEL/FRAME:028647/0541

Effective date: 20120719

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION