JP2013077741A - Semiconductor device, semiconductor element with joint metal layer, mounting member, and method of manufacturing semiconductor device - Google Patents

Semiconductor device, semiconductor element with joint metal layer, mounting member, and method of manufacturing semiconductor device Download PDF

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JP2013077741A
JP2013077741A JP2011217427A JP2011217427A JP2013077741A JP 2013077741 A JP2013077741 A JP 2013077741A JP 2011217427 A JP2011217427 A JP 2011217427A JP 2011217427 A JP2011217427 A JP 2011217427A JP 2013077741 A JP2013077741 A JP 2013077741A
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metal
metal layer
bonding
semiconductor element
mounting member
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Kazutaka Takagi
一考 高木
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Toshiba Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can operate even at or higher than a junction temperature of a semiconductor element with a mounting member, and its manufacturing method.SOLUTION: A semiconductor device includes a substrate 31 having a surface which contains a first metal, and a frame part 36 which has a first insulating material 32 provided to an outer peripheral region 31a and a conductive part 33 provided on the first insulating material. A semiconductor element 20 is electrically connectable to the conductive part. A junction metal layer 50 includes a second metal, a third metal dispersed in the second metal, and a fourth metal dispersed in the second metal. Further, the junction metal layer can connect the semiconductor element with an inner region by a solid solution layer in which weight percent of the second metal is higher than weight percent of the third metal while weight percent of the third metal is higher than weight percent of the fourth metal.

Description

本発明の実施形態は、半導体装置、接合金属層付き半導体素子、実装部材、並びに半導体装置の製造方法に関する。   Embodiments described herein relate generally to a semiconductor device, a semiconductor element with a bonding metal layer, a mounting member, and a method for manufacturing the semiconductor device.

半導体素子の線膨張係数と、実装部材の線膨張係数と、は、通常は異なる。このため、絶縁材や金属板からなる実装部材上に半導体素子を接着した後の降温工程において、実装部材に反りが生じることがある。高出力半導体装置に用いられる実装部材は、例えばサイズが１０ｍｍ×１０ｍｍなどと大きくなるので、反りが大きくなる。このため、半導体装置と放熱板との間に空隙部を生じ、放熱性が低下するなどの問題がある。   The linear expansion coefficient of the semiconductor element and the linear expansion coefficient of the mounting member are usually different. For this reason, the mounting member may be warped in the temperature lowering process after the semiconductor element is bonded onto the mounting member made of an insulating material or a metal plate. Since the mounting member used in the high-power semiconductor device is large, for example, with a size of 10 mm × 10 mm, the warp is large. For this reason, there is a problem that a gap is formed between the semiconductor device and the heat radiating plate, and heat dissipation is reduced.

半導体素子と、実装部材と、の接合強度を保ちつつ、反りを抑制するために、融点が２８０度近傍のＡｕＳｎ共晶半田材が用いられることがある。しかしながら、半田材の融点以上では、半導体素子が剥がれたりずれたりすることがある。   An AuSn eutectic solder material having a melting point of about 280 degrees may be used to suppress warping while maintaining the bonding strength between the semiconductor element and the mounting member. However, the semiconductor element may be peeled off or displaced above the melting point of the solder material.

このため、ＡｕＳｎのような低い融点を有する金属を半田材として用いることは困難である。   For this reason, it is difficult to use a metal having a low melting point such as AuSn as a solder material.

特開２００５−３２８３４号公報JP 2005-32834 A

半導体素子と実装部材との接合温度以上でも動作可能な半導体装置およびその製造方法、接合金属層付き半導体素子、並びに実装部材を提供する。   Provided are a semiconductor device that can operate even at a temperature equal to or higher than a bonding temperature between a semiconductor element and a mounting member, a manufacturing method thereof, a semiconductor element with a bonding metal layer, and a mounting member.

本発明の実施形態の半導体装置は、実装部材と、半導体素子と、接合金属層と、を有する。実装部材は、第１の金属を含む面を有する基板と、前記基板の前記面の外周領域に設けられた第１の絶縁材と前記第１の絶縁材の上に設けられた導電部とを有する枠部と、を有する。半導体素子は、前記基板の前記面の内部領域の上に設けられ、前記導電部と電気的に接続可能である。接合金属層は、銅および銅合金のいずれかである第２の金属と、前記第２の金属内に分散され、錫、亜鉛、およびインジウムのいずれかである第３の金属と、前記第２の金属内に分散され金および白金のうちのいずれかである第４の金属と、を有する。また、接合金属層は、前記第２の金属の重量百分率が前記第３の金属の重量百分率よりも高く、かつ前記第３の金属の重量百分率が前記第４の金属の重量百分率よりも高い固溶体層により、前記半導体素子と前記内部領域とを接合可能である。   A semiconductor device according to an embodiment of the present invention includes a mounting member, a semiconductor element, and a bonding metal layer. The mounting member includes a substrate having a surface containing a first metal, a first insulating material provided in an outer peripheral region of the surface of the substrate, and a conductive portion provided on the first insulating material. Having a frame portion. The semiconductor element is provided on an internal region of the surface of the substrate and can be electrically connected to the conductive portion. The bonding metal layer includes a second metal that is one of copper and a copper alloy, a third metal that is dispersed in the second metal and is one of tin, zinc, and indium, and the second metal And a fourth metal that is either gold or platinum dispersed in the metal. Further, the bonding metal layer is a solid solution in which the weight percentage of the second metal is higher than the weight percentage of the third metal, and the weight percentage of the third metal is higher than the weight percentage of the fourth metal. The semiconductor element and the internal region can be joined by the layer.

図１（ａ）は第１の実施形態にかかる半導体装置の模式平面図、図１（ｂ）はＡ−Ａ線の沿った模式断面図、である。FIG. 1A is a schematic plan view of the semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view taken along the line AA. 図２は、第１の実施形態の半導体装置の製造方法を説明する模式図であり、図２（ａ）は基板と枠部と積層体の断面図、図２（ｂ）は基板の上に、第２の金属、第４の金属、第３の金属、を積層した実装部材の断面図、図２（ｃ）は接合金属層付き半導体素子の断面図、図２（ｄ）は加熱・加圧前の断面図、図２（ｅ）は接合後の断面図、である。2A and 2B are schematic views for explaining the method of manufacturing the semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view of the substrate, the frame portion, and the stacked body, and FIG. , A second metal, a fourth metal, a third metal, a cross-sectional view of a mounting member, FIG. 2C is a cross-sectional view of a semiconductor element with a bonding metal layer, FIG. FIG. 2E is a cross-sectional view before bonding, and FIG. 2E is a cross-sectional view after bonding. 銅−錫２元素平衡状態図である。It is a copper-tin 2 element equilibrium state figure. 図４は、第１の実施形態の半導体装置の製造方法の変形例を説明する模式図であり、図４（ａ）は基板と枠部と積層体の断面図、図４（ｂ）は基板の上に、第２の金属、第４の金属、を積層した実装部材の断面図、図４（ｃ）は接合金属層付き半導体素子の断面図、図４（ｄ）は第３の金属を薄層の断面図、図４（ｅ）は加熱・加圧前の断面図、図４（ｆ）は接合後の断面図、である。4A and 4B are schematic views for explaining a modification of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4A is a cross-sectional view of the substrate, the frame portion, and the stacked body, and FIG. FIG. 4C is a cross-sectional view of a semiconductor element with a bonding metal layer, and FIG. 4D is a cross-sectional view of a third metal. FIG. 4E is a sectional view before heating and pressurizing, and FIG. 4F is a sectional view after joining. 図５（ａ）は第２の実施形態にかかる半導体装置の模式平面図、図５（ｂ）はＡ−Ａ線の沿った模式断面図、である。FIG. 5A is a schematic plan view of the semiconductor device according to the second embodiment, and FIG. 5B is a schematic cross-sectional view taken along the line AA. 図６は、第２の実施形態の半導体装置の製造方法を説明する模式図であり、図６（ａ）は基板と枠部と積層体の断面図、図６（ｂ）は基板の上に、第２の金属、第４の金属、を積層した実装部材の断面図、図６（ｃ）は接合金属層付き半導体素子の断面図、図６（ｄ）は導電パターン基板の断面図、図６（ｅ）は加熱・加圧前の断面図、図６（ｆ）は接合後の断面図、である。6A and 6B are schematic views for explaining a method of manufacturing a semiconductor device according to the second embodiment. FIG. 6A is a cross-sectional view of a substrate, a frame portion, and a stacked body, and FIG. FIG. 6C is a cross-sectional view of a semiconductor element with a bonding metal layer, FIG. 6D is a cross-sectional view of a conductive pattern substrate, and FIG. 6 (e) is a cross-sectional view before heating and pressurization, and FIG. 6 (f) is a cross-sectional view after bonding. 図７（ａ）は第３の実施形態にかかる半導体装置の模式平面図、図７（ｂ）はＢ−Ｂ線に沿った模式断面図、である。FIG. 7A is a schematic plan view of a semiconductor device according to the third embodiment, and FIG. 7B is a schematic cross-sectional view taken along the line BB.

図１（ａ）は第１の実施形態にかかる半導体装置の模式平面図であり、図１（ｂ）はＡ−Ａ線の沿った模式断面図である。
半導体装置は、例えば、ＧａＡｓ ＦＥＴ（Field Effect Transistor)またはＧａＡｓ ＨＥＭＴ（High Electron Mobility Transistor)である。半導体装置は、半導体素子２０と、実装部材４０と、接合金属層５０と、を有する。 FIG. 1A is a schematic plan view of the semiconductor device according to the first embodiment, and FIG. 1B is a schematic cross-sectional view along the line AA.
The semiconductor device is, for example, a GaAs FET (Field Effect Transistor) or a GaAs HEMT (High Electron Mobility Transistor). The semiconductor device includes a semiconductor element 20, a mounting member 40, and a bonding metal layer 50.

半導体素子２０は、第１の面２０ａと、第１の面２０ａとは反対の側の第２の面２０ｂと、を有する。第１の面２０ａは、ドレイン、ゲート、ソース、などを含む能動領域を有する。能動領域は、ＧａＡｓからなる半絶縁性基板に設けられている。   The semiconductor element 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The first surface 20a has an active region including a drain, a gate, a source, and the like. The active region is provided on a semi-insulating substrate made of GaAs.

実装部材４０は、基板３１と、枠部３６と、を少なくとも有する。基板３１は、第１の金属を含む面に、外周領域３１ａおよび内部領域３１ｂを有する。半導体素子２０の第２の面２０ｂと、第１の面２０ａと、の間は高抵抗であるので、基板３１が導電性であっても能動領域と基板３１とを絶縁可能である。   The mounting member 40 includes at least a substrate 31 and a frame portion 36. The board | substrate 31 has the outer peripheral area | region 31a and the internal area | region 31b in the surface containing a 1st metal. Since the resistance between the second surface 20b of the semiconductor element 20 and the first surface 20a is high, the active region and the substrate 31 can be insulated even if the substrate 31 is conductive.

枠部３６は、外周領域３１ａに設けられた第１の絶縁材３２および第１の絶縁材３２の上に設けられた導電部３３を有する。なお、枠部３６は、導電部３３の上に設けられ、外方に向かって突出した２つのリード３５ａ、３５ｂと、第３の絶縁材３４と、をさらに有していてもよい。ＧａＡｓ ＦＥＴのゲート電極は入力側ボンディングワイヤ２２および導電部を介してリード３５ａと接続され、ドレイン電極は出力側ボンディングワイヤ２３および導電部３３を介してリード３５ｂと接続され、ソース電極は接地ボンディングワイヤ２４により基板３１の表面の第１の金属を含む面に接続される。なお、第１の金属を含む面は、第１の金属以外の金属を含んでいてもよい。   The frame portion 36 includes a first insulating material 32 provided in the outer peripheral region 31 a and a conductive portion 33 provided on the first insulating material 32. The frame portion 36 may further include two leads 35a and 35b provided on the conductive portion 33 and projecting outward, and a third insulating material 34. The gate electrode of the GaAs FET is connected to the lead 35a through the input side bonding wire 22 and the conductive portion, the drain electrode is connected to the lead 35b through the output side bonding wire 23 and the conductive portion 33, and the source electrode is connected to the ground bonding wire. 24 is connected to the surface of the substrate 31 including the first metal. Note that the surface including the first metal may include a metal other than the first metal.

また、実装部材４０は、蓋部３８をさらに有することができる。蓋部３８を第３の絶縁材３４と接合することにより半導体素子を気密封止することができる。   The mounting member 40 can further include a lid portion 38. The semiconductor element can be hermetically sealed by bonding the lid portion 38 to the third insulating material 34.

接合金属層５０は、銅（Ｃｕ）および銅合金のいずれかである第２の金属と、第２の金属内に分散され、錫（Ｓｎ）、亜鉛（Ｚｎ）、およびインジウム（Ｉｎ）のいずれかである第３の金属と、第２の金属内に分散され金（Ａｕ）および白金（Ｐｔ）のいずれかである第４の金属と、を有する。なお、銅合金は、例えば、２．３ｗｔ％（重量百分率）の鉄（Ｆｅ）、０．１ｗｔ％の亜鉛、０．０３ｗｔ％の燐（Ｐ）などを含むことができる。銅合金は、ＣｕＷやＣｕＭｏなどであってもよい。   The bonding metal layer 50 is dispersed in the second metal, which is either copper (Cu) or a copper alloy, and any of tin (Sn), zinc (Zn), and indium (In). And a fourth metal which is either gold (Au) or platinum (Pt) dispersed in the second metal. The copper alloy can include, for example, 2.3 wt% (weight percentage) of iron (Fe), 0.1 wt% of zinc, 0.03 wt% of phosphorus (P), and the like. The copper alloy may be CuW or CuMo.

また、接合金属層５０は、第２の金属と、第２の金属内に分散された第３の金属と、第２の金属内に分散された第４の金属と、を含む固溶体層４９を有している。   The bonding metal layer 50 includes a solid solution layer 49 including a second metal, a third metal dispersed in the second metal, and a fourth metal dispersed in the second metal. Have.

例えば、接合金属層５０は、基板３１の側に設けられ、第２の金属からなる第１接合金属層４５と、半導体素子２０の側に設けられ、第２の金属からなる第２接合金属層４８と、第１接合金属層４５と第２接合金属層４８との間に設けられた固溶体層４９と、を有してもよい。また、接合金属層５０は、すべて固溶体層４９であってもよい。   For example, the bonding metal layer 50 is provided on the substrate 31 side, and the first bonding metal layer 45 made of the second metal and the second bonding metal layer made of the second metal provided on the semiconductor element 20 side. 48 and a solid solution layer 49 provided between the first bonding metal layer 45 and the second bonding metal layer 48 may be included. Further, the bonding metal layer 50 may be the solid solution layer 49.

図２は、第１の実施形態の半導体装置の製造方法を説明する模式図であり、図２（ａ）は基板と枠部と積層体の断面図、図２（ｂ）は基板の上に、第２の金属、第４の金属、第３の金属、を積層した実装部材の断面図、図２（ｃ）は接合金属層付き半導体素子の断面図、図２（ｄ）は加熱・加圧前の断面図、図２（ｅ）は接合後の断面図、である。   2A and 2B are schematic views for explaining the method of manufacturing the semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view of the substrate, the frame portion, and the stacked body, and FIG. , A second metal, a fourth metal, a third metal, a cross-sectional view of a mounting member, FIG. 2C is a cross-sectional view of a semiconductor element with a bonding metal layer, FIG. FIG. 2E is a cross-sectional view before bonding, and FIG. 2E is a cross-sectional view after bonding.

図２（ａ）のように、第１の絶縁材３２の上に設けられた導電部３３と第３の絶縁材３４とは、例えば、焼成されて一体となっている。金属からなる基板３１の外周領域３１ａと第１の絶縁材３２との間、および導電部３３とリード３５との間、などは、銀ロウ材により接合されている。   As shown in FIG. 2A, the conductive portion 33 and the third insulating material 34 provided on the first insulating material 32 are, for example, baked and integrated. Between the outer peripheral region 31a of the substrate 31 made of metal and the first insulating material 32, between the conductive portion 33 and the lead 35, and the like are joined by a silver brazing material.

図２（ｂ）に表したように、基板３１の表面の第１の金属を含む面に、銅および銅合金のいずれかである第２の金属からなる第１接合金属層４５と、第１接合金属層４５の上に設けられ、金および白金のいずれかである第４の金属からなる保護金属層４７と、保護金属層４７の上に設けられ、錫、亜鉛、およびインジウムのいずれかである第３の金属からなる第３接合金属層４６と、をマスク蒸着法、スパッタ法、および選択メッキ法などを用いて内部領域３１ｂに形成する。銅などからなる第１接合金属層４５の表面は、酸化しやすい。このため、金などの第４の金属からなる保護金属層４７でその表面を覆うと酸化を抑制することができる。   As shown in FIG. 2B, a first bonding metal layer 45 made of a second metal, which is either copper or a copper alloy, is formed on the surface of the surface of the substrate 31 including the first metal, and the first metal A protective metal layer 47 made of a fourth metal, which is either gold or platinum, provided on the bonding metal layer 45, and provided on the protective metal layer 47, and made of any one of tin, zinc, and indium. A third bonding metal layer 46 made of a third metal is formed in the inner region 31b by using a mask vapor deposition method, a sputtering method, a selective plating method, or the like. The surface of the first bonding metal layer 45 made of copper or the like is easily oxidized. For this reason, if the surface is covered with the protective metal layer 47 made of the fourth metal such as gold, the oxidation can be suppressed.

また、第１接合金属層４５の厚さは、例えば１〜１０μｍなどとできる。第２接合金属層４８の厚さは、例えば１〜１０μｍとすることができる。   Moreover, the thickness of the 1st joining metal layer 45 can be 1-10 micrometers etc., for example. The thickness of the second bonding metal layer 48 can be set to 1 to 10 μm, for example.

他方、図２（ｃ）に表したように、半導体素子２０の第２の面２０ｂに、銅および銅合金のいずれかの第２の金属からなる第２接合金属層４８と、金および白金のいずれかからなる保護金属層４１と、を積層することにより接合金属層つき半導体素子２１が完成する。   On the other hand, as shown in FIG. 2C, the second surface 20 b of the semiconductor element 20 is formed on the second bonding metal layer 48 made of any second metal of copper and copper alloy, and gold and platinum. The semiconductor element 21 with the bonding metal layer is completed by laminating the protective metal layer 41 made of any of the above.

続いて、図２（ｄ）に表したように、半導体素子２０の側の保護金属層４１と、基板３１の側の第３接合金属層４６と、を重ね合わせる。続いて、第３の金属の融点以上に加熱し、第３接合金属層４６を液相状態とする。さらに半導体素子２０と基板３１とに所定の圧力Ｐを加えつつ、所定の温度で所定の時間保持することにより、固溶体層４９を形成し半導体素子２０と基板３１の内部領域とを接合する。例えば、所定の温度は２５０℃、保持時間は３０分、所定の圧力Ｐは、０．０１ＭＰａ以上とすることができる。このようにして、図２（ｅ）に表したように接合工程が完了する。   Subsequently, as illustrated in FIG. 2D, the protective metal layer 41 on the semiconductor element 20 side and the third bonding metal layer 46 on the substrate 31 side are overlaid. Then, it heats more than melting | fusing point of a 3rd metal, and makes the 3rd joining metal layer 46 a liquid state. Further, by applying a predetermined pressure P to the semiconductor element 20 and the substrate 31 and holding it at a predetermined temperature for a predetermined time, a solid solution layer 49 is formed and the semiconductor element 20 and the internal region of the substrate 31 are joined. For example, the predetermined temperature can be 250 ° C., the holding time can be 30 minutes, and the predetermined pressure P can be 0.01 MPa or more. In this way, the joining process is completed as shown in FIG.

保持時間が長くなりすぎると生産性が低下する。本実施形態では、銅などの酸化が抑制できるので水素を用いた還元炉を用いる必要がない。このため、窒素などの不活性ガス雰囲気中で、１時間以内で接合工程が完了するので生産性を高く保つことができる。   If the holding time is too long, the productivity is lowered. In this embodiment, since oxidation of copper or the like can be suppressed, it is not necessary to use a reduction furnace using hydrogen. For this reason, since a joining process is completed within 1 hour in inert gas atmosphere, such as nitrogen, productivity can be kept high.

他方、共晶半田の融点は、ＡｕＳｎで略２８２℃、ＡｕＧｅで略３５０℃、ＡｕＳｉで 略３８０℃などである。このため、基板の反りや半導体素子のクラックなどを生じることがある。これに対して、本実施形態では、融点の低い錫を用いることができるので、基板の反りおよび半導体素子のクラックなどを抑制できる。   On the other hand, the melting point of eutectic solder is approximately 282 ° C. for AuSn, approximately 350 ° C. for AuGe, approximately 380 ° C. for AuSi, and the like. For this reason, the curvature of a board | substrate, the crack of a semiconductor element, etc. may arise. On the other hand, in this embodiment, since tin with a low melting point can be used, warpage of the substrate, cracks in the semiconductor element, and the like can be suppressed.

図３は、銅−錫２元素平衡状態図である。
縦軸は温度（℃）、横軸は錫の重量百分率（ｗｔ％）、である。所定温度を錫の融点２３２℃よりも高い２５０℃とすると錫は液相状態となる。液相状態の錫には、所定圧力が加えられつつ、所定の温度で所定の時間保持される。この結果、錫は、銅金属内に拡散される。同時に銅も錫の側に拡散される。この結果、銅と錫とは、錫が略１５ｗｔ％以下となるα固溶体を含む固溶体層４９を形成する。 FIG. 3 is a copper-tin two-element equilibrium diagram.
The vertical axis represents temperature (° C.), and the horizontal axis represents tin weight percentage (wt%). If the predetermined temperature is 250 ° C. which is higher than the melting point 232 ° C. of tin, tin will be in a liquid phase. The liquid phase tin is held at a predetermined temperature for a predetermined time while a predetermined pressure is applied. As a result, tin is diffused into the copper metal. At the same time, copper is diffused to the tin side. As a result, copper and tin form a solid solution layer 49 containing an α solid solution in which tin is about 15 wt% or less.

例えば、固溶体が、９０ｗｔ％の銅と、１０ｗｔ％の錫と、を含む組成（破線）であるものとする。固溶体層４９は、略３３０〜８２０℃の温度範囲において、相変化を生じることなく、高い接合強度を保つことができる。   For example, it is assumed that the solid solution has a composition (broken line) containing 90 wt% copper and 10 wt% tin. The solid solution layer 49 can maintain a high bonding strength without causing a phase change in a temperature range of approximately 330 to 820 ° C.

本実施形態では、錫のような第３の金属の重量百分率よりも低い百分率を有する金などの第４の金属が固溶体層４９に拡散される。   In the present embodiment, a fourth metal such as gold having a percentage lower than the weight percentage of the third metal such as tin is diffused into the solid solution layer 49.

なお、銅−亜鉛２元素平衡状態図では、銅の重量百分率が略６０％以上の範囲に固溶体層が形成できる。   In the copper-zinc two-element equilibrium diagram, a solid solution layer can be formed in a range where the weight percentage of copper is approximately 60% or more.

もし、銅などの第１接合金属層４５の表面に酸化膜を生じていると、錫などの第３接合金属層４６が、均一に銅内に拡散されにくい。本実施形態では、銅の表面に金などの保護金属層４１、４７を設けることにより銅の酸化を抑制している。金などの第４の金属の重量百分率は、Ｓｎなどの第３の金属の重量百分率よりも低くてよい。すなわち、金の厚さは、例えば５００オングストローム以下であっても酸化を抑制することは容易であり、２元素平衡状態を乱すことは殆どない。微量金属の重量百分率は、例えばＳＩＭＳ（Secondary Ion Mas Spectrometry：二次イオン質量分析法）を用いると測定できる。   If an oxide film is formed on the surface of the first bonding metal layer 45 such as copper, the third bonding metal layer 46 such as tin is not easily diffused into the copper. In the present embodiment, copper oxidation is suppressed by providing protective metal layers 41 and 47 such as gold on the surface of copper. The weight percentage of the fourth metal such as gold may be lower than the weight percentage of the third metal such as Sn. That is, even if the thickness of gold is, for example, 500 angstroms or less, it is easy to suppress oxidation and hardly disturb the two-element equilibrium state. The weight percentage of the trace metal can be measured by using, for example, SIMS (Secondary Ion Mas Spectrometry).

固溶体層４９は、Ｃｕ６Ｓｎ５の金属間化合物（η層）やＣｕ３Ｓｎの金属間化合物（ε層）を含まないので、接合強度を高く保つことができる。 Since the solid solution layer 49 does not contain an intermetallic compound of Cu 6 Sn 5 (η layer) or an intermetallic compound of Cu 3 Sn (ε layer), the bonding strength can be kept high.

もし錫が固相で残っていると、温度が融点以上において液相化し半導体素子２０が基板３１からずれたり剥離する可能性がある。本実施形態では、錫はすべて銅内に拡散され固溶体を形成しているので接合強度を高く保つことができる。他方、銅の融点は高いので、銅層が残っても接合強度を高く保つことができる。   If tin remains in a solid phase, there is a possibility that the semiconductor element 20 is displaced from the substrate 31 or peeled off at a temperature higher than the melting point. In this embodiment, since all the tin is diffused into copper to form a solid solution, the bonding strength can be kept high. On the other hand, since the melting point of copper is high, the bonding strength can be kept high even if the copper layer remains.

図４は、第１の実施形態の半導体装置の製造方法の変形例を説明する模式図であり、図４（ａ）は基板と枠部と積層体の断面図、図４（ｂ）は基板の上に、第２の金属、第４の金属、を積層した実装部材の断面図、図４（ｃ）は接合金属層付き半導体素子の断面図、図４（ｄ）は第３の金属を薄層の断面図、図４（ｅ）は加熱・加圧前の断面図、図４（ｆ）は接合後の断面図、である。   4A and 4B are schematic views for explaining a modification of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4A is a cross-sectional view of the substrate, the frame portion, and the stacked body, and FIG. FIG. 4C is a cross-sectional view of a semiconductor element with a bonding metal layer, and FIG. 4D is a cross-sectional view of a third metal. FIG. 4E is a sectional view before heating and pressurizing, and FIG. 4F is a sectional view after joining.

図４（ａ）は、基板３１と枠部と積層体の模式断面図である。本変形例では、図４（ｂ）に表したように、第２の金属からなる第１接合金属層４５の表面に第４の金属からなる保護金属層４７が設けられている。このため、この状態で長時間保存しても銅の酸化を抑制することができる。接合金属層付き半導体素子２１は、図４（ｃ）に表したような断面構造を有する。   FIG. 4A is a schematic cross-sectional view of the substrate 31, the frame portion, and the laminate. In the present modification, as shown in FIG. 4B, a protective metal layer 47 made of the fourth metal is provided on the surface of the first bonding metal layer 45 made of the second metal. For this reason, even if it preserve | saves for a long time in this state, the oxidation of copper can be suppressed. The semiconductor element 21 with the bonding metal layer has a cross-sectional structure as shown in FIG.

図４（ｄ）に表したように、錫などの第３接合金属層４６は、厚さが３〜２０μｍなどのシート状とすることができる。図４（ｂ）に表した基板３１の側の保護金属層４７と、接合金属付き半導体素子２１と、の間にシート状の第３接合金属層４６を配置する。   As shown in FIG. 4D, the third bonding metal layer 46 such as tin can be formed into a sheet shape having a thickness of 3 to 20 μm. A sheet-like third bonding metal layer 46 is disposed between the protective metal layer 47 on the substrate 31 side shown in FIG. 4B and the semiconductor element 21 with bonding metal.

図４（ｅ）に表したように、第３接合金属４６をその融点以上に加熱し、液相状態とする。半導体素子２０と基板３１とに所定の圧力Ｐを加えつつ、所定の温度で所定の時間保持する。例えば、所定の圧力Ｐは０．０１ＭＰａ、所定の温度は２５０℃、保持時間は３０分、などとすることができる。また、第３接合金属層４６を半導体素子２０の側の保護金属層４１に設けてもよい。このようにして、図４（ｆ）に表したように、接合工程が完了する。   As shown in FIG. 4E, the third bonding metal 46 is heated to the melting point or higher to be in a liquid phase state. While applying a predetermined pressure P to the semiconductor element 20 and the substrate 31, it is held at a predetermined temperature for a predetermined time. For example, the predetermined pressure P can be 0.01 MPa, the predetermined temperature can be 250 ° C., the holding time can be 30 minutes, and the like. Further, the third bonding metal layer 46 may be provided on the protective metal layer 41 on the semiconductor element 20 side. In this way, the joining process is completed as shown in FIG.

図５（ａ）は第２の実施形態にかかる半導体装置の模式平面図、図５（ｂ）はＡ−Ａ線の沿った模式断面図、である。
半導体装置は、例えば、高出力ＧａＡｓ ＦＥＴとする。半導体装置は、半導体素子２０と、実装部材４０と、導電パターン基板６０と、接合金属層５０と、を有する。 FIG. 5A is a schematic plan view of the semiconductor device according to the second embodiment, and FIG. 5B is a schematic cross-sectional view taken along the line AA.
The semiconductor device is, for example, a high output GaAs FET. The semiconductor device includes a semiconductor element 20, a mounting member 40, a conductive pattern substrate 60, and a bonding metal layer 50.

導電パターン基板６０は、第２の絶縁材６２と、その上面に設けられた導電パターン６６と、を有する。また、導電パターン基板６０の下面に、第２の金属からなる第４接合金属層６４、第４の金属からなる保護金属層６５と、を積層して接合金属層付き導電パターン基板６１とすることができる。導電パターン基板６０は、リード３５ａと半導体素子２０との間に設けられた第１の導電パターン６０ａと、リード３５ｂと半導体素子２０との間に設けられた第２の導電パターン基板６０ｂ、とを含むことができる。導電パターン基板６０は、半導体素子２０、２１と、同時に接合してもよい。   The conductive pattern substrate 60 includes a second insulating material 62 and a conductive pattern 66 provided on the upper surface thereof. Further, a conductive pattern substrate 61 with a bonding metal layer is formed by laminating a fourth bonding metal layer 64 made of a second metal and a protective metal layer 65 made of a fourth metal on the lower surface of the conductive pattern substrate 60. Can do. The conductive pattern substrate 60 includes a first conductive pattern 60a provided between the lead 35a and the semiconductor element 20, and a second conductive pattern substrate 60b provided between the lead 35b and the semiconductor element 20. Can be included. The conductive pattern substrate 60 may be bonded to the semiconductor elements 20 and 21 at the same time.

半導体素子２０が、マイクロ波のような高い周波数で動作するものとすると、入力および出力インピーダンスは外部の伝送線路の特性インピーダンス（例えば５０Ω）と整合容易であることが好ましい。この場合、半導体素子２０の近傍にインピーダンス整合回路を設けると広い増幅帯域で整合することが容易となる。例えば、図５（ａ）のように、導電パターンからなるストリップラインの幅を変えることによっても整合回路とすることができる。すなわち、半導体素子２０の特性に応じて、接合金属層付き導電パターン基板６１を変えることが容易となる。   Assuming that the semiconductor element 20 operates at a high frequency such as a microwave, it is preferable that the input and output impedances can be easily matched with the characteristic impedance (eg, 50Ω) of the external transmission line. In this case, if an impedance matching circuit is provided in the vicinity of the semiconductor element 20, matching with a wide amplification band is facilitated. For example, as shown in FIG. 5A, a matching circuit can be obtained by changing the width of a strip line made of a conductive pattern. That is, it becomes easy to change the conductive pattern substrate 61 with the bonding metal layer according to the characteristics of the semiconductor element 20.

図６は、第２の実施形態の半導体装置の製造方法を説明する模式図であり、図６（ａ）は基板と枠部と積層体の断面図、図６（ｂ）は基板の上に、第２の金属、第４の金属、を積層した実装部材の断面図、図６（ｃ）は接合金属層付き半導体素子の断面図、図６（ｄ）は導電パターン基板の断面図、図６（ｅ）は加熱・加圧前の断面図、図６（ｆ）は接合後の断面図、である。   6A and 6B are schematic views for explaining a method of manufacturing a semiconductor device according to the second embodiment. FIG. 6A is a cross-sectional view of a substrate, a frame portion, and a stacked body, and FIG. FIG. 6C is a cross-sectional view of a semiconductor element with a bonding metal layer, FIG. 6D is a cross-sectional view of a conductive pattern substrate, and FIG. 6 (e) is a cross-sectional view before heating and pressurization, and FIG. 6 (f) is a cross-sectional view after bonding.

まず、図６（ａ）に表したような断面構造を有する基板と枠部との積層体を準備する。そして、図６（ｂ）に表したように、基板の上に、第１接合金属層４５、保護金属層４７、第３接合金属層を形成する。接合金属層付き半導体素子は、図６（ｃ）に表したような断面構造を有する。図６（ｄ）に表したように、セラミックなどからなる絶縁材６２の一方の面に導電パターン６６を形成し導電パターン基板６０とする。さらに、導電パターン基板６０の他方の面に、第２の金属からなる第４接合金属層６４と、第４の金属からなる保護金属層６５と、を積層し接合金属層付き導電パターン基板６１とすることができる。   First, a laminate of a substrate and a frame having a cross-sectional structure as shown in FIG. Then, as shown in FIG. 6B, a first bonding metal layer 45, a protective metal layer 47, and a third bonding metal layer are formed on the substrate. The semiconductor element with a bonding metal layer has a cross-sectional structure as shown in FIG. As shown in FIG. 6D, a conductive pattern 66 is formed on one surface of an insulating material 62 made of ceramic or the like to form a conductive pattern substrate 60. Furthermore, a fourth bonding metal layer 64 made of a second metal and a protective metal layer 65 made of a fourth metal are laminated on the other surface of the conductive pattern substrate 60, and a conductive pattern substrate 61 with a bonding metal layer is formed. can do.

そして、図６（ｅ）に表したように、半導体素子２０および導電パターン基板６０ａ、６０ｂの上方から所定の圧力Ｐを加え、所定の温度で加熱しつつ、所定の時間保持する。例えば、所定の圧力Ｐは０．０１ＭＰａ、所定の温度は２５０℃、保持時間は３０分、などとすることができる。このようにして、図６（ｆ）に表したように、半導体素子２０と、導電パターン基板６０と、を、基板３１にそれぞれ接合できる。   Then, as shown in FIG. 6E, a predetermined pressure P is applied from above the semiconductor element 20 and the conductive pattern substrates 60a and 60b, and the substrate is held at a predetermined temperature and held for a predetermined time. For example, the predetermined pressure P can be 0.01 MPa, the predetermined temperature can be 250 ° C., the holding time can be 30 minutes, and the like. In this way, the semiconductor element 20 and the conductive pattern substrate 60 can be bonded to the substrate 31 as shown in FIG.

図７（ａ）は第３の実施形態にかかる半導体装置の模式平面図、図７（ｂ）はＢ−Ｂ線に沿った模式断面図、である。
能動領域が導電性基板の上に設けられているバイポーラトランジスタやＩＧＢＴ（Insulated Gate Bipolar Transistor)などの場合、半導体素子２０の第２の面２０ｂは、例えばコレクタ領域であることが多い。この場合、基板７２は、絶縁材７２ａと、接地領域７２ｂ、島領域７２ｃと、を有する。 FIG. 7A is a schematic plan view of a semiconductor device according to the third embodiment, and FIG. 7B is a schematic cross-sectional view taken along the line BB.
In the case of a bipolar transistor or IGBT (Insulated Gate Bipolar Transistor) in which the active region is provided on a conductive substrate, the second surface 20b of the semiconductor element 20 is often a collector region, for example. In this case, the substrate 72 includes an insulating material 72a, a ground region 72b, and an island region 72c.

バイポーラトランジスタのチップは、周囲の接地領域７２ｂと絶縁された島領域７２ｃに接合される。島領域７２ｃは、出力側ボンディングワイヤ２３で導電部３３ｂと接続されコレクタとなる。通常エミッタは接地されるのでエミッタ電極は、接地ボンディングワイヤ２４により接地領域７２ｂに接続される。また、ベース電極は、入力側ボンディングワイヤ２２により導電部３３ａと接続されベース端子となる。また、パワーＭＯＳＦＥＴの場合、半導体基板の側のバックゲートを接地から絶縁することができる。   The bipolar transistor chip is bonded to an island region 72c that is insulated from the surrounding ground region 72b. The island region 72c is connected to the conductive portion 33b by the output-side bonding wire 23 and becomes a collector. Since the emitter is normally grounded, the emitter electrode is connected to the ground region 72b by the ground bonding wire 24. The base electrode is connected to the conductive portion 33a by the input-side bonding wire 22 and becomes a base terminal. In the case of a power MOSFET, the back gate on the semiconductor substrate side can be insulated from the ground.

半導体素子２０の材料がシリコン（Ｓｉ）の場合、バンドギャップエネルギーは略１．１２ｅＶであり、動作温度を２００℃以上とすることが困難である。他方、ワイドバンドギャップ半導体では、高温動作が容易である。例えば、バンドギャップエネルギーは、炭化珪素（ＳｉＣ）で２．２〜３．０２ｅＶ、窒化ガリウム（ＧａＮ）で略３．３９ｅＶ、と高い。このため、ワイドバンドギャップ材料を用いると、ＭＯＳＦＥＴやＩＧＢＴを、例えば、３００℃以上で動作可能である。   When the material of the semiconductor element 20 is silicon (Si), the band gap energy is approximately 1.12 eV, and it is difficult to set the operating temperature to 200 ° C. or higher. On the other hand, wide band gap semiconductors are easy to operate at high temperatures. For example, the band gap energy is as high as 2.2 to 3.02 eV for silicon carbide (SiC) and about 3.39 eV for gallium nitride (GaN). For this reason, when a wide band gap material is used, MOSFET and IGBT can be operated at, for example, 300 ° C. or more.

本実施形態にかかる半導体装置では、例えば２５０℃近傍で、半導体素子と実装部材とを接合し、実装部材の反りや半導体素子のクラックなどが抑制できる。また、接合温度よりも高い温度で動作させても、拡散接合された固溶体相は変化しないので接合強度を高く保つことができる。   In the semiconductor device according to the present embodiment, for example, the semiconductor element and the mounting member are joined at about 250 ° C., and thus warpage of the mounting member, cracks in the semiconductor element, and the like can be suppressed. Further, even if the operation is performed at a temperature higher than the bonding temperature, the diffusion bonded solid solution phase does not change, so that the bonding strength can be kept high.

いくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。   Although several embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

２０ 半導体素子、２１ 接合電極付き半導体素子、３１ 基板、３２ 第１の絶縁材、３３ 導電部、３４ 第３の絶縁材、３６ 枠部、４０ 実装部材、４１ 保護金属層、４５ 第１接合金属層、４６ 第３接合金属層、４７ 保護金属層、４８ 第２接合金属層、４９ 固溶体層、５０ 接合金属層、６０ 導電パターン基板、６１ 接合金属層付き導電パターン基板、６２ 第２の絶縁材、６４ 第４接合金属層、６５ 保護金属層、６６ 導電パターン 20 Semiconductor element, 21 Semiconductor element with bonding electrode, 31 Substrate, 32 First insulating material, 33 Conductive portion, 34 Third insulating material, 36 Frame portion, 40 Mounting member, 41 Protective metal layer, 45 First bonding metal 46, third bonding metal layer, 47 protective metal layer, 48 second bonding metal layer, 49 solid solution layer, 50 bonding metal layer, 60 conductive pattern substrate, 61 conductive pattern substrate with bonding metal layer, 62 second insulating material , 64 Fourth bonding metal layer, 65 Protective metal layer, 66 Conductive pattern

Claims (11)

第１の金属を含む面を有する基板と、前記基板の前記面の外周領域に設けられた第１の絶縁材と前記第１の絶縁材の上に設けられた導電部とを有する枠部と、を有する実装部材と、
前記基板の前記面の内部領域の上に設けられ、前記導電部と電気的に接続可能な半導体素子と、
銅および銅合金のいずれかである第２の金属と、前記第２の金属内に分散され、錫、亜鉛、およびインジウムのいずれかである第３の金属と、前記第２の金属内に分散され金および白金のうちのいずれかである第４の金属と、を有する接合金属層であって、前記第２の金属の重量百分率が前記第３の金属の重量百分率よりも高く、かつ前記第３の金属の重量百分率が前記第４の金属の重量百分率よりも高い固溶体層により、前記半導体素子と前記内部領域とを接合可能な接合金属層と、
を備えた半導体装置。 A frame having a substrate having a surface containing a first metal, a first insulating material provided in an outer peripheral region of the surface of the substrate, and a conductive portion provided on the first insulating material; A mounting member having,
A semiconductor element provided on an inner region of the surface of the substrate and electrically connectable to the conductive portion;
A second metal that is either copper or a copper alloy, dispersed in the second metal, a third metal that is any of tin, zinc, and indium, and dispersed in the second metal And a fourth metal that is either gold or platinum, wherein a weight percentage of the second metal is higher than a weight percentage of the third metal, and A bonding metal layer capable of bonding the semiconductor element and the internal region by a solid solution layer in which the weight percentage of the third metal is higher than the weight percentage of the fourth metal;
A semiconductor device comprising: 第２の絶縁材と、前記第２の絶縁材の上に設けられた導電パターンと、を有し、上方からみて前記枠部と前記半導体素子との間に設けられた導電パターン基板をさらに備え、
前記導電パターンが設けられない側の前記導電パターン基板の面と、前記内部領域と、が前記接合金属層により接合された請求項１記載の半導体装置。 A conductive pattern substrate provided between the frame portion and the semiconductor element as viewed from above, the second insulating material; and a conductive pattern provided on the second insulating material. ,
The semiconductor device according to claim 1, wherein a surface of the conductive pattern substrate on the side where the conductive pattern is not provided and the internal region are bonded by the bonding metal layer. 前記接合金属層は、前記第２の金属からなり前記内部領域と接合された第１接合金属層と、前記第２の金属からなり前記半導体素子と接合された第２接合金属層と、前記第１接合金属層と前記第２接合金属層との間に設けられた前記固溶体層と、を有する請求項１または２に記載の半導体装置。   The bonding metal layer includes a first bonding metal layer formed of the second metal and bonded to the internal region, a second bonding metal layer formed of the second metal and bonded to the semiconductor element, and the first metal layer. The semiconductor device according to claim 1, further comprising: the solid solution layer provided between the first bonding metal layer and the second bonding metal layer. 第１の金属を含む面を有する基板と、
前記基板の前記面の外周領域に設けられた第１の絶縁材と前記第１の絶縁材の上に設けられた導電部とを有する枠部と、
前記基板の前記面の内周領域の上に設けられ、銅および銅合金のいずれかである第２の金属からなる第１接合金属層と、
前記第１接合金属層の上に設けられ、金および白金のいずれかである第４の金属からなる保護金属層と、
を備えた実装部材。 A substrate having a surface comprising a first metal;
A frame portion having a first insulating material provided in an outer peripheral region of the surface of the substrate and a conductive portion provided on the first insulating material;
A first bonding metal layer provided on an inner peripheral region of the surface of the substrate and made of a second metal that is one of copper and a copper alloy;
A protective metal layer provided on the first bonding metal layer and made of a fourth metal that is either gold or platinum;
Mounting member. 前記保護金属層の上に設けられ、錫、亜鉛、およびインジウムのいずれかである第３の金属からなる第２接合金属層をさらに備えた請求項４記載の実装部材。   The mounting member according to claim 4, further comprising a second bonding metal layer that is provided on the protective metal layer and is made of a third metal that is one of tin, zinc, and indium. 前記枠部は、前記導電部の上および前記導電部の非形成領域となる前記第１の絶縁材の上に設けられた第３の絶縁材をさらに有する請求項４または５に記載の実装部材。   The mounting member according to claim 4, wherein the frame portion further includes a third insulating material provided on the conductive portion and on the first insulating material to be a non-formation region of the conductive portion. . 能動領域を有する第１の面および前記第１の面の反対の側の第２の面を有する半導体素子と、
前記第２の面に設けられ、銅および銅合金のいずれかである第２の金属からなる第３接合金属層と、
前記第３接合金属層の上に設けられ、金および白金のいずれかである第４の金属からなる保護金属層と、
を備えた接合金属層付き半導体素子。 A semiconductor element having a first surface having an active region and a second surface opposite the first surface;
A third bonding metal layer provided on the second surface and made of a second metal that is either copper or a copper alloy;
A protective metal layer provided on the third bonding metal layer and made of a fourth metal that is either gold or platinum;
A semiconductor element with a bonding metal layer. 請求項４記載の実装部材の前記保護金属層と、請求項７記載の接合金属層付き半導体素子の前記保護金属層と、の間に、前記第３の金属からなるシートを配置する工程と、
加熱により前記シートを液相状態とする工程と、
前記半導体素子と前記実装部材とに所定の圧力を加えつつ所定の温度に所定の時間保つことにより、前記第３の金属が前記第１の接合金属層内および前記第３の接合金属層内にそれぞれ拡散された固溶体層を形成し前記半導体素子と前記内部領域とを接合する工程と、
を備えた半導体装置の製造方法。 A step of disposing a sheet made of the third metal between the protective metal layer of the mounting member according to claim 4 and the protective metal layer of the semiconductor element with a bonding metal layer according to claim 7;
Bringing the sheet into a liquid phase by heating;
By maintaining a predetermined temperature at a predetermined temperature while applying a predetermined pressure to the semiconductor element and the mounting member, the third metal is placed in the first bonding metal layer and the third bonding metal layer. Forming each diffused solid solution layer and bonding the semiconductor element and the internal region;
A method for manufacturing a semiconductor device comprising: 前記接合する工程は、前記実装部材の前記第４の金属および前記接合金属層付き半導体素子の前記第４の金属を前記固溶体層内に拡散する請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the bonding step diffuses the fourth metal of the mounting member and the fourth metal of the semiconductor element with the bonding metal layer into the solid solution layer. 請求項５記載の実装部材の前記第２接合金属層と、請求項７記載の接合金属層付き半導体素子の前記保護金属層と、を重ね合わせる工程と、
前記第３の金属を融点以上に加熱し液相状態とする工程と、
前記半導体素子と前記実装部材とに所定の圧力を加えたつつ所定の温度で所定の時間保つことにより、前記第３の金属を前記実装部材の前記第２の金属内および前記半導体素子の前記第２の金属内に拡散された固溶体層を形成し前記半導体素子と前記内部領域とを接合する工程と、
を有する半導体装置の製造方法。 Overlaying the second bonding metal layer of the mounting member according to claim 5 and the protective metal layer of the semiconductor element with the bonding metal layer according to claim 7;
Heating the third metal to a melting point or higher to form a liquid phase;
By maintaining a predetermined temperature at a predetermined temperature while applying a predetermined pressure to the semiconductor element and the mounting member, the third metal is placed in the second metal of the mounting member and the first metal of the semiconductor element. Forming a solid solution layer diffused in the metal of 2 and joining the semiconductor element and the internal region;
A method for manufacturing a semiconductor device comprising: 前記接合する工程は、前記実装部材の前記第４の金属および前記接合金属層付き半導体素子の前記第４の金属を前記固溶体層内に拡散する請求項１０記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 10, wherein in the bonding step, the fourth metal of the mounting member and the fourth metal of the semiconductor element with the bonding metal layer are diffused into the solid solution layer.
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* Cited by examiner, † Cited by third party
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US9013034B2 (en) 2013-04-15 2015-04-21 Kabushiki Kaisha Toshiba Semiconductor package
US9041190B2 (en) 2013-04-15 2015-05-26 Kabushiki Kaisha Toshiba Semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9013034B2 (en) 2013-04-15 2015-04-21 Kabushiki Kaisha Toshiba Semiconductor package
US9041190B2 (en) 2013-04-15 2015-05-26 Kabushiki Kaisha Toshiba Semiconductor package

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