JP6399906B2 - Power module - Google Patents

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JP6399906B2
JP6399906B2 JP2014235218A JP2014235218A JP6399906B2 JP 6399906 B2 JP6399906 B2 JP 6399906B2 JP 2014235218 A JP2014235218 A JP 2014235218A JP 2014235218 A JP2014235218 A JP 2014235218A JP 6399906 B2 JP6399906 B2 JP 6399906B2
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semiconductor element
bonding
layer
sinterable metal
bonding material
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JP2016100424A (en
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佑哉 村松
佑哉 村松
隆行 山田
隆行 山田
範之 別芝
範之 別芝
中島　泰
泰 中島
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Powder Metallurgy (AREA)
  • Die Bonding (AREA)

Description

この発明は、金属微粒子を含む接合材料を用いて半導体素子を実装するパワーモジュールに関する。   The present invention relates to a power module for mounting a semiconductor element using a bonding material containing metal fine particles.

パワーモジュールなどの電力用半導体装置には、スイッチング素子や整流素子としてＩＧＢＴ（Insulated Gate Bipolar Transistor）やダイオードなどの半導体素子が搭載されている。これらの縦型半導体素子は、裏面全域にメタライズを施した裏面電極と、それに対向する面（表面）の一部分にメタライズを施した表面電極とが設けられている。そして、大電流を流すための配線構造として、裏面電極は基板電極に接続するとともに、表面の電極は配線金属板を介して外部端子と接続する。   Power semiconductor devices such as power modules are equipped with semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and diodes as switching elements and rectifier elements. These vertical semiconductor elements are provided with a back surface electrode that has been metallized over the entire back surface and a surface electrode that has been metallized on a portion of the surface (surface) facing it. As a wiring structure for flowing a large current, the back electrode is connected to the substrate electrode, and the front electrode is connected to the external terminal through the wiring metal plate.

一方、電力損失低減の観点から、近年、例えば、炭化ケイ素（ＳｉＣ）、窒化ガリウムのようなワイドバンドギャップ半導体材料を用いた半導体素子が開発されている。半導体素子が、こうしたワイドギャップ半導体の場合、素子自身の耐熱性が高く、大電流による高温動作が可能であるが、その特性を発揮するためには、上述した配線構造を形成するために、高耐熱性能の接合材料が必要とされる。しかし、鉛フリーでかつ高耐熱性能を有するはんだ材は現状見出されていない。そこで、はんだに代わり、金属微粒子の焼結現象を利用した焼結性金属接合材料を用いたパワーモジュールが検討されている（例えば、特許文献１または２参照）。焼結性金属接合材料は金属微粒子、有機溶剤成分および金属微粒子を覆う保護膜から構成されるペースト状の接合材である。焼結性金属接合材料は金属微粒子がその金属の融点よりも低い温度で焼結する現象を利用して、被接合部材との金属結合を達成するものである。接合後の状態は金属微粒子間が拡散接合され、また素子のメタライズ及び素子を搭載する基板の表面との間も拡散接合がなされ、接合後の融点は金属としての本来の融点にまで高まるものである。そのため、接合時の温度よりも高い耐熱性能を有することができる。また、焼結製金属材料として一般的によく知られている金（Ａｕ）、銀（Ａｇ）および銅（Ｃｕ）ははんだに比べて熱伝導率が大きく、さらに接合層を薄くすることができるため高い放熱性能も有する。パワーモジュールは、高電圧・大電流での利用に好適であり、産業機器から家電や情報端末まであらゆる製品に普及しつつある。近年、家電に搭載されるモジュールについては、小型軽量化とともに多品種に対応できる高い生産性と高い信頼性が求められる。また、動作温度が高く、効率に優れている点で、今後の主流となる可能性の高いＳｉＣ半導体に適用できるパッケージ形態であることも同時に求められている。   On the other hand, from the viewpoint of reducing power loss, in recent years, semiconductor devices using wide band gap semiconductor materials such as silicon carbide (SiC) and gallium nitride have been developed. When the semiconductor element is such a wide gap semiconductor, the element itself has high heat resistance and can be operated at a high temperature due to a large current. However, in order to exhibit its characteristics, a high- A bonding material with heat resistance is required. However, no solder material having lead-free and high heat resistance has been found at present. Therefore, a power module using a sinterable metal bonding material using a sintering phenomenon of metal fine particles instead of solder has been studied (for example, see Patent Document 1 or 2). The sinterable metal bonding material is a paste-like bonding material composed of a metal fine particle, an organic solvent component, and a protective film covering the metal fine particle. The sinterable metal bonding material achieves metal bonding with a member to be bonded by utilizing a phenomenon that metal fine particles are sintered at a temperature lower than the melting point of the metal. The state after bonding is diffusion bonding between metal fine particles, and diffusion bonding is also performed between the metallization of the element and the surface of the substrate on which the element is mounted, and the melting point after bonding increases to the original melting point as a metal. is there. Therefore, it can have heat resistance higher than the temperature at the time of joining. In addition, gold (Au), silver (Ag), and copper (Cu), which are generally well-known as sintered metal materials, have higher thermal conductivity than solder, and can further reduce the thickness of the bonding layer. Therefore, it also has high heat dissipation performance. Power modules are suitable for use at high voltages and large currents, and are becoming widespread in various products from industrial equipment to home appliances and information terminals. In recent years, modules mounted on home appliances are required to have high productivity and high reliability that can be used in various types as well as being reduced in size and weight. In addition, it is also required to have a package form that can be applied to SiC semiconductors that are likely to become mainstream in the future because of high operating temperature and excellent efficiency.

特開２００８−２１２９７６号公報（段落００２４〜００４２）JP 2008-212976 (paragraphs 0024 to 0042) 特開２００７−４４７５４号公報（段落００１４、図２）JP 2007-44754 (paragraph 0014, FIG. 2)

このように、焼結現象を利用した焼結性金属接合材料は、高耐熱性能が要求されるパワーモジュールに好適な性質を有するものである。焼結反応は焼結性金属接合材料の金属微粒子は粒径が小さいほど進行しやすいため、金属粒子径を小さくすることで焼結性金属接合材料と被接合材の接合強度が大きくなり信頼性を向上させることができる。しかし、金属粒子の粒径が小さくなるにつれて保護膜の割合が増えていくため接合時、揮発した保護膜による基板汚染が問題となる。また、大面積の半導体素子での接合においては揮発する保護膜の量が多いため、抜けきらなかった保護膜が接合を阻害する恐れもある。   Thus, the sinterable metal bonding material using the sintering phenomenon has properties suitable for power modules that require high heat resistance. Sintering reaction proceeds more easily as the particle size of the sinterable metal bonding material is smaller. Therefore, reducing the metal particle size increases the bonding strength between the sinterable metal bonding material and the material to be bonded. Can be improved. However, since the proportion of the protective film increases as the particle size of the metal particles decreases, substrate contamination due to the volatilized protective film becomes a problem during bonding. In addition, since the amount of the protective film that volatilizes is large in bonding with a large-area semiconductor element, there is a possibility that the protective film that cannot be completely removed may hinder the bonding.

一方で金属粒子径を大きくした場合、粒子同士の隙間が大きくなるため上記汚染の影響は小さくなるものの焼結反応は進みにくくなり、良好な接合部を得るために必要な加圧力の増加、接合時間の増加が発生する。さらには半導体素子よりも外周に配置された未加圧部の加圧不足による導体層からの剥離が発生し、導電性異物の発生を引き起こす。   On the other hand, when the metal particle diameter is increased, the gap between the particles is increased, so the influence of the contamination is reduced, but the sintering reaction is difficult to proceed, and an increase in the pressurizing force necessary for obtaining a good joint is achieved. An increase in time occurs. Further, peeling from the conductor layer due to insufficient pressurization of the non-pressurized portion arranged on the outer periphery than the semiconductor element occurs, causing generation of conductive foreign matter.

この発明は、上記のような課題を解決するためになされたものであり、半導体素子と基板との間の焼結性金属接合材料接合を用いた接合において、剥離を防ぎ、信頼性の高いパワーモジュールを提供することを目的とする。   The present invention has been made in order to solve the above-described problems. In the bonding using the sinterable metal bonding material bonding between the semiconductor element and the substrate, the peeling is prevented and the power is highly reliable. The purpose is to provide modules.

この発明のパワーモジュールは、表面に導体層が設けられた絶縁基板と、裏面に電極が設けられた矩形の半導体素子と、焼結性金属接合材料を用いて前記絶縁基板の導体層と前記半導体素子の電極とを接合した接合層とを備えたパワーモジュールであって、前記接合層は、前記半導体素子の端部から内側に前記半導体素子の大きさの１／１０の位置よりさらに内側の領域となる前記半導体素子の中央部に形成された第１の接合層と、前記半導体素子の端部から内側に前記半導体素子の大きさの１／１０の位置より外側で端部を含む額縁形状の領域に形成された第２の接合層と、を含み、前記第２の接合層は前記第１の接合層で用いられた焼結性金属接合材料より粒子径の小さい焼結性金属接合材料を用いて形成されたことを特徴とする。 The power module of the present invention includes an insulating substrate having a conductor layer provided on the front surface, a rectangular semiconductor element having an electrode provided on the back surface, and a conductive layer of the insulating substrate and the semiconductor using a sinterable metal bonding material. A power module comprising a bonding layer bonded to an electrode of an element, wherein the bonding layer is a region further inside than a position of 1/10 of the size of the semiconductor element inward from an end of the semiconductor element A first bonding layer formed at a central portion of the semiconductor element, and a frame shape including an end portion outside the position of 1/10 of the size of the semiconductor element on the inner side from the end portion of the semiconductor element. A second bonding layer formed in the region, wherein the second bonding layer is made of a sinterable metal bonding material having a particle diameter smaller than that of the sinterable metal bonding material used in the first bonding layer. It was formed using .

また、この発明のパワーモジュールは、表面に導体層が設けられた絶縁基板と、裏面に電極が設けられた半導体素子と、焼結性金属接合材料を用いて前記絶縁基板の導体層と前記半導体素子の電極とを接合した接合層とを備えたパワーモジュールであって、前記接合層は、二層構造であって、少なくとも前記半導体素子側の層または前記絶縁基板側の層のいずれか一方に他方より粒子径の小さい前記焼結性金属接合材料を用いたことを特徴とする。 The power module of the present invention includes an insulating substrate having a conductor layer provided on the front surface, a semiconductor element having an electrode provided on the back surface, and a conductive layer of the insulating substrate and the semiconductor using a sinterable metal bonding material. a power module that includes a bonding layer bonding the element electrode, the bonding layer is a two-layer structure, either one of at least the semiconductor element side of the layer or the insulating substrate side of the layer The sinterable metal bonding material having a smaller particle diameter than the other is used.

この発明によれば、異なる粒子径の焼結性金属接合材料を用いて絶縁基板の導体層と半導体素子の電極とを接合することにより、必要に応じて接触面積を増やすことで、接合強度を向上させ、剥離を防ぐことができる。   According to the present invention, by joining the conductor layer of the insulating substrate and the electrode of the semiconductor element using the sinterable metal bonding materials having different particle sizes, the bonding area can be increased as necessary, thereby increasing the bonding strength. It is possible to improve and prevent peeling.

この発明の実施の形態１によるパワーモジュールの構成を示す模式図である。It is a schematic diagram which shows the structure of the power module by Embodiment 1 of this invention. この発明の実施の形態１によるパワーモジュールの製造工程を示すフローチャート図である。It is a flowchart figure which shows the manufacturing process of the power module by Embodiment 1 of this invention. この発明の実施の形態１によるパワーモジュールの製造工程における拡大断面図である。It is an expanded sectional view in the manufacturing process of the power module by Embodiment 1 of this invention. この発明の実施の形態２によるパワーモジュールの構成を示す模式図である。It is a schematic diagram which shows the structure of the power module by Embodiment 2 of this invention. この発明の実施の形態２によるパワーモジュールの製造工程を示すフローチャート図である。It is a flowchart figure which shows the manufacturing process of the power module by Embodiment 2 of this invention. この発明の実施の形態２によるパワーモジュールの製造工程における拡大断面図である。It is an expanded sectional view in the manufacturing process of the power module by Embodiment 2 of this invention. この発明の実施の形態３によるパワーモジュールの構成を示す模式図である。It is a schematic diagram which shows the structure of the power module by Embodiment 3 of this invention. この発明の実施の形態３によるパワーモジュールの製造工程における拡大断面図である。It is an expanded sectional view in the manufacturing process of the power module by Embodiment 3 of this invention. この発明の実施の形態３によるパワーモジュールの他の構成を示す模式図である。It is a schematic diagram which shows the other structure of the power module by Embodiment 3 of this invention. この発明の実施の形態３によるパワーモジュールの他の製造工程を示すフローチャート図である。It is a flowchart figure which shows the other manufacturing process of the power module by Embodiment 3 of this invention. この発明の実施の形態３によるパワーモジュールの他の製造工程における拡大断面図である。It is an expanded sectional view in the other manufacturing process of the power module by Embodiment 3 of this invention.

実施の形態１．
図１は、この発明の実施の形態１によるパワーモジュール１００の要部を示す模式図である。図１（ａ）は、上面図であり、図１（ｂ）は、図１（ａ）のＡ−Ａ’線での矢視断面図である。
図１に示すように、パワーモジュール１００は、セラミック絶縁基板１と、セラミック絶縁基板１の両面に設けられた導体層２と、セラミック絶縁基板１の表面側の導体層２上に配置される半導体素子５と、セラミック絶縁基板１の表面側の導体層２と半導体素子５の裏面電極５ａとを接合する接合層７とから構成される。 Embodiment 1 FIG.
FIG. 1 is a schematic diagram showing a main part of a power module 100 according to Embodiment 1 of the present invention. FIG. 1A is a top view, and FIG. 1B is a cross-sectional view taken along line AA ′ in FIG.
As shown in FIG. 1, a power module 100 includes a ceramic insulating substrate 1, a conductor layer 2 provided on both surfaces of the ceramic insulating substrate 1, and a semiconductor disposed on the conductor layer 2 on the surface side of the ceramic insulating substrate 1. It is comprised from the element 5, and the joining layer 7 which joins the conductor layer 2 of the surface side of the ceramic insulated substrate 1, and the back surface electrode 5a of the semiconductor element 5. FIG.

セラミック絶縁基板１は、例えばＡｌ２Ｏ３、Ｓｉ３Ｎ４、ＡｌＮなどの絶縁性のセラミックで形成され、セラミック絶縁基板１の両面には導体層２が積層固着されている。
導体層２は、ＣｕやＡｌなどの金属が用いられ、金属層単独の場合もあり得るし、Ａｕなどの貴金属材料で被覆することもある。 The ceramic insulating substrate 1 is formed of an insulating ceramic such as Al 2 O 3 , Si 3 N 4 , or AlN, and the conductor layer 2 is laminated and fixed on both surfaces of the ceramic insulating substrate 1.
The conductor layer 2 is made of a metal such as Cu or Al, and may be a single metal layer or may be coated with a noble metal material such as Au.

半導体素子５は、材質が珪素（Ｓｉ）やワイドバンドギャップ半導体材料としての炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドなどのものが用いられ、大きさは例えば一辺５ｍｍ〜２０ｍｍ程度の長方形のものが用いられる。半導体素子５ではパワーモジュールで扱う電力の数％が損失となり、半導体素子５自身が発熱し、パワーモジュールの負荷の変動や動作非動作に応じて温度が変化する。半導体素子５は、損失による熱を冷却器へと受け渡す必要があるため、半導体素子５の裏面の全面が導体層２上に面接合される。そして、導体層２と半導体素子５の線膨張係数は、例えば、Ｃｕの導体層２であれば１８ｐｐｍ／Ｋの線膨張係数であるのに対して、材質がＳｉの半導体素子５では３ｐｐｍ／Ｋと数倍以上の差があるため、接合層７には大きな熱応力が生じる。このため、この接合層７は極めて大きな熱応力に高温でさらされる。特に、熱応力は半導体素子５のコーナー部で最大となる。そこで、半導体素子５と導体層２とを接合する接合層７には、高耐熱性能の接合材料が必要とされ、金属微粒子の焼結現象を利用した焼結性金属接合材料が用いられる。   The semiconductor element 5 is made of silicon (Si), silicon carbide (SiC) as a wide band gap semiconductor material, gallium nitride (GaN), diamond, or the like, and has a rectangular shape with a side of about 5 mm to 20 mm, for example. Is used. In the semiconductor element 5, several% of the power handled by the power module is lost, the semiconductor element 5 itself generates heat, and the temperature changes in accordance with the load variation or non-operation of the power module. Since the semiconductor element 5 needs to transfer heat due to loss to the cooler, the entire back surface of the semiconductor element 5 is surface-bonded to the conductor layer 2. The linear expansion coefficient of the conductor layer 2 and the semiconductor element 5 is, for example, 18 ppm / K in the case of the Cu conductor layer 2, but 3 ppm / K in the semiconductor element 5 made of Si. Therefore, a large thermal stress is generated in the bonding layer 7. For this reason, the bonding layer 7 is exposed to extremely large thermal stress at a high temperature. Particularly, the thermal stress becomes maximum at the corner portion of the semiconductor element 5. Therefore, the bonding layer 7 for bonding the semiconductor element 5 and the conductor layer 2 requires a bonding material with high heat resistance, and a sinterable metal bonding material using a sintering phenomenon of metal fine particles is used.

接合層７は、Ａｕや、Ａｇ、Ｃｕなどの骨材たる金属属微粒子が有機成分中に分散されてペースト状になった焼結性金属接合材料を用いて形成される。焼結性金属接合材料は、ナノメーターレベルの金属微粒子が非常に大きな表面積を有し、表面エネルギーを多く備えることから反応性が高くなっており、その金属がバルクで示す融点よりも低い温度で金属接合が拡散により進むという現象を利用したものである。ただし、金属微粒子は、その反応性の高さから、常温でも接触するだけで焼結すなわち拡散接合が進行する。そのため、焼結性金属接合材料では、金属微粒子が凝集して焼結反応が進行するのを抑制するため、金属微粒子の表面は保護膜で覆われている。保護膜は、金属微粒子間を独立した状態で分散保持するための有機分散材によって形成されている。さらに、接合工程において焼結反応を生じさせるため、加熱により有機分散材と反応して金属微粒子を裸にする分散材捕捉材と、有機分散材と分散材捕捉材との反応物質を捕捉して揮散する揮発性有機成分等が添加されている。   The bonding layer 7 is formed using a sinterable metal bonding material in which metal group fine particles such as Au, Ag, and Cu are dispersed in an organic component to form a paste. Sinterable metal bonding materials are highly reactive because nanometer level metal particles have a very large surface area and have a lot of surface energy, and the metal is at a temperature lower than the melting point of the bulk. This utilizes the phenomenon that metal bonding proceeds by diffusion. However, because of the high reactivity of the metal fine particles, sintering, that is, diffusion bonding proceeds only by contact at room temperature. Therefore, in the sinterable metal bonding material, the surface of the metal fine particles is covered with a protective film in order to suppress the aggregation of the metal fine particles and the progress of the sintering reaction. The protective film is formed of an organic dispersion material for dispersing and holding the metal fine particles in an independent state. Further, in order to cause a sintering reaction in the joining process, the dispersion trapping material that reacts with the organic dispersion material by heating to bare the metal fine particles, and the reactants of the organic dispersion material and the dispersion material trapping material are captured. Volatile organic components that volatilize are added.

図１（ｂ）に示すように、この実施の形態１におけるパワーモジュール１００では、半導体素子５は、セラミック絶縁基板１の導体層２と接合層７により接合されているが、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面を除く導体層２および裏面電極５ａの全接合面が第１の焼結性金属接合材料である焼結性金属接合材料４を用いた接合層７により接合されており、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面は焼結性金属接合材料４よりも粒子径が小さい第２の焼結性金属接合材料である焼結性金属接合材料６を用いた接合層７により接合されている。焼結性金属接合材料の粒子径は、焼結性金属接合材料４の粒子径がサブミクロン以上で、焼結性金属接合材料６の粒子径が１００ｎｍ未満であることが好ましい。ただし、パワーモジュールの構造および焼成条件によって適切な粒径範囲は異なり、この発明の作用を発揮できるものであれば、上述の粒子径の範囲でなくともよいことは言うまでもないことである。   As shown in FIG. 1B, in the power module 100 according to the first embodiment, the semiconductor element 5 is joined by the conductor layer 2 and the joining layer 7 of the ceramic insulating substrate 1. The sinterable metal bonding material 4 in which all the bonding surfaces of the conductor layer 2 and the back electrode 5a excluding the bonding surface of the conductor layer 2 and the back electrode 5a at the position corresponding to the peripheral portion are the first sinterable metal bonding material. The bonding surface of the conductor layer 2 and the back surface electrode 5a at the position corresponding to the peripheral edge of the back surface of the semiconductor element 5 has a particle diameter smaller than that of the sinterable metal bonding material 4. 2 are joined by a joining layer 7 using a sinterable metal joining material 6 which is a sinterable metal joining material 2. The particle diameter of the sinterable metal bonding material is preferably such that the particle diameter of the sinterable metal bonding material 4 is not less than submicron and the particle diameter of the sinterable metal bonding material 6 is less than 100 nm. However, the appropriate particle size range varies depending on the structure of the power module and the firing conditions, and it goes without saying that the particle size range need not be as long as the function of the present invention can be exhibited.

この実施の形態１においては、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面と接合する接合層７に、焼結性金属接合材料６を使用し、金属微粒子径を小さくすることで、最も熱応力の大きい箇所の接合層と被接合面の接触面積を増やすことができるため、接合強度を向上させることができる。また、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面を除く全接合面と接合する接合層７に、焼結性金属接合材料４を使用し、金属微粒子径を大きくすることで、焼結性金属接合材料６のみの場合に比べて、金属粒子の周りの保護膜の総量が少なく、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。さらに、半導体素子５裏面より外側で、加圧が困難な位置にある導体層２の接合面と接合する接合層７の端部においても、焼結性金属接合材料６を使用し、金属微粒子径を小さくすることで、導体層２との接触面積を増やすことができるため、剥離を防ぐことができる。   In the first embodiment, the sinterable metal bonding material 6 is used for the bonding layer 7 bonded to the bonding surface of the conductor layer 2 and the back electrode 5a at the position corresponding to the peripheral edge of the back surface of the semiconductor element 5; By reducing the metal fine particle diameter, it is possible to increase the contact area between the bonding layer where the thermal stress is greatest and the surface to be bonded, so that the bonding strength can be improved. Further, a sinterable metal bonding material 4 is used for the bonding layer 7 bonded to all the bonding surfaces except the bonding surface of the conductor layer 2 and the back electrode 5a at the position corresponding to the peripheral edge of the back surface of the semiconductor element 5, and a metal By increasing the particle size, the total amount of the protective film around the metal particles is smaller than in the case of the sinterable metal bonding material 6 alone. Inhibition can be prevented. Furthermore, the sinterable metal bonding material 6 is used at the end of the bonding layer 7 that is bonded to the bonding surface of the conductor layer 2 at a position where pressurization is difficult outside the back surface of the semiconductor element 5. Since the contact area with the conductor layer 2 can be increased by reducing the thickness, peeling can be prevented.

次に、この発明の実施の形態１によるパワーモジュール１００の製造方法について、図２に基づき説明する。図２は、この発明の実施の形態１によるパワーモジュール１００の製造工程を示すフローチャート図である。   Next, a method for manufacturing the power module 100 according to Embodiment 1 of the present invention will be described with reference to FIG. FIG. 2 is a flowchart showing a manufacturing process of the power module 100 according to the first embodiment of the present invention.

まず最初に、セラミック絶縁基板１の表面側の導体層２上に、焼結性金属接合材料４を印刷により塗布する。（ステップＳ３１）。半導体素子５の裏面の形状が、１０ｍｍ×１０ｍｍの正方形である場合には、半導体素子５裏面直下の周縁部以外に対応する位置、例えば半導体素子５裏面の４辺の各端部から１ｍｍ幅の部分を除く、８ｍｍ×８ｍｍの正方形状に、３０〜２００μｍ厚で焼結性金属接合材料４を塗布する。 First, the sinterable metal bonding material 4 is applied on the conductor layer 2 on the surface side of the ceramic insulating substrate 1 by printing. (Step S31). When the shape of the back surface of the semiconductor element 5 is a square of 10 mm × 10 mm, a position corresponding to other than the peripheral portion immediately below the back surface of the semiconductor element 5, for example, 1 mm width from each end of four sides of the back surface of the semiconductor element 5. The sinterable metal bonding material 4 is applied in a thickness of 30 to 200 μm in a square shape of 8 mm × 8 mm excluding the portion.

次いで、セラミック絶縁基板１の表面側の導体層２上に、焼結性金属接合材料４よりも粒子径が小さい焼結性金属接合材料６を印刷により塗布する。（ステップＳ３２）。正方形に印刷されている焼結性金属接合材料４の外周で半導体素子５裏面の周縁部に対応する位置、例えば、外形１１ｍｍ×１１ｍｍ、内形８ｍｍ×８ｍｍの額縁形状に、３０〜２００μｍ厚で、焼結性金属接合材料６を塗布する。   Next, a sinterable metal bonding material 6 having a particle diameter smaller than that of the sinterable metal bonding material 4 is applied onto the conductor layer 2 on the surface side of the ceramic insulating substrate 1 by printing. (Step S32). A position corresponding to the periphery of the back surface of the semiconductor element 5 on the outer periphery of the sinterable metal bonding material 4 printed in a square shape, for example, a frame shape of an outer shape 11 mm × 11 mm and an inner shape 8 mm × 8 mm, with a thickness of 30 to 200 μm. The sinterable metal bonding material 6 is applied.

続いて、導体層２に塗布された焼結性金属接合材料４および焼結性金属接合材料６を乾燥（ステップＳ３３）する。最後に、額縁形状に塗布された焼結性金属接合材料６上に、半導体素子５裏面の裏面電極５ａの４辺が位置するように半導体素子５を載せ、半導体素子５を押下して焼結性金属接合材料４および焼結性金属接合材料６を加圧しながら加熱（ステップＳ３４）することで、焼結性金属接合材料４および焼結性金属接合材料６は、導体層２および裏面電極５ａの接合面および金属微粒子同士と焼結接合し、接合層７が形成される。   Subsequently, the sinterable metal bonding material 4 and the sinterable metal bonding material 6 applied to the conductor layer 2 are dried (step S33). Finally, the semiconductor element 5 is placed on the sinterable metal bonding material 6 applied in a frame shape so that the four sides of the back surface electrode 5a on the back surface of the semiconductor element 5 are positioned, and the semiconductor element 5 is pressed and sintered. By heating the sinterable metal bonding material 4 and the sinterable metal bonding material 6 while applying pressure (step S34), the sinterable metal bonding material 4 and the sinterable metal bonding material 6 become the conductor layer 2 and the back electrode 5a. The bonding surface 7 and the metal fine particles are sintered and bonded together to form the bonding layer 7.

図３は、図１（ｂ）の領域Ｂ、つまり半導体素子５裏面の周縁部の拡大断面図である。図３（ａ）は、焼結性金属接合材料を乾燥（ステップＳ３３）した後に半導体素子５を載せた、焼結する前の状態を示し、図３（ｂ）は、焼結性金属接合材料を加圧しながら加熱（ステップＳ３４）し、焼結した後の状態を示す。焼結前においては、図３（ａ）に示すように、半導体素子５裏面直下の焼結性金属接合材料４では金属微粒子径が大きく、金属微粒子間に空隙が大きく存在する。この空隙が金属微粒子を覆う保護膜の有機成分の抜け道となり、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。焼結後は、図３（ｂ）に示すように、半導体素子５裏面直下では加圧によって空隙は減少し、金属粒子間の焼結接合が強固となる。半導体素子５裏面直下の周縁部においては、加圧によって空隙が減少するとともに、粒子径が小さい焼結性金属接合材料６により、最も熱応力の大きい箇所の接合層と導体層２および裏面電極５ａの接合面との接触面積を増やすことで、接合強度を向上させることができる。さらに、接合層７の端部は、半導体素子５裏面より外側で、加圧できない領域にあるが、金属微粒子径の小さい焼結性金属接合材料６を用いることで、被接合面である導体層２との接触面積が増え、剥離を防ぐことができる。   FIG. 3 is an enlarged cross-sectional view of the region B of FIG. 1B, that is, the peripheral edge of the back surface of the semiconductor element 5. FIG. 3A shows a state before the semiconductor element 5 is placed after the sinterable metal bonding material is dried (step S33), and FIG. 3B shows the sinterable metal bonding material. The state after heating (step S34) and pressurizing and sintering is shown. Before the sintering, as shown in FIG. 3A, the sinterable metal bonding material 4 directly under the back surface of the semiconductor element 5 has a large metal fine particle diameter and a large gap exists between the metal fine particles. This void serves as an escape route for the organic component of the protective film covering the metal fine particles, and it is possible to prevent substrate contamination due to the volatilized protective film and bonding inhibition due to the protective film that cannot be completely removed. After the sintering, as shown in FIG. 3B, the voids are reduced by pressurization just below the back surface of the semiconductor element 5, and the sintered joint between the metal particles becomes strong. In the peripheral portion immediately below the back surface of the semiconductor element 5, voids are reduced by pressurization, and the bonding layer, conductor layer 2, and back electrode 5 a of the portion having the largest thermal stress are formed by the sinterable metal bonding material 6 having a small particle diameter. By increasing the contact area with the bonding surface, the bonding strength can be improved. Further, the end portion of the bonding layer 7 is outside the back surface of the semiconductor element 5 and is in a region where pressure cannot be applied. By using a sinterable metal bonding material 6 having a small metal particle diameter, a conductor layer that is a bonded surface is used. The contact area with 2 increases, and peeling can be prevented.

接合層７の形成により、セラミック絶縁基板１上への半導体素子５の接合が完了する。焼結接合では、接合温度、加圧、接合時間が接合力を決定する主なパラメータとなる。Ａｕ、ＡｇおよびＣｕの金属微粒子からなる焼結性金属接合材料の焼結接合においては、焼成条件は、温度：２５０〜３５０℃、加圧：０.１〜３０ＭＰａ、接合時間：１〜６０ｍｉｎであることが好ましい。   Formation of the bonding layer 7 completes bonding of the semiconductor element 5 onto the ceramic insulating substrate 1. In sintered joining, joining temperature, pressurization, and joining time are the main parameters that determine the joining force. In the sinter bonding of a sinterable metal bonding material composed of fine metal particles of Au, Ag and Cu, the firing conditions are as follows: temperature: 250-350 ° C., pressure: 0.1-30 MPa, bonding time: 1-60 min. Preferably there is.

以上のように、この発明の実施の形態１におけるパワーモジュール１００では、セラミック絶縁基板１の表面側の導体層２と半導体素子５とを接合する接合層７は、接合条件としての接合面の位置に基づいて焼結性金属接合材料４および焼結性金属接合材料４よりも粒子径が小さい焼結性金属接合材料６と粒径の異なる焼結性金属接合材料を用い、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面との接合に、金属微粒子径の小さい焼結性金属接合材料６を用いたことにより、最も熱応力の大きい箇所の接合層と導体層２および裏面電極５ａの接合面の接触面積を増やすことで、接合強度を向上させることができる。
また、半導体素子５裏面の周縁部に対応する位置での導体層２および裏面電極５ａの接合面を除く導体層２および裏面電極５ａの全接合面との接合に、金属微粒子径の大きい焼結性金属接合材料４を用いたことにより、金属微粒子径の小さい焼結性金属接合材料のみの場合に比べて、金属粒子の周りの保護膜の総量が少ないだけでなく、焼結前には金属微粒子間に有機成分の抜け道となる空隙を確保でき、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。
さらに、半導体素子５裏面より外側で、加圧が困難な領域の接合層７の端部おいても、金属微粒子径の小さい焼結性金属接合材料６を用いたことにより、導体層との接触面積を増やすことができ、剥離を防ぐことができる。 As described above, in the power module 100 according to the first embodiment of the present invention, the bonding layer 7 for bonding the conductor layer 2 on the surface side of the ceramic insulating substrate 1 and the semiconductor element 5 has the position of the bonding surface as a bonding condition. The sinterable metal bonding material 4 and the sinterable metal bonding material 6 having a particle diameter smaller than that of the sinterable metal bonding material 4 and a sinterable metal bonding material having a different particle diameter are used. By using the sinterable metal bonding material 6 having a small metal particle diameter for bonding between the conductor layer 2 and the bonding surface of the back electrode 5a at a position corresponding to the peripheral edge, the bonding layer at the location where the thermal stress is greatest The bonding strength can be improved by increasing the contact area of the bonding surface between the conductor layer 2 and the back electrode 5a.
Further, sintering with a large metal fine particle diameter is performed for bonding to all the bonding surfaces of the conductor layer 2 and the back electrode 5a except for the bonding surface of the conductor layer 2 and the back electrode 5a at a position corresponding to the peripheral edge of the back surface of the semiconductor element 5. The use of the conductive metal bonding material 4 not only reduces the total amount of the protective film around the metal particles but also the metal before sintering compared to the case of only the sinterable metal bonding material having a small metal particle diameter. It is possible to secure voids that serve as escape paths for organic components between the fine particles, and to prevent substrate contamination due to the volatilized protective film and bonding inhibition due to the protective film that cannot be completely removed.
Furthermore, the contact with the conductor layer can be achieved by using the sinterable metal bonding material 6 having a small metal fine particle diameter at the end of the bonding layer 7 in the region where pressurization is difficult outside the back surface of the semiconductor element 5. The area can be increased and peeling can be prevented.

実施の形態２．
実施の形態１では、半導体素子５裏面の周縁部に対応する位置での接合層７は、半導体素子５裏面とセラミック絶縁基板１の表面側の導体層２との両方に金属微粒子径の小さい焼結性金属接合材料６が接合する構成としたが、実施の形態２では、半導体素子５の裏面電極の全接合面に金属微粒子径の大きい焼結性金属接合材料４が接合する場合について示す。 Embodiment 2. FIG.
In the first embodiment, the bonding layer 7 at the position corresponding to the peripheral edge of the back surface of the semiconductor element 5 is formed on both the back surface of the semiconductor element 5 and the conductor layer 2 on the surface side of the ceramic insulating substrate 1. In the second embodiment, the case is described in which the sinterable metal bonding material 4 having a large metal fine particle diameter is bonded to the entire bonding surface of the back electrode of the semiconductor element 5.

図４は、この発明の実施の形態２によるパワーモジュール２００の要部を示す模式図である。図４（ａ）は、上面図であり、図４（ｂ）は、図４（ａ）のＡ−Ａ’線での矢視断面図である。
図４（ｂ）に示すように、この実施の形態２におけるパワーモジュール２００では、接合層７は、半導体素子５裏面には、裏面電極５ａの全接合面に粒子径が大きい焼結性金属接合材料６で接合し、セラミック絶縁基板１の表面側の導体層２には、半導体素子５裏面の周縁部に対応する位置の接合面とは粒子径が小さい焼結性金属接合材料４で、半導体素子５裏面の周縁部に対応する位置以外の接合面とは粒子径が大きい焼結性金属接合材料６で接合している。
パワーモジュール２００のその他の構成については、実施の形態１のパワーモジュール１００と同様であり、その説明を省略する。 FIG. 4 is a schematic diagram showing a main part of a power module 200 according to Embodiment 2 of the present invention. 4A is a top view, and FIG. 4B is a cross-sectional view taken along the line AA ′ in FIG. 4A.
As shown in FIG. 4B, in the power module 200 according to the second embodiment, the bonding layer 7 is formed on the back surface of the semiconductor element 5 with a sinterable metal bond having a large particle diameter on the entire bonding surface of the back electrode 5a. The conductive layer 2 is bonded with the material 6, and the conductive layer 2 on the front surface side of the ceramic insulating substrate 1 is made of the sinterable metal bonding material 4 having a small particle diameter with respect to the bonding surface at the position corresponding to the peripheral edge of the back surface of the semiconductor element 5. It joins with the joining surface other than the position corresponding to the peripheral part of the element 5 back surface by the sinterable metal joining material 6 with a large particle diameter.
The other configuration of the power module 200 is the same as that of the power module 100 of the first embodiment, and the description thereof is omitted.

次に、この発明の実施の形態２によるパワーモジュール２００の製造方法について、図５に基づき説明する。図５は、この発明の実施の形態２によるパワーモジュール２００の製造工程を示すフローチャート図である。   Next, a method for manufacturing the power module 200 according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 5 is a flowchart showing a manufacturing process of the power module 200 according to the second embodiment of the present invention.

まず最初に、セラミック絶縁基板１の表面側の導体層２上に、粒子径が小さい焼結性金属接合材料６を印刷により塗布する（ステップＳ５１）。半導体素子５の裏面の形状が、１０ｍｍ×１０ｍｍの正方形である場合には、半導体素子５裏面の周縁部に対応する位置、例えば、外形１１ｍｍ×１１ｍｍ、内形８ｍｍ×８ｍｍの額縁形状に、１０〜１００μｍ厚で焼結性金属接合材料６を塗布する。焼結性金属接合材料６を塗布した後、一度乾燥しておく（ステップＳ５２）。   First, the sinterable metal bonding material 6 having a small particle size is applied by printing on the conductor layer 2 on the surface side of the ceramic insulating substrate 1 (step S51). When the shape of the back surface of the semiconductor element 5 is a square of 10 mm × 10 mm, the position corresponding to the peripheral edge of the back surface of the semiconductor element 5, for example, the frame shape of the outer shape 11 mm × 11 mm and the inner shape 8 mm × 8 mm is 10 The sinterable metal bonding material 6 is applied with a thickness of ˜100 μm. After applying the sinterable metal bonding material 6, it is once dried (step S52).

次いで、セラミック絶縁基板１の表面側の導体層２上に、粒子径が大きい焼結性金属接合材料４を印刷により塗布する（ステップＳ５３）。ここでは、半導体素子５裏面の裏面電極５ａの全接合面と粒子径が大きい焼結性金属接合材料４が接合するように、まず額縁形状に印刷されている焼結性金属接合材料６の内側（８ｍｍ×８ｍｍ正方形状）を埋めるために、１０〜１００μｍ厚で焼結性金属接合材料４を塗布し、さらにその上に、中心を合わせて、１０．５ｍｍ×１０．５ｍｍの正方形状に、１０〜１００μｍ厚で焼結性金属接合材料４を塗布する。焼結性金属接合材料４を塗布した後、再度乾燥（ステップＳ５４）する。   Next, the sinterable metal bonding material 4 having a large particle diameter is applied on the conductor layer 2 on the surface side of the ceramic insulating substrate 1 by printing (step S53). Here, first, the inner side of the sinterable metal bonding material 6 printed in a frame shape so that the entire bonding surface of the back electrode 5a on the back surface of the semiconductor element 5 and the sinterable metal bonding material 4 having a large particle diameter are bonded. In order to fill (8 mm × 8 mm square shape), the sinterable metal bonding material 4 is applied with a thickness of 10 to 100 μm, and further, the center is aligned on the square shape of 10.5 mm × 10.5 mm. The sinterable metal bonding material 4 is applied with a thickness of 10 to 100 μm. After the sinterable metal bonding material 4 is applied, it is dried again (step S54).

最後に、正方形状に塗布された焼結性金属接合材料４上に、半導体素子５裏面の裏面電極５ａが位置するように半導体素子５を載せ、半導体素子５を押下して焼結性金属接合材料４および焼結性金属接合材料６を加圧しながら加熱（ステップＳ５５）することで、焼結性金属接合材料４および焼結性金属接合材料６は、被接合面および金属微粒子同士と焼結接合し、接合層７が形成される。   Finally, the semiconductor element 5 is placed on the sinterable metal bonding material 4 applied in a square shape so that the back electrode 5a on the back surface of the semiconductor element 5 is positioned, and the semiconductor element 5 is pressed to sinter metal bonding. By heating the material 4 and the sinterable metal bonding material 6 while applying pressure (step S55), the sinterable metal bonding material 4 and the sinterable metal bonding material 6 are sintered together with the surface to be bonded and the metal fine particles. The bonding layer 7 is formed by bonding.

図６は、図４（ｂ）の領域Ｂ、つまり半導体素子５裏面の周縁部の拡大断面図である。図６（ａ）は、焼結性金属接合材料４を塗布して乾燥（ステップＳ５４）した後に半導体素子５を載せた、焼結する前の状態を示し、図６（ｂ）は、焼結性金属接合材料を加圧しながら加熱（ステップＳ５５）し、焼結した後の状態を示す。焼結前においては、図６（ａ）に示すように、半導体素子５裏面の裏面電極５ａの全接合面に、金属微粒子径が大きい焼結性金属接合材料４が配置され、金属微粒子間に空隙が大きく存在する。実施の形態２では、この空隙を半導体素子５裏面の全面に形成することで、半導体素子５裏面の中央部から端部に至るまで、金属微粒子を覆う保護膜の有機成分の抜け道を確保でき、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。焼結後は、図６（ｂ）に示すように、半導体素子５裏面直下では加圧によって空隙は減少し、金属粒子間の焼結接合が強固となる。また、接合層７の端部は、半導体素子５裏面より外側で、加圧できない領域にあるが、金属微粒子径の小さい焼結性金属接合材料６を用いることで、導体層２の接合面との接触面積が増え、剥離を防ぐことができる。さらに、金属微粒子径の小さい焼結性金属接合材料６の使用量を抑えることで、コストを低減できる。   FIG. 6 is an enlarged cross-sectional view of a region B in FIG. 4B, that is, a peripheral edge portion of the back surface of the semiconductor element 5. FIG. 6A shows a state before the semiconductor element 5 is mounted after the sinterable metal bonding material 4 is applied and dried (step S54), and FIG. The state after heating (step S55) and sintering the pressurizing metal bonding material is shown. Before sintering, as shown in FIG. 6 (a), a sinterable metal bonding material 4 having a large metal fine particle diameter is disposed on the entire bonding surface of the back electrode 5a on the back surface of the semiconductor element 5, and between the metal fine particles. There are large voids. In the second embodiment, by forming this void on the entire back surface of the semiconductor element 5, it is possible to secure an escape route for the organic component of the protective film covering the metal fine particles from the center to the end of the back surface of the semiconductor element 5, It is possible to prevent substrate contamination due to the volatilized protective film and bonding inhibition due to the protective film that cannot be completely removed. After the sintering, as shown in FIG. 6B, the voids are reduced by pressurization just below the back surface of the semiconductor element 5, and the sintered joint between the metal particles becomes strong. Further, the end portion of the bonding layer 7 is outside the back surface of the semiconductor element 5 and is in a region where pressure cannot be applied. By using the sinterable metal bonding material 6 having a small metal fine particle diameter, The contact area increases, and peeling can be prevented. Furthermore, the cost can be reduced by suppressing the amount of the sinterable metal bonding material 6 having a small metal fine particle diameter.

接合層７の形成により、セラミック絶縁基板１上への半導体素子５の接合が完了する。なお、Ａｕ、ＡｇおよびＣｕの金属微粒子からなる焼結性金属接合材料の焼結接合においては、焼成条件は、実施の形態１と同様に、温度：２５０〜３５０℃、加圧：０.１〜３０ＭＰａ、接合時間：１〜６０ｍｉｎであることが好ましい。   Formation of the bonding layer 7 completes bonding of the semiconductor element 5 onto the ceramic insulating substrate 1. In addition, in the sintering joining of the sinterable metal joining material composed of Au, Ag and Cu metal fine particles, the firing conditions are the same as in the first embodiment: temperature: 250 to 350 ° C., pressurization: 0.1. It is preferable that it is -30MPa and joining time: 1-60min.

以上のように、この発明の実施の形態２におけるパワーモジュール２００では、セラミック絶縁基板１の表面側の導体層２と半導体素子５とを接合する接合層７は、接合条件としての接合面の位置に基づいて焼結性金属接合材料４および焼結性金属接合材料４よりも粒子径が小さい焼結性金属接合材料６と粒径の異なる焼結性金属接合材料を用い、半導体素子５裏面の裏面電極５ａの全接合面とは粒子径が大きい焼結性金属接合材料４を用いて接合し、セラミック絶縁基板１の表面側の導体層２とは、半導体素子５裏面の周縁部に対応する位置の接合面とは粒子径が小さい焼結性金属接合材料６を用い、半導体素子５裏面の周縁部に対応する位置以外の接合面とは粒子径が大きい焼結性金属接合材料４を用いて接合したことにより、金属粒子の周りの保護膜の総量がさらに少なくなるとともに、半導体素子５裏面の中央部から端部に至るまで、金属微粒子を覆う保護膜の有機成分の抜け道を確保することで、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。
また、半導体素子裏面より外側で、加圧が困難な領域の接合層の端部おいては、導体層の接合面との接触面積を増やすことで、剥離を防ぐことができる。
さらに、金属微粒子径の小さい焼結性金属接合材料６の使用量を抑えたことで、コストを低減できる。 As described above, in the power module 200 according to the second embodiment of the present invention, the bonding layer 7 that bonds the conductor layer 2 on the surface side of the ceramic insulating substrate 1 and the semiconductor element 5 has the position of the bonding surface as a bonding condition. The sinterable metal bonding material 4 and the sinterable metal bonding material 6 having a particle diameter smaller than that of the sinterable metal bonding material 4 and a sinterable metal bonding material having a different particle diameter are used. The entire surface of the back electrode 5a is bonded using a sinterable metal bonding material 4 having a large particle diameter, and the conductor layer 2 on the surface side of the ceramic insulating substrate 1 corresponds to the peripheral edge of the back surface of the semiconductor element 5. The sinterable metal bonding material 6 having a small particle diameter is used as the bonding surface at the position, and the sinterable metal bonding material 4 having a large particle diameter is used from the bonding surface other than the position corresponding to the peripheral edge of the back surface of the semiconductor element 5. By joining the metal particles The total amount of the surrounding protective film is further reduced, and the substrate contamination by the volatilized protective film is ensured by ensuring the passage of the organic components of the protective film covering the metal fine particles from the center to the end of the back surface of the semiconductor element 5. It is possible to prevent bonding inhibition due to the protective film that could not be removed.
Further, at the end portion of the bonding layer in the region where pressurization is difficult outside the back surface of the semiconductor element, peeling can be prevented by increasing the contact area with the bonding surface of the conductor layer.
Furthermore, the cost can be reduced by suppressing the amount of the sinterable metal bonding material 6 having a small metal particle diameter.

実施の形態３．
実施の形態１および実施の形態２では、接合層７を形成する金属微粒子径の異なる焼結性金属接合材料４と焼結性金属接合材料６を、半導体素子５の周縁部と周縁部以外の位置に基づいて配置したが、実施の形態３では、セラミック絶縁基板上の導体層、半導体素子の裏面電極、および接合層、それぞれの金属材料の種類に基づいて配置する場合について説明する。 Embodiment 3 FIG.
In the first embodiment and the second embodiment, the sinterable metal bonding material 4 and the sinterable metal bonding material 6 having different metal fine particle diameters that form the bonding layer 7 are connected to the periphery of the semiconductor element 5 other than the periphery. In the third embodiment, the case where the conductor layer on the ceramic insulating substrate, the back electrode of the semiconductor element, the bonding layer, and the metal material are arranged will be described.

焼結接合において、Ａｕ、Ａｇの貴金属は、同じ貴金属に対しては無加圧でも拡散し焼結が進んでいくのに対し、Ｃｕに対しては拡散率が小さく接触面積を増やさなければ接合強度を確保できない。従来は、導体層または半導体素子に焼結性金属接合材料と拡散反応を起こしやすい金属をメッキしていた。   In sintering joining, Au and Ag precious metals diffuse and sinter with no-pressurization to the same precious metal, whereas Cu does not have a low diffusivity and does not increase the contact area. Strength cannot be secured. Conventionally, a conductor layer or a semiconductor element is plated with a metal that easily causes a diffusion reaction with a sinterable metal bonding material.

この実施の形態３では、ＡｕまたはＡｇの貴金属とＣｕを焼結接合する接合面おいては、金属をメッキする替わりに、焼結性金属接合材料の金属微粒子の粒子径を小さくして、接合材と被接合材の接触面積を増やすことで、接合強度を確保することを可能とした。   In this Embodiment 3, on the joining surface where the noble metal of Au or Ag and Cu are sintered and joined, instead of plating the metal, the particle diameter of the metal fine particles of the sinterable metal joining material is made small to join. By increasing the contact area between the material and the material to be joined, it was possible to ensure the joining strength.

接合面がＣｕの導体層を有するセラミック絶縁基板と接合面がＡｕまたはＡｇの裏面電極を有する半導体素子をＡｕの焼結性金属接合材料またはＡｇの焼結性金属接合材料で接合する場合や、接合面がＡｕまたはＡｇの導体層を有するセラミック絶縁基板と接合面がＣｕの裏面電極を有する半導体素子をＣｕの焼結性金属接合材料で接合する場合、セラミック絶縁基板の導体層と焼結性金属接合材料との接合強度を確保する必要がある。   When joining a ceramic insulating substrate having a conductor layer of Cu bonding surface and a semiconductor element having a back electrode of Au or Ag bonding surface with Au sinterable metal bonding material or Ag sinterable metal bonding material, When bonding a ceramic insulating substrate having a conductor layer with a bonding surface of Au or Ag and a semiconductor element having a back electrode with a bonding surface of Cu with a Cu sinterable metal bonding material, the conductive layer of the ceramic insulating substrate and the sinterability It is necessary to ensure the bonding strength with the metal bonding material.

図７は、この発明の実施の形態３によるパワーモジュール３００の要部を示す模式図である。図７（ａ）は、上面図であり、図７（ｂ）は、図７（ａ）のＡ−Ａ’線での矢視断面図である。
図７（ｂ）に示すように、この実施の形態３におけるパワーモジュール３００では、セラミック絶縁基板１の表面に設けられたＣｕの導体層２および半導体素子５の裏面に設けられたＡｕの裏面電極５ａの接合面と接合するＡｕの焼結性金属接合材料からなる接合層７が、半導体素子５裏面のＡｕの裏面電極５ａの全接合面に粒子径が大きいＡｕの焼結性金属接合材料４で接合し、セラミック絶縁基板１の表面側のＣｕの導体層２の全接合面には、粒子径が小さいＡｕの焼結性金属接合材料６で接合している。
なお、ここでは、半導体素子５の裏面電極５ａおよび接合層７は、Ａｕとしたが、いずれか一方がＡｇ、または両方がＡｇであってもよい。
また、導体層２がＡｕまたはＡｇ、半導体素子５の裏面電極５ａおよび接合層７がＣｕの組合せであってもよい。
パワーモジュール３００のその他の構成については、実施の形態１のパワーモジュール１００と同様であり、その説明を省略する。 FIG. 7 is a schematic diagram showing a main part of a power module 300 according to Embodiment 3 of the present invention. FIG. 7A is a top view, and FIG. 7B is a cross-sectional view taken along the line AA ′ in FIG.
As shown in FIG. 7B, in the power module 300 according to the third embodiment, the Cu conductor layer 2 provided on the surface of the ceramic insulating substrate 1 and the Au back electrode provided on the back surface of the semiconductor element 5. The bonding layer 7 made of Au sinterable metal bonding material to be bonded to the bonding surface 5a has an Au sinterable metal bonding material 4 having a large particle diameter on the entire bonding surface of the Au back electrode 5a on the back surface of the semiconductor element 5. And bonded to the entire bonding surface of the Cu conductor layer 2 on the surface side of the ceramic insulating substrate 1 with an Au sinterable metal bonding material 6 having a small particle diameter.
Here, although the back electrode 5a and the bonding layer 7 of the semiconductor element 5 are Au, either one may be Ag or both may be Ag.
The conductor layer 2 may be a combination of Au or Ag, and the back electrode 5a of the semiconductor element 5 and the bonding layer 7 may be a combination of Cu.
The other configuration of the power module 300 is the same as that of the power module 100 of the first embodiment, and the description thereof is omitted.

次に、この発明の実施の形態３によるパワーモジュール３００の製造方法について、説明する。なお、パワーモジュール３００の製造工程は、基本的に実施の形態の２のパワーモジュール２００の製造工程と同じであり、図５を用いて説明する。   Next, a method for manufacturing the power module 300 according to Embodiment 3 of the present invention will be described. The manufacturing process of the power module 300 is basically the same as the manufacturing process of the power module 200 according to the second embodiment, and will be described with reference to FIG.

まず最初に、セラミック絶縁基板１の表面側のＣｕの導体層２上に、粒子径が小さいＡｕの焼結性金属接合材料６を印刷により塗布する（ステップＳ５１）。半導体素子５の裏面の形状が、１０ｍｍ×１０ｍｍの正方形である場合には、半導体素子５を配置する領域に、例えば、１１ｍｍ×１１ｍｍの正方形状に、１０〜１００μｍ厚でＡｕの焼結性金属接合材料６を塗布する。Ａｕの焼結性金属接合材料６を塗布した後、一度乾燥しておく（ステップＳ５２）。   First, Au sinterable metal bonding material 6 having a small particle size is applied by printing on the Cu conductor layer 2 on the surface side of the ceramic insulating substrate 1 (step S51). In the case where the shape of the back surface of the semiconductor element 5 is a square of 10 mm × 10 mm, a sinterable metal of Au having a thickness of 10 to 100 μm in a square shape of 11 mm × 11 mm, for example, in a region where the semiconductor element 5 is disposed. The bonding material 6 is applied. After the Au sinterable metal bonding material 6 is applied, it is once dried (step S52).

次いで、ステップＳ５１で塗布後、乾燥したＡｕの焼結性金属接合材料６の上に、粒子径が大きいＡｕの焼結性金属接合材料４を印刷により塗布する（ステップＳ５３）。ここでは、正方形に印刷されているＡｕの焼結性金属接合材料６の上に、中心を合わせて、１０．５ｍｍ×１０．５ｍｍの正方形状に、１０〜１００μｍ厚でＡｕの焼結性金属接合材料６を塗布する。焼結性金属接合材料４を塗布した後、再度乾燥（ステップＳ５４）する。   Next, after the application in step S51, the Au sinterable metal bonding material 4 having a large particle diameter is applied by printing on the dried Au sinterable metal bonding material 6 (step S53). Here, on the Au sinterable metal bonding material 6 printed in a square, the center is aligned to form a square of 10.5 mm × 10.5 mm, and a 10-100 μm thick Au sinterable metal The bonding material 6 is applied. After the sinterable metal bonding material 4 is applied, it is dried again (step S54).

最後に、正方形状に塗布されたＡｕの焼結性金属接合材料４上に、半導体素子５のＡｕの裏面電極５ａが位置するように半導体素子５を載せ、半導体素子５を押下してＡｕの焼結性金属接合材料４および焼結性金属接合材料６を加圧しながら加熱（ステップＳ５５）することで、焼結性金属接合材料４および焼結性金属接合材料６は、導体層２および裏面電極５ａの接合面および金属微粒子同士と焼結接合し、Ａｕの接合層７が形成される。   Finally, the semiconductor element 5 is placed on the Au sinterable metal bonding material 4 applied in a square shape so that the Au back electrode 5a of the semiconductor element 5 is positioned, and the semiconductor element 5 is pushed down to depress Au. By heating the sinterable metal bonding material 4 and the sinterable metal bonding material 6 while applying pressure (step S55), the sinterable metal bonding material 4 and the sinterable metal bonding material 6 become the conductor layer 2 and the back surface. A bonding surface 7 of Au is formed by sintering and bonding with the bonding surface of the electrode 5a and the metal fine particles.

図８は、図７（ｂ）の領域Ｂ、つまり半導体素子５裏面の周縁部の拡大断面図である。図８（ａ）は、焼結性金属接合材料４を塗布して乾燥（ステップＳ５４）した後に半導体素子５を載せた、焼結する前の状態を示し、図８（ｂ）は、焼結性金属接合材料を加圧しながら加熱（ステップＳ５５）し、焼結した後の状態を示す。焼結前においては、図８（ａ）に示すように、半導体素子５裏面の裏面電極５ａの全接合面に、金属微粒子径が大きいＡｕの焼結性金属接合材料４が配置され、金属微粒子間に空隙が大きく存在する。この空隙を半導体素子５裏面の裏面電極５ａの全接合面に形成することで、半導体素子５裏面の中央部から端部に至るまで、金属微粒子を覆う保護膜の有機成分の抜け道を確保でき、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。焼結後は、図８（ｂ）に示すように、半導体素子５裏面直下では加圧によって空隙は減少し、金属粒子間の焼結接合が強固となる。また、Ｃｕの導体層２の全接合面に、金属微粒子径が小さいＡｕの焼結性金属接合材料６が配置され、接触面積を増やすことで、接合強度を向上させることができる。さらに、接合層７の端部は、半導体素子５裏面より外側で、加圧できない領域にあるが、金属微粒子径の小さいＡｕの焼結性金属接合材料６を用いることで、Ｃｕの導体層２の接合面との接触面積が増え、剥離を防ぐことができる。   FIG. 8 is an enlarged cross-sectional view of the region B in FIG. 7B, that is, the peripheral edge of the back surface of the semiconductor element 5. FIG. 8A shows a state before the semiconductor element 5 is mounted after the sinterable metal bonding material 4 is applied and dried (step S54), and FIG. The state after heating (step S55) and sintering the pressurizing metal bonding material is shown. Before sintering, as shown in FIG. 8 (a), Au sinterable metal bonding material 4 having a large metal particle diameter is arranged on all the bonding surfaces of the back electrode 5a on the back surface of the semiconductor element 5, and the metal particles There are large voids between them. By forming this void in the entire bonding surface of the back surface electrode 5a on the back surface of the semiconductor element 5, from the center to the end of the back surface of the semiconductor element 5, it is possible to secure a passage of organic components in the protective film covering the metal fine particles, It is possible to prevent substrate contamination due to the volatilized protective film and bonding inhibition due to the protective film that cannot be completely removed. After the sintering, as shown in FIG. 8B, the voids are reduced by pressurization immediately under the back surface of the semiconductor element 5, and the sintered joint between the metal particles is strengthened. In addition, Au sinterable metal bonding material 6 having a small metal fine particle diameter is disposed on all bonding surfaces of the Cu conductor layer 2, and the contact strength can be increased by increasing the contact area. Further, the end portion of the bonding layer 7 is outside the back surface of the semiconductor element 5 and is in a region where pressure cannot be applied. By using the Au sinterable metal bonding material 6 having a small metal fine particle diameter, the Cu conductor layer 2 is formed. The contact area with the joint surface increases, and peeling can be prevented.

接合層７の形成により、セラミック絶縁基板１上への半導体素子５の接合が完了する。なお、焼成条件は、実施の形態１と同様に、温度：２５０〜３５０℃、加圧：０.１〜３０ＭＰａ、接合時間：１〜６０ｍｉｎであることが好ましい。   Formation of the bonding layer 7 completes bonding of the semiconductor element 5 onto the ceramic insulating substrate 1. The firing conditions are preferably temperature: 250 to 350 ° C., pressurization: 0.1 to 30 MPa, and joining time: 1 to 60 min, as in the first embodiment.

一方、接合面がＣｕの導体層を有するセラミック絶縁基板と接合面がＡｕまたはＡｇの半導体素子をＣｕの焼結性金属接合材料で接合する場合や、接合面がＡｕまたはＡｇの導体層を有するセラミック絶縁基板と接合面がＣｕの裏面電極を有する半導体素子をＡｕの焼結性金属接合材料またはＡｇの焼結性金属接合材料で接合する場合、半導体素子の裏面電極と焼結性金属接合材料との接合強度を確保する必要がある。   On the other hand, when a ceramic insulating substrate having a Cu conductive layer and a semiconductor element having a bonding surface of Au or Ag are bonded with a Cu sintered metal bonding material, or the bonding surface has a Au or Ag conductive layer. When bonding a ceramic element and a semiconductor element having a back surface electrode having a bonding surface of Cu with an Au sinterable metal bonding material or an Ag sinterable metal bonding material, the back surface electrode of the semiconductor element and the sinterable metal bonding material It is necessary to ensure the bonding strength.

図９は、この発明の実施の形態３によるパワーモジュール３０１の要部を示す模式図である。図９（ａ）は、上面図であり、図９（ｂ）は、図９（ａ）のＡ−Ａ’線での矢視断面図である。
図９（ｂ）に示すように、この実施の形態３におけるパワーモジュール３０１では、セラミック絶縁基板１の表面に設けられたＣｕの導体層２の接合面および半導体素子５の裏面に設けられたＡｕの裏面電極５ａの接合面とを接合するＣｕの焼結性金属接合材料からなる接合層７が、半導体素子５裏面のＡｕの裏面電極５ａの全接合面には、全面に粒子径が小さいＣｕの焼結性金属接合材料６で接合し、セラミック絶縁基板１の表面側のＣｕの導体層２の接合面においては、接合層７の端部では粒子径が小さいＣｕの焼結性金属接合材料６で接合し、端部以外は粒子径が大きいＣｕの焼結性金属接合材料４で接合している。
なお、ここでは、半導体素子５の裏面電極５ａはＡｕとしたが、Ａｇであってもよい。
また、導体層２および接合層７がＡｕまたはＡｇ、半導体素子５の裏面電極がＣｕの組合せであってもよい。
パワーモジュール３０１のその他の構成については、実施の形態１のパワーモジュール１００と同様であり、その説明を省略する。 FIG. 9 is a schematic diagram showing a main part of a power module 301 according to Embodiment 3 of the present invention. FIG. 9A is a top view, and FIG. 9B is a cross-sectional view taken along line AA ′ in FIG. 9A.
As shown in FIG. 9 (b), in the power module 301 according to the third embodiment, Au provided on the bonding surface of the Cu conductor layer 2 provided on the surface of the ceramic insulating substrate 1 and on the back surface of the semiconductor element 5. The bonding layer 7 made of a sinterable metal bonding material of Cu for bonding the bonding surface of the back electrode 5a is formed on the entire bonding surface of the Au back electrode 5a on the back surface of the semiconductor element 5 with a small particle diameter. In the joining surface of the Cu conductor layer 2 on the surface side of the ceramic insulating substrate 1, a sintered metal joining material of Cu having a small particle diameter at the end of the joining layer 7. 6 are joined together by a sinterable metal joining material 4 of Cu having a large particle diameter except for the end portions.
Here, although the back electrode 5a of the semiconductor element 5 is Au, Ag may also be used.
The conductor layer 2 and the bonding layer 7 may be a combination of Au or Ag, and the back electrode of the semiconductor element 5 may be a combination of Cu.
The other configuration of the power module 301 is the same as that of the power module 100 of the first embodiment, and the description thereof is omitted.

次に、この発明の実施の形態３によるパワーモジュール３０１の製造方法について、図１０に基づき説明する。図１０は、この発明の実施の形態３によるパワーモジュール３０１の製造工程を示すフローチャート図である。   Next, the manufacturing method of the power module 301 by Embodiment 3 of this invention is demonstrated based on FIG. FIG. 10 is a flowchart showing manufacturing steps of the power module 301 according to the third embodiment of the present invention.

まず最初に、セラミック絶縁基板１の表面側のＣｕの導体層２上に、粒子径が大きいＣｕの焼結性金属接合材料４を印刷により塗布する（ステップＳ１０１）。半導体素子５の裏面の形状が、１０ｍｍ×１０ｍｍの正方形である場合には、半導体素子５を配置する領域に、例えば、１１ｍｍ×１１ｍｍの正方形状に、１０〜１００μｍ厚でＣｕの焼結性金属接合材料４を塗布する。Ｃｕの焼結性金属接合材料４を塗布した後、一度乾燥しておく（ステップＳ１０２）。   First, a Cu sinterable metal bonding material 4 having a large particle diameter is applied on the Cu conductor layer 2 on the surface side of the ceramic insulating substrate 1 by printing (step S101). When the shape of the back surface of the semiconductor element 5 is a square of 10 mm × 10 mm, a sinterable metal of Cu having a thickness of 10 to 100 μm in a square shape of 11 mm × 11 mm, for example, in a region where the semiconductor element 5 is disposed. The bonding material 4 is applied. After the Cu sinterable metal bonding material 4 is applied, it is once dried (step S102).

次いで、ステップＳ１０１で塗布後、乾燥したＣｕの焼結性金属接合材料４の上に、粒子径が小さいＣｕの焼結性金属接合材料６を印刷により塗布する（ステップＳ１０３）。ここでは、粒子径が大きい焼結性金属接合材料４が、半導体素子５裏面の裏面電極５ａの全接合面だけではなく、接合層７の端部においてセラミック絶縁基板１の表面側のＣｕの導体層２とも接合させるために、正方形に印刷されているＣｕの焼結性金属接合材料４を覆うように、中心を合わせて、例えば、１２ｍｍ×１２ｍｍの正方形状に、１０〜１００μｍ厚でＣｕの焼結性金属接合材料６を塗布する。焼結性金属接合材料６を塗布した後、再度乾燥（ステップＳ１０４）する。   Next, after applying in step S101, a Cu sinterable metal bonding material 6 having a small particle size is applied by printing on the dried Cu sinterable metal bonding material 4 (step S103). Here, the sinterable metal bonding material 4 having a large particle size is not only the entire bonding surface of the back electrode 5a on the back surface of the semiconductor element 5, but also the Cu conductor on the surface side of the ceramic insulating substrate 1 at the end of the bonding layer 7. In order to join the layer 2 as well, the center is aligned so as to cover the Cu sinterable metal bonding material 4 printed in a square, for example, in a square shape of 12 mm × 12 mm, with a thickness of 10 to 100 μm of Cu. A sinterable metal bonding material 6 is applied. After applying the sinterable metal bonding material 6, it is dried again (step S104).

最後に、正方形状に塗布されたＣｕの焼結性金属接合材料６上に、半導体素子５のＡｕの裏面電極が位置するように半導体素子５を載せ、半導体素子５を押下してＣｕの焼結性金属接合材料４および焼結性金属接合材料６を加圧しながら加熱（ステップＳ１０５）することで、焼結性金属接合材料４および焼結性金属接合材料６は、導体層２および裏面電極５ａの接合面および金属微粒子同士と焼結接合し、Ｃｕの接合層７が形成される。   Finally, the semiconductor element 5 is placed on the Cu sinterable metal bonding material 6 applied in a square shape so that the Au back electrode of the semiconductor element 5 is positioned, and the semiconductor element 5 is pressed down to burn the Cu. By heating the sinterable metal bonding material 4 and the sinterable metal bonding material 6 while applying pressure (step S105), the sinterable metal bonding material 4 and the sinterable metal bonding material 6 become the conductor layer 2 and the back electrode. The bonding surface 7a and the metal fine particles are sintered and bonded together to form the Cu bonding layer 7.

図１１は、図９（ｂ）の領域Ｂ、つまり半導体素子５裏面の周縁部の拡大断面図である。図１１（ａ）は、焼結性金属接合材料６を塗布して乾燥（ステップＳ１０４）した後に半導体素子５を載せた、焼結する前の状態を示し、図１１（ｂ）は、焼結性金属接合材料を加圧しながら加熱（ステップＳ１０５）し、焼結した後の状態を示す。焼結前においては、図１１（ａ）に示すように、セラミック絶縁基板１の表面側のＣｕの導体層２上の、半導体素子５裏面に対応する位置の全接合面に、金属微粒子径が大きいＣｕの焼結性金属接合材料４が配置され、金属微粒子間に空隙が大きく存在する。この空隙を導体層２上の半導体素子５裏面に対応する位置の全接合面に形成することで、半導体素子５裏面の中央部から端部に至るまで、金属微粒子を覆う保護膜の有機成分の抜け道を確保でき、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。焼結後は、図１１（ｂ）に示すように、半導体素子５裏面直下では加圧によって空隙は減少し、金属粒子間の焼結接合が強固となる。また、半導体素子５のＡｕの裏面電極５ａとＣｕの接合層７の全接合面に、金属微粒子径が小さいＡｕの焼結性金属接合材料６が配置され、接触面積を増やすことで、接合強度を向上させることができる。さらに、接合層７の端部は、半導体素子５裏面より外側で、加圧できない領域にあるが、金属微粒子径の小さい焼結性金属接合材料６を用いることで、導体層２の接合面との接触面積が増え、剥離を防ぐことができる。   FIG. 11 is an enlarged cross-sectional view of a region B in FIG. 9B, that is, a peripheral edge portion of the back surface of the semiconductor element 5. FIG. 11A shows a state before the semiconductor element 5 is mounted after the sinterable metal bonding material 6 is applied and dried (step S104), and FIG. The state after heating (step S105) and sintering the conductive metal bonding material is shown. Before sintering, as shown in FIG. 11 (a), the metal fine particle diameter is on the entire bonding surface at the position corresponding to the back surface of the semiconductor element 5 on the Cu conductor layer 2 on the front surface side of the ceramic insulating substrate 1. A large Cu sinterable metal bonding material 4 is arranged, and a large gap exists between the metal fine particles. By forming this void on the entire bonding surface at a position corresponding to the back surface of the semiconductor element 5 on the conductor layer 2, the organic component of the protective film covering the metal fine particles is covered from the center to the end of the back surface of the semiconductor element 5. The escape route can be secured, and the substrate contamination due to the volatilized protective film and the bonding inhibition due to the protective film that could not be removed can be prevented. After the sintering, as shown in FIG. 11B, the voids are reduced by pressurization immediately below the back surface of the semiconductor element 5, and the sintered joint between the metal particles is strengthened. Further, Au sinterable metal bonding material 6 having a small metal fine particle diameter is disposed on all bonding surfaces of the Au back electrode 5a and the Cu bonding layer 7 of the semiconductor element 5 to increase the contact area, thereby increasing the bonding strength. Can be improved. Furthermore, although the edge part of the joining layer 7 exists in the area | region which cannot pressurize outside the semiconductor element 5 back surface, by using the sinterable metal joining material 6 with a small metal fine particle diameter, The contact area increases, and peeling can be prevented.

接合層７の形成により、セラミック絶縁基板１上への半導体素子５の接合が完了する。なお、焼成条件は、実施の形態１と同様に、温度：２５０〜３５０℃、加圧：０.１〜３０ＭＰａ、接合時間：１〜６０ｍｉｎであることが好ましい。   Formation of the bonding layer 7 completes bonding of the semiconductor element 5 onto the ceramic insulating substrate 1. The firing conditions are preferably temperature: 250 to 350 ° C., pressurization: 0.1 to 30 MPa, and joining time: 1 to 60 min, as in the first embodiment.

以上のように、この発明の実施の形態３におけるパワーモジュール３００、３０１では、セラミック絶縁基板１の表面側の導体層２と半導体素子５とを接合する接合層７は、接合条件としての接合面の材料の種類に基づいて焼結性金属接合材料４および焼結性金属接合材料４よりも粒子径が小さい焼結性金属接合材料６と粒径の異なる焼結性金属接合材料を用い、ＡｕまたはＡｇの貴金属とＣｕの接合の関係にある接合面においては、粒子径が小さい焼結性金属接合材料６を用いて接合したことにより、接合面との接触面積を増やすことで、剥離を防ぐことができる。
また、半導体素子裏面より外側で、加圧が困難な領域の接合層の端部おいては、導体層との接触面積を増やすことで、剥離を防ぐことができる。
さらに、ＡｕまたはＡｇの貴金属とＣｕの接合の関係にない接合面においては、粒子径が大きい焼結性金属接合材料６を用いて接合したことにより、半導体素子５裏面側の中央部から端部に至るまで、金属微粒子を覆う保護膜の有機成分の抜け道を確保することで、揮発した保護膜による基板汚染や抜けきらなかった保護膜による接合阻害を防ぐことができる。 As described above, in the power modules 300 and 301 according to the third embodiment of the present invention, the bonding layer 7 for bonding the conductor layer 2 on the surface side of the ceramic insulating substrate 1 and the semiconductor element 5 has the bonding surface as a bonding condition. The sinterable metal bonding material 4 and the sinterable metal bonding material 6 having a particle diameter smaller than that of the sinterable metal bonding material 4 and a sinterable metal bonding material having a different particle diameter from the sinterable metal bonding material 4 are used. Alternatively, at the joint surface in which Ag noble metal and Cu are joined, by using the sinterable metal joint material 6 having a small particle diameter, the contact area with the joint surface is increased, thereby preventing peeling. be able to.
Further, at the end of the bonding layer in the region where pressurization is difficult outside the back surface of the semiconductor element, peeling can be prevented by increasing the contact area with the conductor layer.
Further, on the joint surface that is not in the relationship of joining between the noble metal of Au or Ag and Cu, by joining using the sinterable metal joint material 6 having a large particle diameter, the end portion from the center portion on the back surface side of the semiconductor element 5 is obtained. Thus, by securing a passage of organic components in the protective film covering the metal fine particles, substrate contamination due to the volatilized protective film and bonding inhibition due to the protective film that cannot be completely removed can be prevented.

上述した実施の形態１から実施の形態３におけるパワーモジュールを構成する半導体素子５としては、珪素（Ｓｉ）によって形成されたものには限定されず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成してもよい。ワイドバンドギャップ半導体としては、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドなどが挙げられことは、すでに述べたとおりである。   The semiconductor element 5 constituting the power module in the first to third embodiments described above is not limited to one formed of silicon (Si), and is a wide band gap semiconductor having a larger band gap than silicon. May be formed. As described above, examples of the wide band gap semiconductor include silicon carbide (SiC), gallium nitride (GaN), and diamond.

このようなワイドバンドギャップ半導体によって形成された半導体素子は、耐電圧性が高く、許容電流密度も高い。また、耐熱性も高いため、放熱部材の冷却フィンの小型化や、空冷化が可能であるので、パワーモジュールの一層の小型化が可能になる。   A semiconductor element formed of such a wide bandgap semiconductor has high voltage resistance and high allowable current density. In addition, since the heat resistance is high, the cooling fins of the heat dissipating member can be downsized and air cooled, so that the power module can be further downsized.

パワーモジュールの小型化が進むと、放熱性を確保し、熱応力に対する長期信頼性への要求がさらに高度になる。このような要求に対しても、この発明のパワーモジュールは、優れた効果を発揮する。   As miniaturization of power modules progresses, the requirement for long-term reliability against thermal stress is further enhanced to ensure heat dissipation. The power module of the present invention exhibits excellent effects even for such demands.

なお、この発明は、発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。   It should be noted that within the scope of the invention, the embodiments can be freely combined, or the embodiments can be appropriately modified or omitted.

１ セラミック絶縁基板、２ 導体層、４ 焼結性金属接合材料、５ 半導体素子、５ａ 裏面電極、６ 焼結性金属接合材料、７ 接合層、１００、２００、３００、３０１ パワーモジュール DESCRIPTION OF SYMBOLS 1 Ceramic insulating substrate, 2 Conductor layer, 4 Sinterable metal joining material, 5 Semiconductor element, 5a Back electrode, 6 Sinterable metal joining material, 7 Joining layer, 100, 200, 300, 301 Power module

Claims (7)

表面に導体層が設けられた絶縁基板と、
裏面に電極が設けられた矩形の半導体素子と、
焼結性金属接合材料を用いて前記絶縁基板の導体層と前記半導体素子の電極とを接合した接合層とを備えたパワーモジュールであって、
前記接合層は、
前記半導体素子の端部から内側に前記半導体素子の大きさの１／１０の位置よりさらに内側の領域となる前記半導体素子の中央部に形成された第１の接合層と、
前記半導体素子の端部から内側に前記半導体素子の大きさの１／１０の位置より外側で端部を含む額縁形状の領域に形成された第２の接合層と、を含み、
前記第２の接合層は前記第１の接合層で用いられた焼結性金属接合材料より粒子径の小さい焼結性金属接合材料を用いて形成されたことを特徴とするパワーモジュール。 An insulating substrate provided with a conductor layer on the surface;
A rectangular semiconductor element provided with electrodes on the back surface;
A power module comprising a bonding layer obtained by bonding a conductor layer of the insulating substrate and an electrode of the semiconductor element using a sinterable metal bonding material,
The bonding layer is
A first bonding layer formed in a central portion of the semiconductor element that is a region further on the inner side than a position of 1/10 of the size of the semiconductor element from an end portion of the semiconductor element;
A second bonding layer formed in a frame-shaped region including the end outside the position of 1/10 of the size of the semiconductor element on the inner side from the end of the semiconductor element,
The power module, wherein the second bonding layer is formed using a sinterable metal bonding material having a particle diameter smaller than that of the sinterable metal bonding material used in the first bonding layer . 前記第２の接合層は、二層構造であって、前記絶縁基板側の層のみ粒子径の小さい前記焼結性金属接合材料を用いたことを特徴とする請求項１に記載のパワーモジュール。 2. The power module according to claim 1, wherein the second bonding layer has a two-layer structure, and the sinterable metal bonding material having a small particle diameter is used only for the layer on the insulating substrate side. 表面に導体層が設けられた絶縁基板と、
裏面に電極が設けられた半導体素子と、
焼結性金属接合材料を用いて前記絶縁基板の導体層と前記半導体素子の電極とを接合した接合層とを備えたパワーモジュールであって、
前記接合層は、二層構造であって、少なくとも前記半導体素子側の層または前記絶縁基板側の層のいずれか一方に他方より粒子径の小さい前記焼結性金属接合材料を用いたことを特徴とするパワーモジュール。 An insulating substrate provided with a conductor layer on the surface;
A semiconductor element having an electrode on the back surface;
A power module comprising a bonding layer obtained by bonding a conductor layer of the insulating substrate and an electrode of the semiconductor element using a sinterable metal bonding material,
The bonding layer has a two-layer structure, and at least one of the semiconductor element side layer and the insulating substrate side layer uses the sinterable metal bonding material having a smaller particle diameter than the other. And power module. 前記絶縁基板の導体層の材料と前記接合層に用いられる材料が、一方がＡｕまたはＡｇで、他方がＣｕである場合に、前記接合層は、前記絶縁基板側の層に粒子径の小さい前記焼結性金属接合材料を用いたことを特徴とする請求項３に記載のパワーモジュール。 The material used for the material and the bonding layer of the conductor layer of the insulating substrate, one of Au or Ag, to the other is Cu, the bonding layer is smaller the particle diameters in the layer of the insulating substrate side The power module according to claim 3, wherein a sinterable metal bonding material is used. 前記半導体素子の電極の材料と前記接合層に用いられる材料が、一方がＡｕまたはＡｇで、他方がＣｕである場合に、前記接合層は、前記絶縁基板側の層の端部および前記半導体素子側の層に粒子径の小さい前記焼結性金属接合材料を用いたことを特徴とする請求項３に記載のパワーモジュール。 The material used for the material and the bonding layer of the electrode of the semiconductor element, one is a Au or Ag, to the other is Cu, the bonding layer, the insulating substrate side of the layer of the end portion and the semiconductor element The power module according to claim 3, wherein the sinterable metal bonding material having a small particle diameter is used for the side layer . 前記半導体素子は、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたことを特徴とする請求項１から請求項５のいずれか１項に記載のパワーモジュール。 6. The power module according to claim 1 , wherein the semiconductor element is formed of a wide band gap semiconductor having a larger band gap than silicon . 前記ワイドバンドギャップ半導体は、炭化ケイ素、窒化ガリウム系材料または、ダイヤモンドを用いた半導体であることを特徴とする請求項６に記載のパワーモジュール。 The power module according to claim 6 , wherein the wide band gap semiconductor is a semiconductor using silicon carbide, a gallium nitride-based material, or diamond.
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