CN105190856A - Semiconductor device, power conversion device and semiconductor device manufacturing method - Google Patents

Semiconductor device, power conversion device and semiconductor device manufacturing method Download PDF

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Publication number
CN105190856A
CN105190856A CN201380074724.4A CN201380074724A CN105190856A CN 105190856 A CN105190856 A CN 105190856A CN 201380074724 A CN201380074724 A CN 201380074724A CN 105190856 A CN105190856 A CN 105190856A
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China
Prior art keywords
knitting layer
semiconductor device
layer
conductive component
knitting
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CN201380074724.4A
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Chinese (zh)
Inventor
小熊清典
竹中国浩
山口芳文
本田友和
氏田祐
佐佐木亮
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Yaskawa Electric Corp
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Yaskawa Electric Corp
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Publication of CN105190856A publication Critical patent/CN105190856A/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Inverter Devices (AREA)
  • Die Bonding (AREA)

Abstract

A semiconductor device (100, 100a-100c) comprises a conductive member (20), a semiconductor device component (10) disposed on top of the conductive member, and a bonding layer for bonding the conductive member and the semiconductor device component. When viewed in plan view, the bonding layer includes the following: a first bonding layer (16) that is disposed inward from the outer edge of the semiconductor device component; and a second bonding layer (17) that is disposed on the outer side of the first bonding layer and has smaller porosity than the first bonding layer.

Description

The manufacture method of semiconductor device, power inverter and semiconductor device
Technical field
The present invention relates to the manufacture method of semiconductor device, power inverter and semiconductor device.
Background technology
Conventionally, there is known the semiconductor device that conductive component and part are bonded together by knitting layer.Such as in Japanese Unexamined Patent Publication 2012-009703 publication, disclose such semiconductor device.
In above-mentioned Japanese Unexamined Patent Publication 2012-009703 publication, disclose a kind of semiconductor device, it has: substrate, and it has conductive pattern; Semiconductor element, it is configured on the conductive pattern of substrate; And knitting layer, it is configured between the conductive pattern of substrate and semiconductor element, conductive pattern and semiconductor element is bonded together.The knitting layer of this semiconductor device has the sintering pattern of three-decker on longitudinal cross-section.In addition, the sintering pattern of the superiors in the sintering pattern of three-decker engages with the whole back side of semiconductor element, and undermost sintering pattern engages with the conductive pattern of substrate.
Prior art document
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 2012-009703 publication
Summary of the invention
The problem that invention will solve
; such problem is there is: because whole of forming near the inner side comprising the back side of the superiors in 3 layers of knitting layer sintering pattern and semiconductor element and peripheral part engages in the semiconductor device disclosed in above-mentioned Japanese Unexamined Patent Publication 2012-009703 publication; therefore; when the voidage of the sintering pattern of the superiors is larger; interparticle engaging force is more weak; therefore; when being applied with thermal stress, the sintering pattern that there are the superiors is peeled off or on sintering pattern, produces the situation of crack (be full of cracks).In addition, there is such problem: when the voidage of the sintering pattern of the superiors is less, when being applied with thermal stress when the difference due to the coefficient of thermal expansion between part and knitting layer, compared with the situation that voidage is larger, thermal stress is not easy to be relaxed, therefore, there is the situation destroyed with the semiconductor element of sintering combination of patterns.
The present invention completes to solve problem as described above, 1 object of the present invention is the manufacture method providing a kind of semiconductor device, power inverter and semiconductor device, it can suppress the stripping of the knitting layer near the peripheral part of part and the generation in crack, and the situation that when can suppress the difference at the coefficient of thermal expansion because of part and knitting layer and be applied with thermal stress, part is destroyed.
For the means of dealing with problems
The semiconductor device of the 1st aspect possesses: conductive component; Semiconductor device part, it is configured on conductive component; And knitting layer, it is configured between conductive component and semiconductor device part, and conductive component and semiconductor device part are engaged, knitting layer comprises: the 1st knitting layer, its configure when overlooking than semiconductor device part outer rim in the inner part; With the 2nd knitting layer, it is configured in the outside of the 1st knitting layer, and has the voidage less than the 1st knitting layer.
In semiconductor device in the 1st, by arranging knitting layer, outside is engaged by the 2nd knitting layer with the voidage less than the 1st knitting layer, therefore, by the 2nd knitting layer with little voidage that interionic adhesion is stronger, the stripping of the knitting layer near the peripheral part that can suppress semiconductor device part and crack (be full of cracks), wherein, described knitting layer is included in and configures than outer rim the 1st knitting layer in the inner part of semiconductor device part when overlooking, there is the 2nd knitting layer of the voidage less than the 1st knitting layer with the outside being configured in the 1st knitting layer.In addition, the 1st inner side of knitting layer to semiconductor device part with the voidage larger than the 2nd knitting layer is utilized to engage, thus, the coefficient of thermal expansion due to semiconductor device part and knitting layer difference and when being applied with thermal stress, thermal stress is relaxed compared with the 1st knitting layer of large porosity by having, therefore, it is possible to suppress semiconductor device part to be destroyed.Thereby, it is possible to the stripping of knitting layer near the peripheral part suppressing semiconductor device part and crack, and, the situation that when can suppress the difference at the coefficient of thermal expansion due to part and knitting layer and be applied with thermal stress, part is destroyed.
The power inverter of the 2nd aspect possesses: conductive component; Power inverter part, it is configured on conductive component; And knitting layer, it is configured between conductive component and power inverter part, and conductive component and power inverter part are engaged, knitting layer comprises: the 1st knitting layer, its configure when overlooking than power inverter part outer rim in the inner part; With the 2nd knitting layer, it is configured in the outside of the 1st knitting layer, and has the voidage less than the 1st knitting layer.
In power inverter in the 2nd, by arranging knitting layer, outside is engaged by the 2nd knitting layer with the voidage less than the 1st knitting layer, therefore, by the 2nd knitting layer with little voidage that interionic adhesion is stronger, the stripping of the knitting layer near the peripheral part that can suppress power inverter part and crack (be full of cracks), wherein, described knitting layer is included in and configures than outer rim the 1st knitting layer in the inner part of power inverter part when overlooking, there is the 2nd knitting layer of the voidage less than the 1st knitting layer with the outside being configured in the 1st knitting layer.In addition, the 1st inner side of knitting layer to power inverter part with the voidage larger than the 2nd knitting layer is utilized to engage, thus, the coefficient of thermal expansion due to power inverter part and knitting layer difference and when being applied with thermal stress, thermal stress is relaxed compared with the 1st knitting layer of large porosity by having, therefore, it is possible to suppress power inverter part to be destroyed.Thus, such power inverter can be provided: the stripping of the knitting layer near the peripheral part that can suppress part and crack, and, the situation that when can suppress the difference at the coefficient of thermal expansion due to part and knitting layer and be applied with thermal stress, part is destroyed.
The manufacture method of the semiconductor device of the 3rd aspect comprises: the operation forming the 1st metal layer of paste on conductive component; To cover the operation of the mode configuring semiconductor device part of the 1st metal layer of paste; By heat-treating the operation forming the 1st knitting layer engaged with semiconductor device part by conductive component to the 1st metal layer of paste; Near the end of semiconductor device part, form the operation of the 2nd metal layer of paste, the 2nd metal layer of paste comprises the average grain diameter metallic less than the average grain diameter of the 1st metal layer of paste; And by heat-treating the operation forming the 2nd knitting layer to the 2nd metal layer of paste, the 2nd knitting layer engages near the end of conductive component and semiconductor device part, and has the voidage less than the 1st knitting layer.
In the manufacture method of the semiconductor device in the 3rd, by arranging the operation of formation the 2nd knitting layer, the outside of semiconductor device part is engaged by the 2nd knitting layer with the voidage less than the 1st knitting layer, therefore, 2nd knitting layer with little voidage that interionic adhesion can be utilized strong is to the stripping of knitting layer near the peripheral part suppressing semiconductor device part and the generation of crack (be full of cracks), wherein, 2nd knitting layer makes conductive component engage with near the end of semiconductor device part, and has the voidage less than the 1st knitting layer.In addition, the 1st inner side of knitting layer to semiconductor device part with the voidage larger than the 2nd knitting layer is utilized to engage, thus, the coefficient of thermal expansion due to semiconductor device part and knitting layer difference and when being applied with thermal stress, thermal stress is relaxed by the 1st knitting layer with large voidage, therefore, it is possible to suppress semiconductor device part to be destroyed.Thus, the manufacture method of such semiconductor device can be provided: the stripping of knitting layer near the peripheral part that can suppress part and the generation in crack, and the situation that when can suppress the difference at the coefficient of thermal expansion because of part and knitting layer and be applied with thermal stress, part is destroyed.
Invention effect
As mentioned above, the stripping of knitting layer near the peripheral part that can suppress part and the generation in crack, and the situation that when can suppress the difference at the coefficient of thermal expansion because of part and knitting layer and be applied with thermal stress, part is destroyed.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of 3 phase inverters of an execution mode.
Fig. 2 is the vertical view of the semiconductor element illustrated on the conductive component being configured in an execution mode.
Fig. 3 is the cutaway view along the 200-200 line in Fig. 2.
Fig. 4 is the SEM image of an example of the knitting layer of the 3 phase inverters that an execution mode is shown.
Fig. 5 is the cutaway view for illustration of the operation forming pattern electrode on the semiconductor wafer of an execution mode.
Fig. 6 is the cutaway view of the operation for illustration of the groove portion forming substantially V-like shape on the semiconductor wafer of an execution mode.
Fig. 7 is the cutaway view for illustration of the operation forming metal level on the semiconductor wafer of an execution mode.
Fig. 8 is the cutaway view of the cutting action of semiconductor wafer for illustration of an execution mode.
Fig. 9 is the figure of the semiconductor element that an execution mode is shown.
Figure 10 is the cutaway view of the operation of the 1st metal layer of paste for illustration of a formation execution mode.
Figure 11 is the cutaway view for illustration of the operation be configured in by semiconductor element in the 1st metal layer of paste of an execution mode.
Figure 12 is the cutaway view of the operation of the 1st knitting layer for illustration of a formation execution mode.
Figure 13 is the cutaway view of the operation of the 2nd metal layer of paste for illustration of a formation execution mode.
Figure 14 is the vertical view of the semiconductor element illustrated on the conductive component being configured in the 1st variation.
Figure 15 is the vertical view of the columnar electrode illustrated on the conductive component being configured in the 2nd variation.
Embodiment
Below, based on accompanying drawing, execution mode is described.
First, with reference to Fig. 1, the structure with the 3 phase inverters 100 of power model 100a, 100b and 100c of the 1st execution mode is described.Power model 100a ~ 100c and 3 phase inverters 100 are examples of " semiconductor device " and " power inverter ".
As shown in Figure 1,3 power models 100a, 100b and 100c of the electric power conversion carrying out U phase, V phase and W phase are respectively electrically connected and form by 3 phase inverters 100 in parallel.
Power model 100a, 100b and 100c are configured to be converted to 3 phases (U phase, V phase and W phase) alternating electromotive force by from DC power supply (not shown) via the direct current power that input terminal P and N inputs respectively.Further, power model 100a, 100b and 100c is configured to export the alternating electromotive force of the U phase changed as described above, V phase and W phase to outside via lead-out terminal U, V and W respectively.Further, lead-out terminal U, V, W is connected with motor (not shown) etc.
Power model 100a comprises 2 thyristor 1a and 2a.Thyristor 1a (2a) has 3 electrodes (grid G 1a (G2a), source S 1a (S2a) and drain D 1a (D2a)).In addition, thyristor 1a and 2a is such as made up of SiC device, GaN device, Si device (MOSFET (field-effect transistor), IGBT (igbt) or bipolar transistor etc.) etc.Further, thyristor 1a and 2a is an example of " semiconductor device part ", " semiconductor element " and " power inverter part ".
Thyristor 1a and 2a is configured to carry out switch motion based on the control signal inputted from outside via control terminal 3a and 4a respectively, thus, the direct current power inputted via input terminal P and N is converted to the alternating electromotive force of U phase, exports outside to via lead-out terminal U.
The drain D 1a of thyristor 1a is connected with input terminal P, and grid G 1a is connected with control terminal 3a.In addition, the source S 1a of thyristor 1a is connected with the drain D 2a of lead-out terminal U, thyristor 2a.
The drain D 2a of thyristor 2a is connected with lead-out terminal U, and grid G 2a is connected with control terminal 4a.In addition, the source S 2a of thyristor 2a is connected with input terminal N.
In addition, identical with above-mentioned power model 100a, power model 100b also comprises 2 thyristor 1b and 2b.Thyristor 1b (2b) has 3 electrodes (grid G 1b (G2b), source S 1b (S2b) and drain D 1b (D2b)).Further, thyristor 1b and 2b is an example of " semiconductor device part ", " semiconductor element " and " power inverter part ".
Thyristor 1b and 2b is configured to carry out switch motion based on the control signal inputted from outside via control terminal 3b and 4b respectively, thus, the direct current power inputted via input terminal P and N is converted to the alternating electromotive force of V phase, exports outside to via lead-out terminal V.
In addition, identical with above-mentioned power model 100a with 100b, power model 100c also comprises 2 thyristor 1c and 2c.Thyristor 1c (2c) has 3 electrodes (grid G 1c (G2c), source S 1c (S2c) and drain D 1c (D2c)).Further, thyristor 1c and 2c is an example of " semiconductor device part ", " semiconductor element " and " power inverter part ".
Thyristor 1c and 2c is configured to carry out switch based on the control signal inputted from outside via control terminal 3c and 4c respectively, thus, the direct current power inputted via input terminal P and N is converted to the alternating electromotive force of W phase, exports outside to via lead-out terminal W.
Next, with reference to Fig. 2 ~ Fig. 4, the semiconductor element 10 of 3 phase inverters 100 (power model 100a, 100b and 100c) of present embodiment is described with the connected structure of conductive component 20.Further, semiconductor element 10 is the power inverter parts of thyristor 1a and 2a (1b and 2b, 1c and 2c) comprising power model 100a (100b, 100c).In addition, semiconductor element 10 is examples of " semiconductor device part " and " power inverter part ".
As shown in Figures 2 and 3, semiconductor element 10 is configured on conductive component 20.In addition, semiconductor element 10 and conductive component 20 are engaged by the knitting layer (the 1st knitting layer 16 and the 2nd knitting layer 17) be configured between semiconductor element 10 with conductive component 20.Further, conductive component 20 can be arranged on not shown substrate as conductive pattern, also can arrange as the terminal electrode on not shown electronic component or joint electrode.
As shown in Figure 2, semiconductor element 10 (when observing from Z-direction) when overlooking is formed as rectangular shape.In addition, as shown in Figure 3, semiconductor element 10 comprises element portion 11, terminal electrode 12, joint electrode 13, metal level 14 and chamfered section 15.Element portion 11 is such as made up of the semi-conducting material containing SiC, GaN, Si etc.
Terminal electrode 12 is arranged on the upper surface (surface of side, Z2 direction) of element portion 11.Terminal electrode 12 such as has drain electrode, source electrode or grid etc.Joint electrode 13 is arranged on the lower surface (surface of side, Z1 direction) of element portion 11.In addition, joint electrode 13 is arranged to engage with conductive component 20 via metal level 14.
Metal level 14 is formed on the surface of conductive component 20 side (side, Z1 direction) beyond the surface of chamfered section 15 and chamfered section 15.That is, metal level 14 is formed as covering the lower surface (surface of side, Z1 direction) of joint electrode 13 and the surface of chamfered section 15.In addition, metal level 14 is arranged to engage with conductive component 20.
As shown in Figure 3, chamfered section 15 is arranged on the end of conductive component 20 side (side, Z1 direction) of element portion 11 (semiconductor element 10).Specifically, chamfered section 15 is arranged to all shapes along 4 limits comprising 4 angles of conductive component 20 side (side, Z1 direction) of the semiconductor element 10 of rectangular shape.In addition, chamfered section 15 has the tabular surface of inclination, and the tabular surface of this inclination has the angle of regulation relative to the lower surface (surface of side, Z1 direction) of element portion 11.
At this, in the present embodiment, as shown in Figures 2 and 3, the knitting layer making semiconductor element 10 and conductive component 20 engage comprises the 1st knitting layer 16 and the 2nd knitting layer 17.As shown in Figure 2, when top view (from Z-direction observe), the 1st knitting layer 16 configure than semiconductor element 10 outer rim in the inner part.2nd knitting layer 17 is configured in the outside of the 1st knitting layer 16.In addition, when overlooking, the 2nd knitting layer 17 is configured near the end of semiconductor element 10.
Specifically, as shown in Figure 3, the 1st knitting layer 16 be configured than semiconductor element 10 chamfered section 15 in the inner part.In addition, the 2nd knitting layer 17 is configured to be connected (joint) with the 1st knitting layer 16 of the inner side being configured in chamfered section 15 and chamfered section 15 both sides.In other words, the 1st knitting layer 16 is connected (joint) via the surface of metal level 14 with conductive component 20 side (side, Z1 direction) beyond the chamfered section 15 of semiconductor element 10.In addition, the 2nd knitting layer 17 is connected (joint) with the chamfered section 15 of semiconductor element 10 via metal level 14.
As shown in Figure 2, when top view, the area of plane of the 2nd knitting layer 17 is less than the area of plane of the 1st knitting layer 16.In addition, as shown in Figure 3, the maximum ga(u)ge h2 of the 2nd knitting layer 17 is larger than the maximum ga(u)ge h1 of the 1st knitting layer 16.That is, the 2nd knitting layer 17 is connected (joint) with chamfered section 15, and therefore, correspondingly, maximum ga(u)ge is larger.
In addition, as shown in Figures 2 and 3, the 2nd knitting layer 17 is that all shapes are connected (joint) with semiconductor element 10 along the 4 articles of limits comprising 4 angles of the semiconductor element 10 of rectangular shape.
In addition, in the present embodiment, as shown in Figure 4, the voidage of the 2nd knitting layer 17 is less than the voidage of the 1st knitting layer 16.That is, the 1st knitting layer 16 is states of porous (voidage is large), and the 2nd knitting layer 17 is the states of fine and close (voidage is little).Specifically, the voidage of the 1st knitting layer 16 more than 10% and the voidage of the less than 30%, 2nd knitting layer 17 below 1%.And, such as, as shown in Figure 4, according to SEM (scanning electron microscope) image, the area of the area being revealed as the metallic member of white of trying to achieve the per unit area of SEM image and the gap being revealed as black, by calculating the voidage obtaining knitting layer.
In addition, in the present embodiment, the 1st knitting layer 16 and the 2nd knitting layer 17 are formed by the metal material containing mutually the same metal.Specifically, the 1st knitting layer 16 and the 2nd knitting layer 17 are formed by the metal material mainly containing Ag respectively.
In addition, the 2nd knitting layer 17 is formed by the metal material comprising metallic, the average grain diameter of the metallic that the metal material that the average grain diameter of this metallic is less than formation the 1st knitting layer 16 comprises.Such as, the 1st knitting layer 16 is formed by the metal material of the Ag particle mainly containing sub-micron (such as 100nm ~ 600nm) size.In addition, such as, the 2nd knitting layer 17 is formed by the metal material of the Ag particle of the size mainly containing below 50nm.
Next, with reference to Fig. 3 and Fig. 5 ~ Figure 13, the manufacture method of 3 phase inverters 100 (power model 100a, 100b and 100c) of present embodiment is described.
The manufacture method of 3 phase inverters 100 (power model 100a, 100b and 100c) possesses: the operation forming semiconductor element 10; Conductive component 20 is formed the operation of the 1st metal layer of paste 16a; The operation of configuring semiconductor element 10; Form the operation of the 1st knitting layer 16; Form the operation of the 2nd metal layer of paste 17a; And form the operation of the 2nd knitting layer 17.
The operation forming semiconductor element 10 comprises: the operation forming terminal electrode 12 and electrode layer 13a on semiconductor wafer 11a; A surface of semiconductor wafer 11a is formed the operation with the groove portion 15a in the cross section of substantially V-like shape; With what cover semiconductor wafer 11a, there is the operation that the surperficial mode of of groove portion 15a forms metal level 14a; And the operation of cutting semiconductor chip 11a.
Semiconductor wafer 11a is formed in the operation of terminal electrode 12 and electrode layer 13a, as shown in Figure 5, form the multiple terminal electrodes 12 corresponding with semiconductor element 10 at the upper surface (surface of side, Z2 direction) of semiconductor wafer 11a.In addition, electrode layer 13a is formed at the lower surface (surface of side, Z1 direction) of semiconductor wafer 11a.
A surface of semiconductor wafer 11a is formed to be had in the operation of groove portion 15a in the cross section of substantially V-like shape, as shown in Figure 6, the lower surface (surface of Z1 direction side) of the cutting tool of V-shaped to semiconductor wafer 11a is utilized to carry out hemisection, thus, semiconductor wafer 11a forms groove portion 15a.In addition, electrode layer 13a is split by groove portion 15a, forms multiple joint electrode 13.
Being formed in the operation of metal level 14a in the mode having of groove portion 15a surperficial covering semiconductor wafer 11a, as shown in Figure 7, sputtering method is utilized to form metal level 14a at the lower surface (surface of side, Z1 direction) of semiconductor wafer 11a.In addition, metal level 14a is formed as groove portion 15a and the joint electrode 13 of the lower surface (surface of side, Z1 direction) covering semiconductor wafer 11a.
In the operation of cutting semiconductor chip 11a, as shown in Figure 8, semiconductor wafer 11a is split (cutting) by along groove portion 15a, thus, form multiple semiconductor element 10 (with reference to Fig. 9), this semiconductor element 10 has chamfered section 15 in end, and has the metal level 14 covered the surface of the side being provided with chamfered section 15 (side, Z1 direction).
Conductive component 20 is formed in the operation of the 1st metal layer of paste 16a, as shown in Figure 10, the surface of the Z2 side of conductive component 20 applies the 1st metal layer of paste 16a in the mode less than the area of plane of semiconductor element 10.In addition, the 1st metal layer of paste 16a be scattered in organic solvent by the metallic made using the Ag particle of submicron-scale as principal component state under creamy material formed.
In the operation of configuring semiconductor element 10, as shown in figure 11, semiconductor element 10 is configured in side, Z2 direction in the mode covering the 1st metal layer of paste 16a.In the operation of formation the 1st knitting layer 16, as shown in figure 12, the 1st metal layer of paste 16a is heat-treated, thus, form the 1st knitting layer 16 that conductive component 20 and semiconductor element 10 are engaged.Such as, by heating 1 hour at 200 DEG C, thus, make organic solvent gasify and come out from the 1st metal layer of paste 16a, form the 1st knitting layer 16 be made up of metal (Ag).
In addition, in the present embodiment, in the operation of formation the 2nd metal layer of paste 17a, as shown in figure 13, near the end of semiconductor element 10, form the 2nd metal layer of paste 17a, the 2nd metal layer of paste 17a comprise the metallic with the average grain diameter less than the 1st metal layer of paste 16a.Specifically, utilize distributing nozzle (not shown) to the material supplying paste between semiconductor element 10 and conductive component 20, form the 2nd metal layer of paste 17a.In addition, the 2nd metal layer of paste 17a be scattered in organic solvent by the metallic made using the Ag particle of nano-scale as principal component state under creamy material formed.
In the operation of formation the 2nd knitting layer 17, by heat-treating the 2nd metal layer of paste 17a, form the 2nd knitting layer 17 thus, as shown in Figure 3,2nd knitting layer 17 makes conductive component 20 engage with near the end of semiconductor element 10, and has the voidage less than the 1st knitting layer 16.Such as, by heating 1 hour at 200 DEG C, making organic solvent gasify and come out from the 2nd metal layer of paste 17a, forming the 2nd knitting layer 17 be made up of metal (Ag).
In the present embodiment, as mentioned above, by arranging knitting layer, outside is engaged by the 2nd knitting layer 17 with the voidage less than the 1st knitting layer 16, therefore, by the 2nd knitting layer with little voidage that interionic adhesion is stronger, the stripping of the knitting layer near the peripheral part that can suppress semiconductor element 10 and crack (be full of cracks), wherein, configure than outer rim the 1st knitting layer 16 in the inner part of semiconductor element 10 when described knitting layer is included in and overlooks (observing from Z-direction), there is the 2nd knitting layer 17 of the voidage less than the 1st knitting layer 16 with the outside being configured in the 1st knitting layer 16.In addition, the inner side with the 1st knitting layer 16 pairs of semiconductor elements 10 of the voidage larger than the 2nd knitting layer 17 is utilized to engage, thus, when being applied with thermal stress due to semiconductor element 10 and the difference of the coefficient of thermal expansion of knitting layer, thermal stress is relaxed compared with the 1st knitting layer 16 of large porosity by having, therefore, it is possible to suppress semiconductor element 10 to be destroyed.Thereby, it is possible to the stripping of knitting layer near the peripheral part suppressing semiconductor element 10 and crack, and, the situation that semiconductor element 10 is destroyed when being applied with thermal stress due to semiconductor element 10 and the difference of the coefficient of thermal expansion of knitting layer can be suppressed.
In addition, in the present embodiment, as mentioned above, by the 2nd knitting layer 17 is connected with near the end of semiconductor element 10, connect near the end of the semiconductor element 10 that the 2nd knitting layer 17 pairs of thermal stress with the voidage less than the 1st knitting layer 16 can be utilized to concentrate, therefore, it is possible to the stripping of knitting layer near the peripheral part effectively suppressing semiconductor element 10 and crack (be full of cracks).
In addition, in the present embodiment, as mentioned above, the metal material containing mutually the same metal is utilized to form the 1st knitting layer 16 and the 2nd knitting layer 17, the difference of the coefficient of thermal expansion of the 1st knitting layer 16 and the 2nd knitting layer 17 can be suppressed thus to become large, therefore, it is possible to suppress the 1st knitting layer 16 to be separated with the 2nd knitting layer 17.
In addition, in the present embodiment, as mentioned above, by the 2nd knitting layer 17 is connected with the chamfered section 15 of semiconductor element 10, compared with there is no the situation of chamfered section 15, the connection area of the 2nd knitting layer 17 and semiconductor element 10 can be increased, therefore, it is possible to the bond strength of the conductive component 20 improved based on the 2nd knitting layer 17 and semiconductor element 10.
In addition, in the present embodiment, as mentioned above, when overlooking (observing from Z-direction), 1st knitting layer 16 is configured than semiconductor element 10 chamfered section 15 in the inner part, the 2nd knitting layer 17 is connected with the 1st knitting layer 16 of inner side and chamfered section 15 both sides being configured in chamfered section 15.Thereby, it is possible to the 2nd knitting layer 17 with little voidage is seamlessly configured at the 1st knitting layer 16, therefore, it is possible to effectively suppress stripping and crack (be full of cracks) of the 1st knitting layer 16.
In addition, in the present embodiment, as mentioned above, 1st knitting layer 16 is connected via the surface of metal level 14 with conductive component 20 side (side, Z1 direction) beyond the chamfered section 15 of semiconductor element 10, and the 2nd knitting layer 17 is connected with the chamfered section 15 of semiconductor element 10 via metal level 14.Thereby, it is possible to the 2nd knitting layer 17 is connected with chamfered section 15 via metal level 14, therefore, it is possible to more reliably the 2nd metal level 17 is connected with chamfered section 15.
In addition, in the present embodiment, as mentioned above, by the maximum ga(u)ge h1 making the maximum ga(u)ge h2 of the 2nd knitting layer 17 be greater than the 1st knitting layer 16, the 2nd knitting layer 17 length in a thickness direction with little voidage can be increased, thus the connection area of the 2nd knitting layer 17 and semiconductor element 10 can be increased.Thereby, it is possible to improve based on the 2nd knitting layer 17, the bond strength of conductive component 20 and semiconductor element 10.
In addition, in the present embodiment, as mentioned above, when overlooking (observing from Z-direction), making semiconductor element 10 be formed as rectangular shape, and four angles of the 2nd knitting layer 17 with the semiconductor element 10 of rectangular shape are connected.Thereby, it is possible to utilize the 2nd knitting layer 17 with little voidage to connect four angles of the semiconductor element 10 of the most concentrated rectangular shape of thermal stress, therefore, it is possible to the stripping of knitting layer near the peripheral part effectively suppressing semiconductor element 10 and crack.
In addition, in the present embodiment, as mentioned above, 4 limits along the face of conductive component 20 side (side, Z1 direction) of the semiconductor element 10 of rectangular shape are that all shapes arrange chamfered section 15, further, 4 articles of limits along the semiconductor element 10 of rectangular shape are that all shapes connect the 2nd knitting layer 17.Thereby, it is possible to be that all shapes connect the 2nd knitting layer 17 and semiconductor element 10 along 4 articles of limits of rectangular shape, thus can easily improve based on the 2nd knitting layer 17, the bond strength of conductive component 20 and semiconductor element 10.
In addition, in the present embodiment, as mentioned above, when overlooking (observing from Z-direction), the area of plane of the 2nd knitting layer 17 is made to be less than the area of plane of the 1st knitting layer 16.Thus, can suppress the densification that bond strength is larger (voidage is little) the 2nd knitting layer 17 becomes greatly with the connection area of semiconductor element 10, therefore, it is possible to easily suppress to cause because of the difference of the coefficient of thermal expansion of the 2nd little knitting layer 17 of voidage and semiconductor element 10 situation that semiconductor element 10 is destroyed.
In addition, in the present embodiment, as mentioned above, utilize the metal material containing Ag to form the 1st knitting layer 16 and the 2nd knitting layer 17 respectively, thermal endurance and the adhesion of knitting layer can be improved thus.
In addition, in the present embodiment, as mentioned above, the voidage of the 1st knitting layer 16 is set in more than 10% and less than 30%, the voidage of the 2nd knitting layer 17 is set as less than 1%.Thereby, it is possible to guarantee the bond strength of semiconductor element 10 and knitting layer, and, more reliably can suppress the situation that semiconductor element 10 is destroyed when being applied with thermal stress due to semiconductor element 10 and the difference of the coefficient of thermal expansion of knitting layer.
In addition, in the present embodiment, as mentioned above, the 2nd knitting layer 17 is formed by the metal material comprising metallic, the average grain diameter of the metallic that the metal material that the average grain diameter of this metallic is less than formation the 1st knitting layer 16 comprises.Thereby, it is possible to easily make the voidage of the 2nd knitting layer 17 be less than the voidage of the 1st knitting layer 16.
Further, execution mode of disclosure is example in all respects, should not be considered limiting content.Scope of the present invention is illustrated by claim, instead of is illustrated by the explanation of above-mentioned execution mode, in addition, is also included in all changes in the meaning and scope that are equal to claim.
Such as, in the above-described embodiment, as an example of power inverter, show 3 phase inverters, but also can be the power inverter beyond 3 phase inverters.In addition, as an example of semiconductor device, show 3 phase inverters, but also can be the semiconductor device beyond 3 phase inverters.
In addition, in the above-described embodiment, the semiconductor device shown along rectangular shape is the structure that all shapes connect the 2nd knitting layer with 4 articles of limits of part (semiconductor element), but, as long as the 2nd knitting layer 27 is connected with at least 4 angles of part (semiconductor element) with the semiconductor device of rectangular shape by the 1st variation as shown in figure 14 like that.In this case, the chamfered section of semiconductor device part is at least arranged on 4 angles.
In addition, in the above-described embodiment, as semiconductor device part and power inverter part, show the example using semiconductor element, but semiconductor device part and power inverter part also can be the parts beyond semiconductor element.Such as, the 2nd variation as shown in figure 15, semiconductor device part and power inverter part can be the such parts of the columnar electrode 30 be configured on conductive component 20.In this case, if by the 1st knitting layer 31 and the outside being configured in the 1st knitting layer 31 and the 2nd knitting layer 32 with the voidage less than the 1st knitting layer 31 conductive component 20 and columnar electrode 30 are carried out engaging.
In addition, in the above-described embodiment, the structure that the 1st knitting layer and the 2nd knitting layer are formed by the metal material containing Ag is shown, as long as the 1st knitting layer and the 2nd knitting layer are formed by the metal material containing at least one in Au, Ag and Cu.In addition, also can be formed by other metal materials or nonmetallic materials not containing Au, Ag or Cu.
In addition, in the above-described embodiment, show such example: the chamfered section of semiconductor device part (semiconductor element) is formed as having the tabular surface of inclination, the tabular surface of this inclination has the angle of regulation relative to the lower surface of semiconductor element, but, as long as chamfered section has the circular arc chamfering of curved surface.
In addition, in the above-described embodiment, the voidage showing the 1st knitting layer is more than 10% and the example of the structure of voidage below 1% of the less than 30%, the 2nd knitting layer, but, as long as the voidage of the 2nd knitting layer is less than the voidage of the 1st knitting layer, then the voidage of the 1st knitting layer and the voidage of the 2nd knitting layer also can be other ratios.
In addition, in the above-described embodiment, show the structure that the operation forming semiconductor element comprises the operation forming electrode layer 13a, but the operation forming semiconductor element also can not comprise the operation forming electrode layer 13a.In this case, behind formation groove portion, form metal level 14a in the mode having of groove portion surperficial covering semiconductor wafer, thus, even if be not pre-formed electrode layer 13a, metal level 14a also can double as electrode layer 13a.
Label declaration
1a, 1b, 1c, 2a, 2b, 2c: thyristor (semiconductor device part, semiconductor element, power inverter part);
10: semiconductor element (semiconductor device part, power inverter part);
14: metal level;
15: chamfered section;
16,31: the 1 knitting layers (knitting layer);
16a: the 1 metal layer of paste;
17,27,32: the 2 knitting layers (knitting layer);
17a: the 2 metal layer of paste;
20: conductive component;
30: columnar electrode (semiconductor device part, power inverter part);
100:3 phase inverter (semiconductor device, power inverter);
100a, 100b, 100c: power model (semiconductor device, power inverter).

Claims (18)

1. a semiconductor device, it possesses:
Conductive component (20);
Semiconductor device is with part (1a ~ 1c, 2a ~ 2c, 10,30), and it is configured on described conductive component; And
Knitting layer, it is configured between described conductive component and described semiconductor device part, described conductive component and described semiconductor device part is engaged,
Described knitting layer comprises:
1st knitting layer (16,31), its configure when overlooking than described semiconductor device part outer rim in the inner part; With
2nd knitting layer (17,27,32), it is configured in the outside of described 1st knitting layer, and has the voidage less than described 1st knitting layer.
2. semiconductor device according to claim 1, wherein,
Described 2nd knitting layer is connected with near the end of part with described semiconductor device.
3. semiconductor device according to claim 1 and 2, wherein,
Described 1st knitting layer and described 2nd knitting layer are formed by the metal material containing mutually the same metal.
4. the semiconductor device according to any one in claims 1 to 3, wherein,
Described semiconductor device part has the chamfered section (15) of the end in the face being arranged on described conductive component side,
Described 2nd knitting layer is connected with the described chamfered section of described semiconductor device with part.
5. semiconductor device according to claim 4, wherein,
Described 1st knitting layer configure when overlooking than described semiconductor device part chamfered section in the inner part,
Described 2nd knitting layer is connected with described 1st knitting layer of inner side and described chamfered section both sides being configured in described chamfered section.
6. the semiconductor device according to claim 4 or 5, wherein,
Described semiconductor device part comprises semiconductor element (1a ~ 1c, 2a ~ 2c, 10), and there is the metal level (14) that the surface of the described conductive component side beyond the surface and described chamfered section of the described chamfered section of described semiconductor element is formed
Described 1st knitting layer is connected via the surface of described metal level with the described conductive component side beyond the described chamfered section of described semiconductor element,
Described 2nd knitting layer is connected with the described chamfered section of described semiconductor element via described metal level.
7. the semiconductor device according to any one in claim 4 ~ 6, wherein,
The maximum ga(u)ge of described 2nd knitting layer is greater than the maximum ga(u)ge of described 1st knitting layer.
8. the semiconductor device according to any one in claim 1 ~ 7, wherein,
Described semiconductor device part is formed as rectangular shape when overlooking,
Described 2nd knitting layer is connected with at least 4 angles of part with the described semiconductor device of rectangular shape.
9. semiconductor device according to claim 8, wherein,
The semiconductor device part of described rectangular shape comprises the chamfered section at least 4 angles in the face being arranged on described conductive component side.
10. semiconductor device according to claim 8 or claim 9, wherein,
Described 2nd knitting layer is that all shapes connect along the semiconductor device of described rectangular shape with 4 articles of limits of part.
11. semiconductor devices according to any one in claim 1 ~ 10, wherein,
When overlooking, the area of plane of described 2nd knitting layer is less than the area of plane of described 1st knitting layer.
12. semiconductor devices according to any one in claim 1 ~ 11, wherein,
Described 1st knitting layer and described 2nd knitting layer are formed by the metal material containing at least one in Au, Ag or Cu respectively.
13. semiconductor devices according to any one in claim 1 ~ 12, wherein,
The voidage of described 1st knitting layer more than 10% and less than 30%,
The voidage of described 2nd knitting layer is below 1%.
14. semiconductor devices according to any one in claim 1 ~ 13, wherein,
Described 2nd knitting layer is formed by the metal material comprising metallic, and wherein the average grain diameter of this metallic is less than the average grain diameter of the metallic that the metal material that forms described 1st knitting layer comprises.
15. 1 kinds of power inverters, it comprises:
Conductive component (20);
Power inverter is with part (1a ~ 1c, 2a ~ 2c, 10,30), and it is configured on described conductive component; And
Knitting layer, it is configured between described conductive component and described power inverter part, is engaged by described conductive component with described power inverter part,
Described knitting layer comprises:
1st knitting layer (16,31), its configure when overlooking than described power inverter part outer rim in the inner part; With
2nd knitting layer (17,27,32), it is configured in the outside of described 1st knitting layer, and has the voidage less than described 1st knitting layer.
The manufacture method of 16. 1 kinds of semiconductor devices, it comprises:
In the operation of the upper formation the 1st metal layer of paste (16a) of conductive component (20);
To cover the operation of the mode configuring semiconductor device part (1a ~ 1c, 2a ~ 2c, 10,30) of described 1st metal layer of paste;
By heat-treating the operation forming the 1st knitting layer (16,31) engaged with described semiconductor device part by described conductive component to described 1st metal layer of paste;
Near the end of described semiconductor device part, form the operation of the 2nd metal layer of paste (17a), the 2nd metal layer of paste (17a) comprises the average grain diameter metallic less than the average grain diameter of described 1st metal layer of paste; And
By heat-treating to described 2nd metal layer of paste the operation forming the 2nd knitting layer (17,27,32), described 2nd knitting layer (17,27,32) engages near the end of described conductive component and described semiconductor device part, and has the voidage less than described 1st knitting layer.
The manufacture method of 17. semiconductor devices according to claim 16, wherein,
The manufacture method of described semiconductor device is also included in the operation of end formation chamfered section (15) in the face of the described conductive component side of described semiconductor device part,
The operation forming described 2nd knitting layer comprises to form the operation of described 2nd knitting layer by the mode that the described chamfered section of part is connected with described semiconductor device.
The manufacture method of 18. semiconductor devices according to claim 16 or 17, wherein,
The operation forming described 2nd knitting layer comprises to form the operation of described 2nd knitting layer by the mode that at least 4 angles of part are connected with the described semiconductor device of rectangular shape.
CN201380074724.4A 2013-03-28 2013-03-28 Semiconductor device, power conversion device and semiconductor device manufacturing method Pending CN105190856A (en)

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