WO2020055244A1 - Seed layer for electroplating eutectic ausn solder - Google Patents

Seed layer for electroplating eutectic ausn solder Download PDF

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Publication number
WO2020055244A1
WO2020055244A1 PCT/NL2019/050586 NL2019050586W WO2020055244A1 WO 2020055244 A1 WO2020055244 A1 WO 2020055244A1 NL 2019050586 W NL2019050586 W NL 2019050586W WO 2020055244 A1 WO2020055244 A1 WO 2020055244A1
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WIPO (PCT)
Prior art keywords
layer
semiconductor
substrate
package substrate
die
Prior art date
Application number
PCT/NL2019/050586
Other languages
French (fr)
Inventor
Sandra KITS
Johannes Wilhelmus Van Rijckevorsel
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Ampleon Netherlands B.V.
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Publication date
Application filed by Ampleon Netherlands B.V. filed Critical Ampleon Netherlands B.V.
Publication of WO2020055244A1 publication Critical patent/WO2020055244A1/en

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Definitions

  • the present invention relates to a semiconductor assembly comprising a semiconductor die and a package substrate onto which the semiconductor die is to be attached using an eutectic Gold Tin (AuSn) alloy solder layer.
  • the invention further relates to a packaged radiofrequency‘RF’ amplifier that comprises this semiconductor assembly. Furthermore, the invention relates to a method for manufacturing the packaged RF amplifier.
  • RADAR transmit amplifiers or solid-state cooking power amplifiers.
  • high power devices are Silicon-based LDMOS amplifiers or Gallium Nitride based amplifiers.
  • a Doherty configuration is often used.
  • the high power devices typically comprise a package having a package substrate and a plurality of leads spaced apart from the package substrate.
  • the power amplifying element in the form of a semiconductor die on which a power transistor, such as a field-effect transistor‘FET’ is realized, is mounted on the package substrate.
  • the terminals of the FET, or the circuitry in which it is used, are connected to respective leads to allow signals to be fed to and extract from the package.
  • thermal conductivity of the package substrate should be as high as possible. Copper (Cu) substrates or Cu-based substrates are therefore used more often nowadays despite the apparent mismatch in thermal expansion coefficient between the Cu substrate and the semiconductor die.
  • an eutectic die-attach process uses an eutectic Gold-Tin (AuSn) alloy solder layer.
  • the solder layer has a particular ratio between Au and Sn such as 80/20 wt%.
  • This layer is electroplated onto the semiconductor die.
  • the semiconductor die is pressed onto the Cu substrate simultaneous with the application of heat sufficient for melting the solder layer.
  • the AuSn will solidify and provide a strong bond between the semiconductor die and the Cu substrate.
  • the eutectic AuSn alloy solder layer cannot be applied on the semiconductor die directly. Firstly, a metal seed layer is required for the electroplating process. Secondly, during die-attach, the molten AuSn layer may partially dissolve the semiconductor die causing excessive formation of Silicon oxides, such as Si0 2 , around the semiconductor die.
  • Figure 1 illustrates an example of the formation of Silicon oxides due to the reaction of the AuSn layer with the Silicon semiconductor substrate.
  • the AuSn layer creeps from underneath the semiconductor die 110.
  • part 100 consists, at least in a large part, of the AuSn solder layer. This layer is covered by a Silicon oxide that was formed as a result of the interaction between the AuSn solder layer and the Silicon semiconductor substrate.
  • seed layer One of the intended purposes of this seed layer is to prevent the migration of the AuSn layer towards the semiconductor die.
  • Most high power amplifiers have a single-ended configuration in which the source of the FET should be grounded via a low inductance and low resistance path to ground.
  • Most semiconductor dies therefore comprise a conductive semiconductor substrate.
  • a low resistance connection can then be obtained via the semiconductor substrate and the grounded package substrate.
  • An important part of the low resistance connection is formed by the contact resistance associated with the connection between the semiconductor substrate and the abovementioned seed layer.
  • US 9,324,674 discloses a seed layer comprising, starting from the backside of the semiconductor substrate, a first layer of Gold (Au), a second layer of Silver (Ag), a third layer of Nickel (Ni), and a fourth layer of Au onto which the AuSn will be arranged.
  • the Ni layer provides a barrier to the AuSn layer and limits the formation of Silicon oxides.
  • an additional fifth relatively thick Ni layer in between the AuSn and the fourth Au layer.
  • This fifth layer as well as the AuSn layer are arranged using electroplating techniques.
  • the thickness of this electroplated Ni layer is approximately 1 micrometer and the thickness of the AuSn layer varies between 3 and 5 micrometers.
  • An object of the present invention is to provide a seed layer in which the abovementioned problem does not or hardly occur.
  • this object is achieved with a semiconductor assembly as defined in claim 1 , which comprises a semiconductor die and a package substrate.
  • semiconductor die comprises a semiconductor substrate, a seed layer arranged on a backside of the semiconductor substrate, and an electroplated eutectic AuSn alloy solder layer arranged on the seed layer.
  • the semiconductor die is to be attached on the package substrate using the eutectic AuSn alloy solder layer.
  • the semiconductor assembly is characterized in that the seed layer comprises a first layer of Aluminum (Al) contacting the backside of the semiconductor substrate, and a second layer of Ni contacting the first layer.
  • Al Aluminum
  • Ni nickel
  • the Applicant has found that the relatively thick Ni layer used in the prior art causes burring to occur when the individual semiconductor dies are separated from the semiconductor wafer by means of for example a cutting or sawing operation.
  • the semiconductor die having burred edges, is placed on the package substrate to which it is to be connected using the abovementioned die-attach process, a small separation between the backside of the semiconductor die and the substrate may occur ln some cases, this separation may be so large that the die-attach process fails or that the die-attach provides a low-strength bond.
  • the Applicant has further found that when an A1 layer is used as the first layer, the relatively thick Ni layer can be omitted without causing a considerable increase in the formation of Silicon oxides during the die-attach process. More in particular, together with a Ni layer as the second layer, a sufficiently high barrier for limiting the formation of Silicon oxides is realized. Due to the fact that the relatively thick Ni layer of the prior art can be omitted, the amount of burring can be greatly reduced, thereby improving the reliability of the die-attach process ln addition, because the formation of Silicon oxides is reduced, the temperature used during the die-attach process can be increased, thereby improving the reliability of the connection between die and the package substrate.
  • the seed layer may further comprise a third layer of Ag that contacts the second layer.
  • the third layer may constitute the outer metal layer that acts as an electrode during the electroplating process.
  • the first layer may have a thickness in the range between 100 and 600 nm, more preferably in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
  • the second layer may have a thickness in the range between 100 and 900 nm, more preferably in the range between 100 and 400 nm, more preferably between 200 and 300 nm, and even more preferably between 230 and 270 nm.
  • the third layer may have a thickness in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
  • each of the first, second, and third layer has a thickness in the range between 180 and 270 nm.
  • the first layer, the second layer, and the third layer when applicable, may each have been formed using a metal evaporation process or a sputtering process.
  • the eutectic AuSn alloy solder layer may have a thickness in the range between 1 and 8 micrometer, and more preferably between 2.5 and 5.5 micrometer.
  • the Au content in the AuSn alloy solder layer may range from 70 to 90 percent by weight, preferably from 75 to 85 percent, more preferably substantially equaling 80 percent by weight.
  • the eutectic alloy of AuSn using this latter ratio provides a melting temperature of approximately 280°C.
  • the package substrate may comprise a Copper substrate comprising more than 80 percent of Copper by weight, more preferably more than 90 percent, and even more preferably more than 98 percent.
  • the package substrate may alternatively comprise a copper plated ceramic‘CPC’ substrate or a Copper Tungsten (CuW) substrate.
  • the package substrate may comprise a package substrate body and an oxide prevention layer arranged on a top surface of the package substrate body.
  • the oxide prevention layer may for example have been applied using sputtering, evaporation, or electroplating techniques, and may comprise a Nickel Palladium Gold layer stack or a Palladium Gold layer stack.
  • An Ag pad may be arranged in between the package substrate body and the oxide prevention layer at a position where the semiconductor die is to be attached.
  • the Ag pad may function as a stress relieve layer to mitigate the difference in thermal expansion coefficient of the semiconductor die and the package substrate body. As such, the Ag pad may reduce the risk of the attachment between the semiconductor die and package substrate to weaken or break as a result of temperature changes.
  • the seed layer of the invention is particularly suitable for Silicon substrates although it may equally be used for Gallium Nitride substrates.
  • the present invention provides a packaged RF power amplifier comprising the semiconductor assembly as described above, wherein the semiconductor die has been die-attached to the package substrate using the eutectic AuSn alloy solder layer.
  • the packaged RF amplifier preferably comprises an RF power transistor arranged on the semiconductor die.
  • the packaged RF amplifier may further comprise a plurality of leads being arranged spaced apart from the package substrate, and a separation element for separating the package substrate and the plurality of leads.
  • the separation element may for example comprise a ceramic ring or a solidified and/or cured molding compound.
  • the packaged RF amplifier may further comprise a plurality of bondwires electrically connecting the RF pow'er transistor to the plurality of leads.
  • the present invention provides a method for manufacturing the packaged RF amplifier described above.
  • the method comprises the steps of: a) providing a semiconductor die having a semiconductor substrate, and b) arranging a seed layer on a backside of the semiconductor substrate.
  • Step b) comprises the steps of bl ) arranging a first layer of Aluminum (Al) on the backside of the semiconductor substrate by means of sputtering or evaporation, and b2) arranging a second layer of Nickel (Ni) on the first layer by means of sputtering or evaporation.
  • the method according to the invention further comprises c) arranging an eutectic AuSn alloy solder layer on the seed layer by means of electroplating, d) providing a package substrate, and e) die-attaching the semiconductor die to the package substrate using the eutectic AuSn alloy solder layer.
  • Step b) may further comprise b3) arranging a third layer of Silver (Ag) on the third layer by means of sputtering or evaporation.
  • the first layer, the second layer, the third layer, the semiconductor die, and/or the package substrate may be configured as defined in connection with the abovementioned semiconductor assembly.
  • FIG. 1 illustrates the formation of Silicon oxides
  • FIG. 2 illustrates a semiconductor assembly in accordance with the present invention
  • Figure 3 illustrates a packaged RF amplifier obtained using the semiconductor assembly of figure 2.
  • Figure 4 illustrates a method for manufacturing the RF amplifier of figure 3.
  • Figure 2 illustrates a semiconductor assembly in accordance with the present invention. It comprises a semiconductor die 10 and a package substrate 20.
  • Semiconductor die 10 comprises a semiconductor substrate 11, for example a Silicon substrate in which one or more integrated circuits are realized.
  • a seed layer 12 is arranged by means of evaporation or sputtering techniques.
  • Seed layer 12 comprises a first layer of A1 having a thickness in the range between 180 and 220 nm, and a second layer of Ni having a thickness in the range between 230 and 270 nm.
  • seed layer 12 comprises an additional layer that provides a suitable exposed surface for a subsequent electroplating process.
  • seed layer 12 may comprise a third layer of Ag having a thickness in the range between 180 and 220 nm.
  • the invention is however not limited to these ranges.
  • a thicker first and/or second layer may be used.
  • An eutectic AuSn alloy solder layer 13 having a thickness in the range between 1 and 8 micrometer, and having an Au substantially equaling 80 percent by weight, is electroplated onto seed layer 12.
  • Package substrate 20 comprises a package substrate body 21, for example comprising a Copper block or coin.
  • Package substrate body 21 is covered by an oxide prevention layer 22, such as a Nickel Palladium Gold metal layer stack, wherein the thicknesses of each layer are in the range between 200 and 1500 nm, 20 and 200 nm, and 1 and 20 nm, respectively.
  • a Palladium Gold metal layer stack is used, wherein the thicknesses of each layer are in the range between 50 and 800 nm, and 1 and 20 nm, respectively.
  • a stress relieve layer 23 is arranged in between package substrate body 21 and oxide prevention layer 22.
  • This relieve layer may be formed using a relatively thick layer of Ag, for example having a thickness exceeding 4 micrometer, for example between 6 and 10 micrometer, and arranged at the position where semiconductor die 10 is to be mounted.
  • Figure 3 illustrates the implementation of the assembly in figure 1 in a packaged radiofrequency‘RF’ amplifier.
  • a power transistor 32 or circuitry comprising such a transistor is realized in semiconductor die 11. Signals can be fed to or collected from transistor 32 using bondwires 33 that extend between transistor 32 and leads 30.
  • leads 30 are fixed relative to package substrate 30 in a spaced apart manner. Such separation may for example be achieved by a cera ic ring 31 as shown. Alternatively, the separation is achieved by a solidified and/or cured molding compound.
  • Figure 3 illustrates the semiconductor assembly in an assembled slate.
  • the identification of the various layers may in practice not be as clear as indicated in figure 2.
  • the heat treatments involved may cause the various layers to melt and to become mixed instead of the clear borders in between layers in figures 2 and 3.
  • the skilled person will therefore understand that these borders have an illustrational purpose only.
  • Figure 4 illustrates a method for manufacturing the semiconductor package of figure 3. As illustrated, the method comprises, as a first step, the provision (SI) of a semiconductor die having a semiconductor substrate. Next, a seed layer will be arranged (S2) on a backside of the
  • This step comprises the sub-steps of arranging (S2_J) a first layer of Aluminum on the backside of the semiconductor substrate by means of sputtering or evaporation, and arranging (S2 _ 2) a second layer of Nickel on the first layer by means of sputtering or evaporation.
  • an eutectic AuSn alloy solder layer is arranged (S3) on the seed layer by means of electroplating.
  • a package substrate is provided (S4), and a die-attach process using the eutectic AuSn alloy solder layer is performed (S5) by which the semiconductor die is connected to the package substrate.

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Abstract

The present invention relates to a packaged radiofrequency ' RF' amplifier comprising a semiconductor assembly, the semiconductor assembly comprising a semiconductor die (10) comprising a semiconductor substrate (11), a seed layer (12) arranged on a backside of the semiconductor substrate, and an electroplated eutectic AuSn alloy solder layer (13) arranged on the seed layer (12) and a package substrate (20) onto which the semiconductor is die- attached using the eutectic AuSn alloy solder layer (13). The package substrate (20) comprises a copper substrate or a copper plated ceramic 'CPC substrate or a copper tungsten (CuW) substrate. An RF power transistor (32) is arranged on the semiconductor die (10). The semiconductor substrate comprises a silicon substrate. The seed layer (12) comprises a first layer (12a) of aluminium (Al) contacting the backside of the semiconductor substrate, a second layer (12b) of nickel (Ni) contacting the first layer (12a), and a third layer (12c) of silver (Ag) contacting the second layer (12b), wherein the first layer (12a) (Al) has a thickness in the range between 100 and 400 nm, the second layer (12b) (Ni) has a thickness in the range between 100 and 400 nm and the third layer (12c) (Ag) has a thickness in the range between 100 and 400 nm. Thanks to the Al layer (12a), a thick Ni layer of the prior art can be omitted without causing a considerable increase in the formation of silicon oxides during the die-attach process. More in particular, together with a Ni layer (12b) as the second layer (12b), a sufficiently high barrier for limiting the formation of silicon oxides is realised. Thanks to the fact that the relatively thick Ni layer of the prior art can be omitted, the amount of burring upon wafer cutting can be greatly reduced, thereby improving the reliability of the die-attach process. T he AuSn alloy solder layer (13) has a thickness in the range between 1 and 8 micrometres. The package substrate (20) may comprise a package substrate body (21) and an oxide prevention layer (22) arranged on a top surface of said package substrate body (21), the oxide prevention layer (22) preferably comprising a nickel-palladium-gold layer stack or a palladium-gold layer stack. The package substrate (20) may further comprise an Ag pad (23) arranged in between the package substrate body (21) and the oxide prevention layer (22) at the position where the semiconductor die (10) is to be attached, wherein the Ag pad (23) may function as a stress relieve layer to mitigate the difference in thermal expansion coefficient of the semiconductor die (10) and the package substrate body (21).

Description

Seed layer for electroplating eutectic AuSn solder
The present invention relates to a semiconductor assembly comprising a semiconductor die and a package substrate onto which the semiconductor die is to be attached using an eutectic Gold Tin (AuSn) alloy solder layer. The invention further relates to a packaged radiofrequency‘RF’ amplifier that comprises this semiconductor assembly. Furthermore, the invention relates to a method for manufacturing the packaged RF amplifier.
In modern day RF electronics, high power devices (>50W) have become important components in applications such as base station amplifiers for mobile telecommunications,
RADAR transmit amplifiers, or solid-state cooking power amplifiers. Examples of high power devices are Silicon-based LDMOS amplifiers or Gallium Nitride based amplifiers. For these amplifiers, a Doherty configuration is often used.
The high power devices typically comprise a package having a package substrate and a plurality of leads spaced apart from the package substrate. The power amplifying element, in the form of a semiconductor die on which a power transistor, such as a field-effect transistor‘FET’ is realized, is mounted on the package substrate. The terminals of the FET, or the circuitry in which it is used, are connected to respective leads to allow signals to be fed to and extract from the package.
As the high power devices typically consume a relatively large amount of heat, thermal properties of the package are important. To this end, the thermal conductivity of the package substrate should be as high as possible. Copper (Cu) substrates or Cu-based substrates are therefore used more often nowadays despite the apparent mismatch in thermal expansion coefficient between the Cu substrate and the semiconductor die.
To mount the semiconductor die onto the Cu substrate, an eutectic die-attach process is known that uses an eutectic Gold-Tin (AuSn) alloy solder layer. The solder layer has a particular ratio between Au and Sn such as 80/20 wt%. This layer is electroplated onto the semiconductor die. During the die-attach process, the semiconductor die is pressed onto the Cu substrate simultaneous with the application of heat sufficient for melting the solder layer. Upon cooling, the AuSn will solidify and provide a strong bond between the semiconductor die and the Cu substrate.
The eutectic AuSn alloy solder layer cannot be applied on the semiconductor die directly. Firstly, a metal seed layer is required for the electroplating process. Secondly, during die-attach, the molten AuSn layer may partially dissolve the semiconductor die causing excessive formation of Silicon oxides, such as Si02, around the semiconductor die.
Figure 1 illustrates an example of the formation of Silicon oxides due to the reaction of the AuSn layer with the Silicon semiconductor substrate. As shown in figure 1, the AuSn layer creeps from underneath the semiconductor die 110. Here, part 100 consists, at least in a large part, of the AuSn solder layer. This layer is covered by a Silicon oxide that was formed as a result of the interaction between the AuSn solder layer and the Silicon semiconductor substrate.
It is known to arrange one or more metal layers in between the semiconductor die and the AuSn solder layer. Within the context of the present invention, these layers will be jointly referred to as seed layer. One of the intended purposes of this seed layer is to prevent the migration of the AuSn layer towards the semiconductor die.
Most high power amplifiers have a single-ended configuration in which the source of the FET should be grounded via a low inductance and low resistance path to ground. Most semiconductor dies therefore comprise a conductive semiconductor substrate. A low resistance connection can then be obtained via the semiconductor substrate and the grounded package substrate. An important part of the low resistance connection is formed by the contact resistance associated with the connection between the semiconductor substrate and the abovementioned seed layer.
US 9,324,674 discloses a seed layer comprising, starting from the backside of the semiconductor substrate, a first layer of Gold (Au), a second layer of Silver (Ag), a third layer of Nickel (Ni), and a fourth layer of Au onto which the AuSn will be arranged. In this layer stack, the Ni layer provides a barrier to the AuSn layer and limits the formation of Silicon oxides.
To reduce the formation of Silicon oxides even further it is known to arrange an additional fifth relatively thick Ni layer in between the AuSn and the fourth Au layer. This fifth layer as well as the AuSn layer are arranged using electroplating techniques. The thickness of this electroplated Ni layer is approximately 1 micrometer and the thickness of the AuSn layer varies between 3 and 5 micrometers.
The Applicant has found that the reliability and manufacturability of the abovementioned die-attach between the semiconductor die having the additional fifth Ni layer and Copper or Copper based substrates is unsatisfactory
An object of the present invention is to provide a seed layer in which the abovementioned problem does not or hardly occur.
According to the invention, this object is achieved with a semiconductor assembly as defined in claim 1 , which comprises a semiconductor die and a package substrate. The
semiconductor die comprises a semiconductor substrate, a seed layer arranged on a backside of the semiconductor substrate, and an electroplated eutectic AuSn alloy solder layer arranged on the seed layer. The semiconductor die is to be attached on the package substrate using the eutectic AuSn alloy solder layer.
The semiconductor assembly is characterized in that the seed layer comprises a first layer of Aluminum (Al) contacting the backside of the semiconductor substrate, and a second layer of Ni contacting the first layer. The Applicant has found that the relatively thick Ni layer used in the prior art causes burring to occur when the individual semiconductor dies are separated from the semiconductor wafer by means of for example a cutting or sawing operation. When the semiconductor die, having burred edges, is placed on the package substrate to which it is to be connected using the abovementioned die-attach process, a small separation between the backside of the semiconductor die and the substrate may occur ln some cases, this separation may be so large that the die-attach process fails or that the die-attach provides a low-strength bond.
The Applicant has further found that when an A1 layer is used as the first layer, the relatively thick Ni layer can be omitted without causing a considerable increase in the formation of Silicon oxides during the die-attach process. More in particular, together with a Ni layer as the second layer, a sufficiently high barrier for limiting the formation of Silicon oxides is realized. Due to the fact that the relatively thick Ni layer of the prior art can be omitted, the amount of burring can be greatly reduced, thereby improving the reliability of the die-attach process ln addition, because the formation of Silicon oxides is reduced, the temperature used during the die-attach process can be increased, thereby improving the reliability of the connection between die and the package substrate.
The seed layer may further comprise a third layer of Ag that contacts the second layer. The third layer may constitute the outer metal layer that acts as an electrode during the electroplating process.
The first layer may have a thickness in the range between 100 and 600 nm, more preferably in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
The second layer may have a thickness in the range between 100 and 900 nm, more preferably in the range between 100 and 400 nm, more preferably between 200 and 300 nm, and even more preferably between 230 and 270 nm.
The third layer may have a thickness in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
hi an embodiment, each of the first, second, and third layer has a thickness in the range between 180 and 270 nm.
The first layer, the second layer, and the third layer when applicable, may each have been formed using a metal evaporation process or a sputtering process.
Additionally or alternatively, the eutectic AuSn alloy solder layer may have a thickness in the range between 1 and 8 micrometer, and more preferably between 2.5 and 5.5 micrometer. The Au content in the AuSn alloy solder layer may range from 70 to 90 percent by weight, preferably from 75 to 85 percent, more preferably substantially equaling 80 percent by weight. The eutectic alloy of AuSn using this latter ratio provides a melting temperature of approximately 280°C. The package substrate may comprise a Copper substrate comprising more than 80 percent of Copper by weight, more preferably more than 90 percent, and even more preferably more than 98 percent. The package substrate may alternatively comprise a copper plated ceramic‘CPC’ substrate or a Copper Tungsten (CuW) substrate.
The package substrate may comprise a package substrate body and an oxide prevention layer arranged on a top surface of the package substrate body. The oxide prevention layer may for example have been applied using sputtering, evaporation, or electroplating techniques, and may comprise a Nickel Palladium Gold layer stack or a Palladium Gold layer stack.
An Ag pad may be arranged in between the package substrate body and the oxide prevention layer at a position where the semiconductor die is to be attached. The Ag pad may function as a stress relieve layer to mitigate the difference in thermal expansion coefficient of the semiconductor die and the package substrate body. As such, the Ag pad may reduce the risk of the attachment between the semiconductor die and package substrate to weaken or break as a result of temperature changes.
The seed layer of the invention is particularly suitable for Silicon substrates although it may equally be used for Gallium Nitride substrates.
According to a further aspect, the present invention provides a packaged RF power amplifier comprising the semiconductor assembly as described above, wherein the semiconductor die has been die-attached to the package substrate using the eutectic AuSn alloy solder layer. The packaged RF amplifier preferably comprises an RF power transistor arranged on the semiconductor die.
The packaged RF amplifier may further comprise a plurality of leads being arranged spaced apart from the package substrate, and a separation element for separating the package substrate and the plurality of leads. The separation element may for example comprise a ceramic ring or a solidified and/or cured molding compound. The packaged RF amplifier may further comprise a plurality of bondwires electrically connecting the RF pow'er transistor to the plurality of leads.
According to an even further aspect, the present invention provides a method for manufacturing the packaged RF amplifier described above. The method comprises the steps of: a) providing a semiconductor die having a semiconductor substrate, and b) arranging a seed layer on a backside of the semiconductor substrate. Step b) comprises the steps of bl ) arranging a first layer of Aluminum (Al) on the backside of the semiconductor substrate by means of sputtering or evaporation, and b2) arranging a second layer of Nickel (Ni) on the first layer by means of sputtering or evaporation.
The method according to the invention further comprises c) arranging an eutectic AuSn alloy solder layer on the seed layer by means of electroplating, d) providing a package substrate, and e) die-attaching the semiconductor die to the package substrate using the eutectic AuSn alloy solder layer. Step b) may further comprise b3) arranging a third layer of Silver (Ag) on the third layer by means of sputtering or evaporation.
The first layer, the second layer, the third layer, the semiconductor die, and/or the package substrate may be configured as defined in connection with the abovementioned semiconductor assembly.
Next, the present invention will be described in more detail referring to the appended drawings, wherein:
Figure 1 illustrates the formation of Silicon oxides;
Figure 2 illustrates a semiconductor assembly in accordance with the present invention;
Figure 3 illustrates a packaged RF amplifier obtained using the semiconductor assembly of figure 2; and
Figure 4 illustrates a method for manufacturing the RF amplifier of figure 3.
Figure 2 illustrates a semiconductor assembly in accordance with the present invention. It comprises a semiconductor die 10 and a package substrate 20. Semiconductor die 10 comprises a semiconductor substrate 11, for example a Silicon substrate in which one or more integrated circuits are realized. On a backside of substrate 11, a seed layer 12 is arranged by means of evaporation or sputtering techniques. Seed layer 12 comprises a first layer of A1 having a thickness in the range between 180 and 220 nm, and a second layer of Ni having a thickness in the range between 230 and 270 nm. Preferably, seed layer 12 comprises an additional layer that provides a suitable exposed surface for a subsequent electroplating process. For example, seed layer 12 may comprise a third layer of Ag having a thickness in the range between 180 and 220 nm. The invention is however not limited to these ranges. For example, a thicker first and/or second layer may be used.
An eutectic AuSn alloy solder layer 13, having a thickness in the range between 1 and 8 micrometer, and having an Au substantially equaling 80 percent by weight, is electroplated onto seed layer 12.
Package substrate 20 comprises a package substrate body 21, for example comprising a Copper block or coin. Package substrate body 21 is covered by an oxide prevention layer 22, such as a Nickel Palladium Gold metal layer stack, wherein the thicknesses of each layer are in the range between 200 and 1500 nm, 20 and 200 nm, and 1 and 20 nm, respectively. Alternatively, a Palladium Gold metal layer stack is used, wherein the thicknesses of each layer are in the range between 50 and 800 nm, and 1 and 20 nm, respectively.
In an embodiment, a stress relieve layer 23 is arranged in between package substrate body 21 and oxide prevention layer 22. This relieve layer may be formed using a relatively thick layer of Ag, for example having a thickness exceeding 4 micrometer, for example between 6 and 10 micrometer, and arranged at the position where semiconductor die 10 is to be mounted.
Figure 3 illustrates the implementation of the assembly in figure 1 in a packaged radiofrequency‘RF’ amplifier. Here, a power transistor 32 or circuitry comprising such a transistor is realized in semiconductor die 11. Signals can be fed to or collected from transistor 32 using bondwires 33 that extend between transistor 32 and leads 30. As shown in figure 2, leads 30 are fixed relative to package substrate 30 in a spaced apart manner. Such separation may for example be achieved by a cera ic ring 31 as shown. Alternatively, the separation is achieved by a solidified and/or cured molding compound.
Figure 3 illustrates the semiconductor assembly in an assembled slate. Here, it should be noted that the identification of the various layers may in practice not be as clear as indicated in figure 2. The heat treatments involved may cause the various layers to melt and to become mixed instead of the clear borders in between layers in figures 2 and 3. The skilled person will therefore understand that these borders have an illustrational purpose only.
Figure 4 illustrates a method for manufacturing the semiconductor package of figure 3. As illustrated, the method comprises, as a first step, the provision (SI) of a semiconductor die having a semiconductor substrate. Next, a seed layer will be arranged (S2) on a backside of the
semiconductor substrate. This step comprises the sub-steps of arranging (S2_J) a first layer of Aluminum on the backside of the semiconductor substrate by means of sputtering or evaporation, and arranging (S2 _ 2) a second layer of Nickel on the first layer by means of sputtering or evaporation. Next, an eutectic AuSn alloy solder layer is arranged (S3) on the seed layer by means of electroplating. Then, a package substrate is provided (S4), and a die-attach process using the eutectic AuSn alloy solder layer is performed (S5) by which the semiconductor die is connected to the package substrate.
The present invention has been described using detailed embodiments thereof. However, it will be clear to the skilled person in the art that various modifications can be made without departing from the scope of the invention that is defined by the appended claims.

Claims

1. A packaged radiofrequency‘RF’ amplifier comprising a semiconductor assembly, the semiconductor assembly comprising:
a semiconductor die (10) comprising a semiconductor substrate (11), a seed layer (12) arranged on a backside of the semiconductor substrate, and an electroplated eutectic AuSn alloy solder layer (13) arranged on the seed layer;
a package substrate (20) onto which the semiconductor is die-attached using the eutectic AuSn alloy solder layer, wherein the package substrate comprises a Copper substrate comprising more than 80 percent of Copper by weight, more preferably more than 90 percent, and even more preferably more than 98 percent or wherein the package substrate comprises a copper plated ceramic‘CPC’ substrate or a Copper Tungsten (CuW) substrate;
wherein an RF power transistor (32) is arranged on the semiconductor die;
wherein the semiconductor substrate comprises a .Silicon substrate;
wherein the seed layer comprises a first layer (12a) of Aluminum (Al) contacting the backside of the semiconductor substrate, a second layer (12b) of Nickel (Ni) contacting the first layer, and a third layer (12c) of Silver (Ag) contacting the second layer;
wherein the first layer has a thickness in the range between 100 and 400 nm;
wherein the second layer has a thickness in the range between 100 and 400 nm;
wherein the third layer has a thickness in the range between 100 and 400 nm;
wherein the AuSn alloy solder layer has a thickness in the range between 1 and 8 micrometer, wherein the Au content in the AuSn alloy solder layer ranges from 70 to 90 percent by weight, preferably from 75 to 85 percent, more preferably substantially equaling 80 percent.
2. The semiconductor assembly according to claim 1 , wherein the third layer has a thickness in the range between 150 and 250 nm, and even more preferably between 180 and 220 nm.
3. The semiconductor assembly according to any of the previous claims, wherein the first layer has a thickness in the range between 150 and 250 nm, and even more preferably between 180 and 220 nm.
4. The semiconductor assembly according to any of the previous claims, wherein the second layer has a thickness in the range between 200 and 300 nm, and even more preferably between 230 and 270 nm.
5. The semiconductor assembly according to any of the previous claims, wherein each of the first, second, and third layer, if applicable, has a thickness in the range between 180 and 270 nm.
6. The semiconductor assembly according to any of the previous claims, wherein the first layer, the second layer, and the third layer when applicable, have each been formed using a metal evaporation process or a sputtering process.
7. The semiconductor assembly according to any of the previous claims, wherein the package substrate comprises a package substrate body (21) and an oxide prevention layer (22) arranged on a top surface of said package substrate body, the oxide prevention layer preferably comprising a Nickel Palladium Gold layer stack or a Palladium Gold layer stack.
8. The semiconductor assembly according to claim 7, wherein the package substrate comprises an Ag pad (23) arranged in between a package substrate body and the oxide prevention layer at the position where the semiconductor die is to be attached.
9. The packaged RF amplifier according to any of the previous claims, further comprising:
a plurality of leads (30) being arranged spaced apart from the package substrate;
a separation element (31) for separating the package substrate and the plurality of leads; and
a plurality of bondwires (33) electrically connecting the RF power transistor to the plurality of leads.
10. A method for manufacturing the packaged radioffequency‘RF’ amplifier as defined in any of the previous claims, comprising the steps of:
a) providing (SI) the semiconductor die having the semiconductor substrate;
b) arranging (S2) the seed layer on the backside of the semiconductor substrate comprising the steps of:
bl) arranging the first layer of Aluminum (Al) on the backside of the semiconductor substrate by means of sputtering or evaporation;
b2) arranging the second layer of Nickel (Ni) on the first layer by means of sputtering or evaporation;
b3) arranging the third layer of Silver (Ag) on the second layer by means of sputtering or evaporation c) arranging (S3) the eutectic AuSn alloy solder layer on the seed layer by means of electroplating;
d) providing (S4) the package substrate; and
e) die-attaching (S5) the semiconductor die to the package substrate using the eutectic AuSn alloy solder layer.
PCT/NL2019/050586 2018-09-10 2019-09-10 Seed layer for electroplating eutectic ausn solder WO2020055244A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739854A (en) * 2020-07-06 2020-10-02 绍兴同芯成集成电路有限公司 Thick copper film of two-sided electroplating of windowing

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1207010A (en) * 1967-12-01 1970-09-30 Semikron Gleichrichterbau Improvements relating to contact electrodes
US5275958A (en) * 1992-01-23 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Method for producing semiconductor chips
US20070131734A1 (en) * 2005-12-07 2007-06-14 Khalil Hosseini Method for the planar joining of components of semiconductor devices and a diffusion joining structure
EP2693465A1 (en) * 2012-07-31 2014-02-05 Nxp B.V. Electronic device and method of manufacturing such device
US20140070226A1 (en) * 2012-09-12 2014-03-13 Avogy, Inc Bondable top metal contacts for gallium nitride power devices
EP2830089A1 (en) * 2013-07-25 2015-01-28 Nxp B.V. RF power device
US20160111395A1 (en) * 2014-10-15 2016-04-21 Infineon Technologies Ag Method of forming a chip assembly and chip assembly
US9324674B2 (en) 2013-12-24 2016-04-26 Ampleon Netherlands B.V. Die substrate assembly and method
US20160358884A1 (en) * 2015-06-04 2016-12-08 Daniel Cavasin Semiconductor chip metal alloy thermal interface material

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1207010A (en) * 1967-12-01 1970-09-30 Semikron Gleichrichterbau Improvements relating to contact electrodes
US5275958A (en) * 1992-01-23 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Method for producing semiconductor chips
US20070131734A1 (en) * 2005-12-07 2007-06-14 Khalil Hosseini Method for the planar joining of components of semiconductor devices and a diffusion joining structure
EP2693465A1 (en) * 2012-07-31 2014-02-05 Nxp B.V. Electronic device and method of manufacturing such device
US20140070226A1 (en) * 2012-09-12 2014-03-13 Avogy, Inc Bondable top metal contacts for gallium nitride power devices
EP2830089A1 (en) * 2013-07-25 2015-01-28 Nxp B.V. RF power device
US9324674B2 (en) 2013-12-24 2016-04-26 Ampleon Netherlands B.V. Die substrate assembly and method
US20160111395A1 (en) * 2014-10-15 2016-04-21 Infineon Technologies Ag Method of forming a chip assembly and chip assembly
US20160358884A1 (en) * 2015-06-04 2016-12-08 Daniel Cavasin Semiconductor chip metal alloy thermal interface material

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEE CH C: "Silver Flip-chip Interconnect Technology", 20 September 2011 (2011-09-20), XP055647896, Retrieved from the Internet <URL:http://site.ieee.org/ocs-cpmt/files/2011/08/CPMT_OC_Sep_20_2011_Prof_Lee_Presentation.pdf> [retrieved on 20191129] *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739854A (en) * 2020-07-06 2020-10-02 绍兴同芯成集成电路有限公司 Thick copper film of two-sided electroplating of windowing
CN111739854B (en) * 2020-07-06 2022-03-29 绍兴同芯成集成电路有限公司 Thick copper film of two-sided electroplating of windowing

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