NL2021598B1 - Seed layer for electroplating eutectic AuSn solder - Google Patents

Seed layer for electroplating eutectic AuSn solder Download PDF

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Publication number
NL2021598B1
NL2021598B1 NL2021598A NL2021598A NL2021598B1 NL 2021598 B1 NL2021598 B1 NL 2021598B1 NL 2021598 A NL2021598 A NL 2021598A NL 2021598 A NL2021598 A NL 2021598A NL 2021598 B1 NL2021598 B1 NL 2021598B1
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NL
Netherlands
Prior art keywords
layer
semiconductor
substrate
package substrate
composition according
Prior art date
Application number
NL2021598A
Other languages
Dutch (nl)
Inventor
Kits Sandra
Wilhelmus Van Rijckevorsel Johannes
Original Assignee
Ampleon Netherlands Bv
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Filing date
Publication date
Application filed by Ampleon Netherlands Bv filed Critical Ampleon Netherlands Bv
Priority to NL2021598A priority Critical patent/NL2021598B1/en
Priority to PCT/NL2019/050586 priority patent/WO2020055244A1/en
Application granted granted Critical
Publication of NL2021598B1 publication Critical patent/NL2021598B1/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
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    • H01L2924/35121—Peeling or delaminating

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Abstract

The present invention relates to a semiconductor assembly comprising a semiconductor die and a package substrate onto which the semiconductor die has been attached using an eutectic Gold 5 Tin (AuSn) solder layer. The present invention proposes a seed layer in between the eutectic AuSn alloy solder layer and semiconductor substrate that comprises a first layer of Aluminum contacting the backside of the semiconductor substrate, and a second layer of Nickel contacting the first layer. 1 O

Description

Seed layer for electroplating eutectic AuSn solder
The present invention relates to a semiconductor assembly comprising a semiconductor die and a package substrate onto which the semiconductor die is to be attached using an eutectic Gold Tin (AuSn) alloy solder layer. The invention further relates to a packaged radiofrequency ‘RF’ amplifier that comprises this semiconductor assembly. Furthermore, the invention relates to a method for manufacturing the packaged RF amplifier.
In modern day RF electronics, high power devices (>50W) have become important components in applications such as base station amplifiers for mobile telecommunications, RADAR transmit amplifiers, or solid-state cooking power amplifiers. Examples of high power devices are Silicon-based LDMOS amplifiers or Gallium Nitride based amplifiers. For these amplifiers, a Doherty configuration is often used.
The high power devices typically comprise a package having a package substrate and a plurality of leads spaced apart from the package substrate. The power ampl ifying element, in the form of a semiconductor die on which a power transistor, such as a field-effect transistor ‘FET’ is realized, is mounted on the package substrate. The terminals of the FET, or the circuitry in which it is used, are connected to respective leads to allow signals to be fed to and extract from the package.
As the high power devices typically consume a relatively large amount of heat, thermal properties of the package are important. To this end, the thermal conductivity of the package substrate should be as high as possible. Copper (Cu) substrates or Cu-based substrates are therefore used more often nowadays despite the apparent mismatch in thermal expansion coefficient between the Cu substrate and the semiconductor die.
To mount the semiconductor die onto the Cu substrate, an eutectic die-attach process is known that uses an eutectic Gold-Tin (AuSn) alloy solder lay er. The solder layer has a particular ratio between Au and Sn such as 80/20 wt%. This layer is electroplated onto the semiconductor die. During the die-attach process, the semiconductor die is pressed onto the Cu substrate simultaneous with the application of heat sufficient for melting the solder layer. Upon cooling, the AuSn will solidify and provide a strong bond between the semiconductor die and the Cu substrate.
The eutectic AuSn alloy solder layer cannot be applied on the semiconductor die directly. Firstly, a metal seed layer is required for the electroplating process Secondly, during die-attach, the molten AuSn layer may partially dissolve the semiconductor die causing excessive formation of Silicon oxides, such as SiO2, around the semiconductor die.
Figure 1 illustrates an example of the formation of Silicon oxides due to the reaction of the AuSn layer with the Silicon semiconductor substrate. As shown in figure 1. the AuSn layer creeps from underneath the semiconductor die 110. Here, part 100 consists, at least in a large part, of the
AuSn solder layer. This layer is covered by a Silicon oxide that was formed as a result of the interaction between the AuSn solder layer and the Silicon semiconductor substrate.
It is known to arrange one or more metal layers in between the semiconductor die and the AuSn solder layer. Within the context of the present invention, these layers will be jointly referred to as seed layer. One of the intended purposes of this seed layer is to prevent the migration of the AuSn layer towards the semiconductor die.
Most high power amplifiers have a single-ended configuration in which the source of the FET should be grounded via a low inductance and low resistance path to ground. Most semiconductor dies therefore comprise a conductive semiconductor substrate. A low resistance connection can then be obtained via the semiconductor substrate and the grounded package substrate. An important part of the low resistance connection is formed by the contact resistance associated with the connection between the semiconductor substrate and the abovementioned seed layer.
US 9.324,674 discloses a seed layer comprising, starting from the backside of the semiconductor substrate, a first layer of Gold (Au), a second layer of Silver (Ag), a third layer of Nickel (Ni), and a fourth layer of Au onto which the AuSn will be arranged. In this layer stack, the Ni layer provides a barrier to the AuSn layer and limits the formation of Silicon oxides.
To reduce the formation of Silicon oxides even further it is known to arrange an additional fifth relatively thick Ni layer in between the AuSn and the fourth Au layer. This fifth layer as well as the AuSn layer are arranged using electroplating techniques. The thickness of this electroplated Ni layer is approximately 1 micrometer and the thickness of the AuSn layer varies between 3 and 5 micrometers.
The Applicant has found that the reliability and manufacturability of the abovementioned die-attach between the semiconductor die having the additional fifth Ni layer and Copper or Copper based substrates is unsatisfactory
An object of the present invention is to provide a seed layer in which the abovementioned problem does not or hardly occur.
According to the invention, this object is achieved with a semiconductor assembly as defined in claim 1, which comprises a semiconductor die and a package substrate. The semiconductor die comprises a semiconductor substrate, a seed layer arranged on a backside of the semiconductor substrate, and an electroplated eutectic AuSn alloy solder layer arranged on the seed layer. The semiconductor die is to be attached on the package substrate using the eutectic AuSn alloy solder layer.
The semiconductor assembly is characterized in that the seed layer comprises a first layer of Aluminu m (Al) contacting the backside of the semiconductor substrate, and a second layer of Ni contacting the first layer.
The Applicant has found that the relatively thick Ni layer used in the prior art causes burring to occur when the individual semiconductor dies are separated from the semiconductor wafer by means of for example a cutting or sawing operation. When the semiconductor die, having burred edges, is placed on the package substrate to which it is to be connected using the abovementioned die-attach process, a small separation between the backside of the semiconductor die and the substrate may occur. In some cases, this separation may be so large that the die-attach process fails or that the die-attach provides a low-strength bond.
The Applicant has further found that when an Al layer is used as the first layer, the relatively thick Mi layer can be omitted without causing a considerable increase in the formation of Silicon oxides during the die-attach process. More in particular, together with a Ni layer as the second layer, a sufficiently high barrier for limiting the formation of Silicon oxides is realized. Due to the fact that the relatively thick Ni layer of the prior art can be omitted, the amount of burring can be greatly reduced, thereby improving the reliability of the die-attach process. In addition, because the formation of Silicon oxides is reduced, the temperature used during the die-attach process can be increased, thereby improving the reliability of the connection betw een die and the package substrate.
The seed layer may further comprise a third layer of Ag that contacts the second layer. The third layer may constitute the outer metal layer that acts as an electrode during the electroplating process.
The first layer may have a thickness in the range between 100 and 600 nm, more preferably in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
The second layer may have a thickness in the range between 100 and 900 nm. more preferably in the range between 100 and 400 nm, more preferably between 200 and 300 nm, and even more preferably between 230 and 270 nm.
The third layer may have a thickness in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm.
In an embodiment, each of the first, second, and third layer has a thickness in the range between 180 and 270 nm.
The first layer, the second layer, and the third layer when applicable, may each have been formed using a metal evaporation process or a sputtering process.
Additionally or alternatively, the eutectic AuSn alloy solder layer may have a thickness in the range between 1 and 8 micrometer, and more preferably between 2.5 and 5.5 micrometer. The Au content in the AuSn alloy solder layer may range from 70 to 90 percent by weight, preferably from 75 to 85 percent, more preferably substantially equaling 80 percent by weight. The eutectic alloy of AuSn using this latter ratio provides a melting temperature of approximately 280°C.
The package substrate may comprise a Copper substrate comprising more than 80 percent of Copper by weight., more preferably more than 90 percent, and even more preferably more than 98 percent. The package substrate may alternatively comprise a copper plated ceramic ‘CPC’ substrate or a Copper Tungsten (CuW) substrate.
The package substrate may comprise a package substrate body and an oxide prevention layer arranged on a top surface of the package substrate body. The oxide prevention layer may for example have been applied using sputtering, evaporation, or electroplating techniques,, and may comprise a Nickel Palladium Gold layer stack or a Palladium Gold layer stack.
An Ag pad may be arranged in between the package substrate body and the oxide prevention layer at a position where the semiconductor die is to be attached. The Ag pad may function as a stress relieve layer to mitigate the difference in thermal expansion coefficient of the semiconductor die and the package substrate body. As such, the Ag pad may reduce the risk of the attachment between the semiconductor die and package substrate to weaken or break as a result of temperature changes.
The seed layer of the invention is particularly suitable for Silicon substrates although it may equally be used for Gallium Nitride substrates.
According to a further aspect, the present invention provides a packaged RF power amplifier comprising the semiconductor assembly as described above,, wherein the semiconductor die has been die-attached to the package substrate using the eutectic AuSn alloy solder layer. The packaged RF amplifier preferably comprises an RF power transistor arranged on the semiconductor die.
The packaged RF amplifier may further comprise a plurality of leads being arranged spaced apart from the package substrate, and a separation element for separating the package substrate and the plurality of leads. The separation element may for example comprise a ceramic ring or a solidified and/or cured molding compound. The packaged RF amplifier may further comprise a plurality of bondwires electrically connecting the RF power transistor to the plurality of leads.
According to an even further aspect, the present invention provides a method for manufacturing the packaged RF amplifier described above. The method comprises the steps of a) providing a semiconductor die having a semiconductor substrate, and b) arranging a seed layer on a backside of the semiconductor substrate. Step b) comprises the steps of bl) arranging a first layer of Aluminum (Al) on the backside of the semiconductor substrate by means of sputtering or evaporation, and b2) arranging a second layer of Nickel (Ni) on the first layer by means of sputtering or evaporation .
The method according to the invention further comprises c) arranging an eutectic AuSn alloy solder layer on the seed layer by means of electroplating, d) providing a package substrate, and e) die-attaching the semiconductor die to the package substrate using the eutectic AuSn alloy solder layer. Step b) may further comprise b3) arranging a third layer of Silver (Ag) on the third layer by means of sputtering or evaporation.
The first layer, the second layer, the third layer, the semiconductor die, and/or the package substrate may be configured as defined in connection with the abovementioned semiconductor assembly.
Next, the present invention will be described in more detail referring to the appended drawings, wherein:
Figure 1 illustrates the formation of Silicon oxides;
Figure 2 illustrates a semiconductor assembly in accordance with the present invention;
Figure 3 illustrates a packaged RF amplifier obtained using the semiconductor assembly of figure 2: and
Figure 4 illustrates a method for manufacturing the RF amplifier of figure 3.
Figure 2 illustrates a semiconductor assembly in accordance with the present invention. It comprises a semiconductor die 10 and a package substrate 20. Semiconductor die 10 comprises a semiconductor substrate 11, for example a Silicon substrate in which one or more integrated circuits are realized. On a backside of substrate 11, a seed layer 12 is arranged by means of evaporation or sputtering techniques. Seed layer 12 comprises a first layer of Al having a thickness in the range between 180 and 220 nm, and a second layer of Ni having a thickness in the range between 230 and 270 nm. Preferably, seed layer 12 comprises an additional layer that provides a suitable exposed surface for a subsequent electroplating process. For example, seed layer 12 may comprise a. third layer of Ag having a thickness in the range between 180 and 220 nm. The invention is however not limited to these ranges. For example, a thicker first and/or second layer may be used.
An eutectic AuSn alloy solder layer 13, having a thickness in the range between 1 and 8 micrometer, and having an Au substantially equaling 80 percent by weight, is electroplated onto seed layer 12.
Package substrate 20 comprises a package substrate body 21, for example comprising a Copper block or coin. Package substrate body 21 is covered by an oxide prevention layer 22, such as a Nickel Palladium Gold metal layer stack, wherein the thicknesses of each layer are in the range between 200 and 1500 nm, 20 and 200 nm, and 1 and 20 nm, respectively. Alternatively, a Palladium Gold metal layer stack is used, w herein the thicknesses of each layer are in the range between 50 and 800 nm, and 1 and 20 nm, respectively.
In an embodiment, a. stress relieve layer 23 is arranged in between package substrate body 21 and oxide prevention layer 22. This relieve layer may be formed using a relatively thick layer of
Ag, for example having a. thickness exceeding 4 micrometer, for example between 6 and 10 micrometer, and arranged at the position where semiconductor die 10 is to be mounted.
Figure 3 illustrates the implementation of the assembly in figure 1 in a packaged radiofrequency ‘RF’ amplifier. Here, a power transistor 32 or circuitry comprising such a transistor is realized in semiconductor die 11. Signals can be fed to or collected from transistor 32 using bondwires 33 that extend between transistor 32 and leads 30. As shown in figure 2, leads 30 are fixed relative to package substrate 30 in a spaced apart manner. Such separation may for example be achieved by a ceramic ring 31 as shown. Alternatively, the separation is achieved by a solidified and/or cured molding compound.
Figure 3 illustrates the semiconductor assembly in an assembled state. Here, it should be noted that the identification of the various layers may in practice not be as clear as indicated in figure 2. The heat treatments involved may cause the various layers to melt and to become mixed instead of the clear borders in between layers in figures 2 and 3. The skilled person will therefore understand that these borders have an illustrational purpose only.
Figure 4 illustrates a method for manufacturing the semiconductor package of figure 3. As illustrated, the method comprises, as a first step, the provision (S1) of a semiconductor die having a semiconductor substrate. Next, a seed layer will be arranged (S2) on a backside of the semiconductor substrate. This step comprises the sub-steps of arranging (S2_l) a first layer of Aluminum on the backside of the semiconductor substrate by means of sputtering or evaporation, and arranging (S2_2) a second layer of N ickel on the first layer by means of sputtering or evaporation. Next, an eutectic AuSn alloy solder layer is arranged (S3) on the seed layer by means of electroplating. Then, a package substrate is provided (S4), and a die-a.ttach process using the eutectic AuSn alloy solder layer is performed (S5) by which the semiconductor die is connected to the package substrate.
The present invention has been described using detailed embodiments thereof. However, it will be clear to the skilled person in the art that various modifications can be made without departing from the scope of the invention that is defined by the appended claims.

Claims (18)

1. Halfgeleidersamenstelling omvattende:Semiconductor composition comprising: een halfgeleiderdie (10) omvattende een halfgeleidersubstraat (11), een startlaag (“seed layer”) (12), gerangschikt op een achterzijde van het halfgeleidersubstraat en een door middel van elektroplating aangebrachte eutectische AuSn-legering soldeerlaag (13) gerangschikt op de startlaag;a semiconductor die (10) comprising a semiconductor substrate (11), a starting layer (seed layer) (12) arranged on a back side of the semiconductor substrate and an electroplated eutectic AuSn alloy solder layer (13) arranged on the starting layer ; een package-substraat (20) waar de halfgeleiderdie op bevestigd moet worden door gebruik te maken van de eutectische AuSn-legering soldeerlaag;a package substrate (20) to which the semiconductor to be attached using the eutectic AuSn alloy solder layer; met het kenmerk, dat de startlaag een eerste laag (12a) van aluminium (Al) omvat welke in contact staat met de achterzijde van het halfgeleidersubstraat en een tweede laag (12b) van nikkel (Ni) welke in contact staat met de eerste laag.characterized in that the starting layer comprises a first layer (12a) of aluminum (Al) which contacts the back of the semiconductor substrate and a second layer (12b) of nickel (Ni) which contacts the first layer. 2. Halfgeleidersamenstelling volgens conclusie 1, waarbij de startlaag verder een derde laag (12c) van zilver (Ag) omvat, welke in contact staat met de tweede laag.The semiconductor composition of claim 1, wherein the starting layer further comprises a third layer (12c) of silver (Ag) which is in contact with the second layer. 3. Halfgeleidersamenstelling volgens conclusie 2, waarbij de derde laag een dikte heeft in het bereik tussen 100 en 400 nm, meer bij voorkeur tussen 150 en 250 nm en nog meer bij voorkeur tussen 180 en 220 nm.The semiconductor composition according to claim 2, wherein the third layer has a thickness in the range between 100 and 400 nm, more preferably between 150 and 250 nm and even more preferably between 180 and 220 nm. 4. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij de eerste laag een dikte heeft in het bereik tussen 100 en 600 nm, meer bij voorkeur in het bereik tussen 100 en 400 nm, meer bij voorkeur tussen 150 en 250 nm, en nog meer bij voorkeur tussen 180 en 220 nm.The semiconductor composition according to any of the preceding claims, wherein the first layer has a thickness in the range between 100 and 600 nm, more preferably in the range between 100 and 400 nm, more preferably between 150 and 250 nm, and even more preferably between 180 and 220 nm. 5. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij de tweede laag een dikte heeft in het bereik tussen 100 en 900 nm, meer bij voorkeur in het bereik tussen 100 en 400 nm, meer bij voorkeur tussen 200 en 300 nm en nog meer bij voorkeur tussen 230 en 270 nm.The semiconductor composition according to any of the preceding claims, wherein the second layer has a thickness in the range between 100 and 900 nm, more preferably in the range between 100 and 400 nm, more preferably between 200 and 300 nm and even more at preferably between 230 and 270 nm. 6. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij elk van de eerste, tweede en derde laag, wanneer van toepassing, een dikte heeft in het bereik tussen 180 en 270 nm.The semiconductor composition according to any of the preceding claims, wherein each of the first, second and third layers, when applicable, has a thickness in the range between 180 and 270 nm. 7. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij de eerste laag, de tweede laag en de derde laag, wanneer van toepassing, elk zijn gevormd door gebruik te maken van een metaalverdampingsproces of een sputterproces.The semiconductor composition according to any of the preceding claims, wherein the first layer, the second layer and the third layer, when applicable, are each formed using a metal evaporation process or a sputtering process. 8. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij de AuSn-legering soldeerlaag een dikte heeft in het bereik tussen 1 en 8 micrometer, waarbij het Au gehalte in de AuSn-legering soldeerlaag varieert tussen 70 tot 90 gewichtsprocent, bij voorkeur tussen 75 en 85 procent, meer bij voorkeur substantieel gelijk aan 80 procent,The semiconductor composition according to any of the preceding claims, wherein the AuSn alloy brazing layer has a thickness in the range between 1 and 8 micrometers, the Au content in the AuSn alloy brazing layer ranging between 70 to 90 weight percent, preferably between 75 and 90 85 percent, more preferably substantially equal to 80 percent, 9. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij het package-substraat een kopersubstraat omvat, omvattende meer dan 80 gewichtsprocent koper, meer bij voorkeur meer dan 90 procent en nog meer bij voorkeur meer dan 98 procent.The semiconductor composition according to any of the preceding claims, wherein the package substrate comprises a copper substrate comprising more than 80 weight percent copper, more preferably more than 90 percent, and even more preferably more than 98 percent. 10. Halfgeleidersamenstelling volgens een van de conclusies 1-8, waarbij het packagesubstraat een met koper geplateerd keramiek ‘CPC’ substraat of een koper wolfraam (CuW) substraat omvat.The semiconductor composition of any one of claims 1-8, wherein the package substrate comprises a copper plated ceramic "CPC" substrate or a copper tungsten (CuW) substrate. 11. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij het package-substraat een package-substraat-lichaam (21) en een oxide-preventie-laag (22) omvat, gerangschikt op een bovenste oppervlak van het package-substraat-lichaam, waarbij de oxidepreventie-laag bij voorkeur een nikkel-palladium-goud laagstapel of een palladium-goud laagstapel omvat.The semiconductor composition according to any preceding claim, wherein the package substrate comprises a package substrate body (21) and an oxide prevention layer (22) arranged on an upper surface of the package substrate body, wherein the oxide prevention layer preferably comprises a nickel-palladium-gold layer stack or a palladium-gold layer stack. 12. Halfgeleidersamenstelling volgens conclusie 11, waarbij het package-substraat een Ag-vlak (23) omvat, gerangschikt tussen een package-substraat-lichaam en de oxide-preventie-laag op de positie waar de halfgeleiderdie moet worden bevestigd.The semiconductor composition of claim 11, wherein the package substrate comprises an Ag plane (23) disposed between a package substrate body and the oxide prevention layer at the position where the semiconductor to be attached. 13. Halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij het halfgeleidersubstraat een silicium substraat of een gallium-nitride substraat omvat.The semiconductor composition according to any of the preceding claims, wherein the semiconductor substrate comprises a silicon substrate or a gallium nitride substrate. 14. Verpakte radiofrequentie “RF” versterker omvattende de halfgeleidersamenstelling volgens een van de voorgaande conclusies, waarbij de halfgeleiderdie die-gemonteerd (“dieattached”) is aan het package-substraat door gebruik te maken van de eutectische AuSn-legering soldeerlaag, waarbij de verpakte RF-versterker een RF-vermogens transistor (32) omvat gerangschikt op de halfgeleiderdie.Packaged radio frequency "RF" amplifier comprising the semiconductor composition according to any of the preceding claims, wherein the semiconductor is die-mounted to the package substrate using the eutectic AuSn alloy solder layer, wherein the packaged RF amplifier includes an RF power transistor (32) arranged on the semiconductor. 15. Verpakte RF-versterker volgens conclusie 14 verder omvattende:The packaged RF amplifier of claim 14 further comprising: een veelvoud aan leiders (“leads”) (30) welke zijn gerangschikt op een afstand van het package-s u bstraat;a plurality of leaders (“leads”) (30) which are arranged at a distance from the package's substrate; een scheidingselement (31) voor het scheiden van het package-substraat en het veelvoud aan leiders; en een veelvoud aan bonddraden (33) welke de RF-vermogenstransistor elektrisch aan het veelvoud van leiders verbinden.a separating element (31) for separating the package substrate and the plurality of leaders; and a plurality of bond wires (33) electrically connecting the RF power transistor to the plurality of conductors. 16. Werkwijze voor het vervaardigen van de verpakte radiofrequentie “RF” versterker zoals gedefinieerd in een van de conclusies 14 of 15, de stappen omvattende van:A method of manufacturing the packaged radio frequency "RF" amplifier as defined in any one of claims 14 or 15, comprising the steps of: a) het verschaffen (SI) van een halfgeleiderdie welke een halfgeleidersubstraat omvat;a) providing (SI) a semiconductor which includes a semiconductor substrate; b) het rangschikken (S2) van een startlaag op een achterzijde van het halfgeleidersubstraat, de stappen omvattende van:b) arranging (S2) a starting layer on a back side of the semiconductor substrate, comprising the steps of: bl) het rangschikken van een eerste laag van aluminium (Al) op de achterzijde van het halfgeleidersubstraat door gebruik te maken van sputteren of verdamping, b2) het rangschikken van een tweede laag van nikkel (Ni) op de eerste laag door gebruik te maken van sputteren of verdampen;bl) arranging a first layer of aluminum (Al) on the back of the semiconductor substrate using sputtering or evaporation, b2) arranging a second layer of nickel (Ni) on the first layer using sputtering or evaporation; c) het rangschikken (S3) van een eutectische AuSn-legering soldeerlaag op de startlaag door gebruik te maken van elektroplalen;c) arranging (S3) an eutectic AuSn alloy brazing layer on the starting layer using electrical poles; d) het verschaffen (S4) van een package-substraat; end) providing (S4) a package substrate; and e) het die-monteren (“die-attaching”) (S5) van de halfgeleiderdie aan het packagesubstraat door gebruik te maken van de eutectische AuSn-legering soldeerlaag.e) die-mounting (S5) the semiconductor die to the package substrate using the eutectic AuSn alloy brazing layer. 17. Werkwijze volgens conclusie 16, waarbij de stap b) verder omvat:The method of claim 16, wherein step b) further comprises: b3) het rangschikken van een derde laag van zilver (Ag) op de derde laag door gebruik te maken van sputteren of verdampen.b3) arranging a third layer of silver (Ag) on the third layer using sputtering or evaporation. 18. Werkwijze volgens conclusie 16 of 17, waarbij de eerste laag, de tweede laag, de derde laag, de halfgeleiderdie en/of het package-substraat zijn ingericht zoals is gedefinieerd in een van de conclusies 1-13.A method according to claim 16 or 17, wherein the first layer, the second layer, the third layer, the semiconductor and / or the package substrate are arranged as defined in any one of claims 1-13.
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