JP2014207388A - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP2014207388A JP2014207388A JP2013085233A JP2013085233A JP2014207388A JP 2014207388 A JP2014207388 A JP 2014207388A JP 2013085233 A JP2013085233 A JP 2013085233A JP 2013085233 A JP2013085233 A JP 2013085233A JP 2014207388 A JP2014207388 A JP 2014207388A
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- Prior art keywords
- bonding
- semiconductor package
- bonding layer
- copper
- wiring pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
11 基板
12 セラミック枠体
13 配線パターン
14 メタルリング
15 リード
16 接合層
Claims (6)
- 上面に半導体装置が固着される固着領域を有する平板状の基板と、
平面状の上下2層のセラミック枠からなり、下層のセラミック枠の上面には端子となる配線パターンが形成され、上層のセラミック枠のうち、前記配線パターンの両端に該当する部分は前記下層のセラミック枠よりもその枠幅を細くすることにより前記配線パターンの両端を側壁に露出させて端子を兼ねた形状の側壁とするとともに、前記固着領域を囲み前記基板上面に積層されて一方の開口面が第1の接合層を介して前記基板上面に接合されたセラミック枠体と、
前記セラミック枠体の他方の開口面における枠体の形状に対応した形状を有し、前記セラミック枠体の他方の開口面に積層されて第2の接合層を介してこのセラミック枠体に接合されたメタルリングと、
前記配線パターン上に積層されて第3の接合層を介してこの配線パターンに接合されたリードとを備え、
前記第1の接合層、前記第2の接合層、及び前記第3の接合層は、その組成として錫(Sn)、インジウム(In)及び亜鉛(Zn)のうちの少なくとも1つの金属と、銅(Cu)とを含み、前記接合層の厚さ方向の両端となる対向する2面の接合面のどちらか一方の面に向けて前記金属の含有量が減少し、同方向に前記銅の含有量が増加する
ことを特徴とする半導体パッケージ。 - 前記第1乃至第3の接合層における前記金属の含有量は、前記2面の接合面の両方に向けて減少し、前記銅の含有量は、前記2面の接合面の両方に向けて増加することを特徴とする請求項1に記載の半導体パッケージ。
- 前記接合層の2面の接合面は銅層をなしていることを特徴とする請求項2に記載の半導体パッケージ。
- 前記接合層は、金(Au)及び白金(Pt)の少なくともいずれかを含有することを特徴とする請求項1乃至請求項3のいずれか1項に記載の半導体パッケージ。
- 前記基板は銅、または銅合金からなり、前記メタルリングは鉄(Fe)にニッケル(Ni)及びコバルト(Co)を配合した合金からなり、前記リードは銅、または鉄(Fe)にニッケル(Ni)及びコバルト(Co)を配合した合金からなることを特徴とする請求項1乃至請求項4のいずれか1項に記載の半導体パッケージ。
- 前記セラミック枠体の側面は階段状の外形を有し、前記配線パターンはこの階段面上に露出して形成されていることを特徴とする請求項1乃至請求項5のいずれか1項に記載の半導体パッケージ。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013085233A JP2014207388A (ja) | 2013-04-15 | 2013-04-15 | 半導体パッケージ |
TW103104890A TWI579993B (zh) | 2013-04-15 | 2014-02-14 | 半導體封裝 |
KR1020140017711A KR20140123893A (ko) | 2013-04-15 | 2014-02-17 | 반도체 패키지 |
CN201410058300.5A CN104103600A (zh) | 2013-04-15 | 2014-02-20 | 半导体封装体 |
US14/202,075 US9013034B2 (en) | 2013-04-15 | 2014-03-10 | Semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013085233A JP2014207388A (ja) | 2013-04-15 | 2013-04-15 | 半導体パッケージ |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2014207388A true JP2014207388A (ja) | 2014-10-30 |
Family
ID=51671618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013085233A Pending JP2014207388A (ja) | 2013-04-15 | 2013-04-15 | 半導体パッケージ |
Country Status (5)
Country | Link |
---|---|
US (1) | US9013034B2 (ja) |
JP (1) | JP2014207388A (ja) |
KR (1) | KR20140123893A (ja) |
CN (1) | CN104103600A (ja) |
TW (1) | TWI579993B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020009953A (ja) * | 2018-07-10 | 2020-01-16 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5588419B2 (ja) * | 2011-10-26 | 2014-09-10 | 株式会社東芝 | パッケージ |
US9728510B2 (en) * | 2015-04-10 | 2017-08-08 | Analog Devices, Inc. | Cavity package with composite substrate |
JP6915556B2 (ja) * | 2018-01-24 | 2021-08-04 | 三菱マテリアル株式会社 | 半導体モジュールの接合層、半導体モジュール及びその製造方法 |
KR102325114B1 (ko) * | 2019-12-06 | 2021-11-11 | 제엠제코(주) | 반도체 패키지의 제조 방법 |
US20220044979A1 (en) * | 2020-08-04 | 2022-02-10 | Qorvo Us, Inc. | Hermetic package for high cte mismatch |
CN112366193B (zh) * | 2020-11-02 | 2021-09-17 | 上海燧原智能科技有限公司 | 一种桥接芯片及半导体封装结构 |
US11823991B2 (en) * | 2021-03-26 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Frames stacked on substrate encircling devices and manufacturing method thereof |
CN115547939B (zh) * | 2022-12-02 | 2023-03-17 | 合肥圣达电子科技实业有限公司 | 一种小体积大电流功率型陶瓷一体化外壳及制备方法 |
Citations (3)
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JP2003068916A (ja) * | 2001-08-24 | 2003-03-07 | Sumitomo Electric Ind Ltd | 半導体素子収納用パッケージ |
JP2006269970A (ja) * | 2005-03-25 | 2006-10-05 | Yoshikawa Kogyo Co Ltd | 電子部品のはんだ接合方法 |
WO2008149584A1 (ja) * | 2007-06-04 | 2008-12-11 | Murata Manufacturing Co., Ltd. | 電子部品装置およびその製造方法 |
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US4649416A (en) * | 1984-01-03 | 1987-03-10 | Raytheon Company | Microwave transistor package |
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US5041695A (en) * | 1989-06-01 | 1991-08-20 | Westinghouse Electric Corp. | Co-fired ceramic package for a power circuit |
EP0434264B1 (en) * | 1989-12-22 | 1994-10-12 | Westinghouse Electric Corporation | Package for power semiconductor components |
JP3292798B2 (ja) * | 1995-10-04 | 2002-06-17 | 三菱電機株式会社 | 半導体装置 |
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-
2013
- 2013-04-15 JP JP2013085233A patent/JP2014207388A/ja active Pending
-
2014
- 2014-02-14 TW TW103104890A patent/TWI579993B/zh not_active IP Right Cessation
- 2014-02-17 KR KR1020140017711A patent/KR20140123893A/ko active Search and Examination
- 2014-02-20 CN CN201410058300.5A patent/CN104103600A/zh active Pending
- 2014-03-10 US US14/202,075 patent/US9013034B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003068916A (ja) * | 2001-08-24 | 2003-03-07 | Sumitomo Electric Ind Ltd | 半導体素子収納用パッケージ |
JP2006269970A (ja) * | 2005-03-25 | 2006-10-05 | Yoshikawa Kogyo Co Ltd | 電子部品のはんだ接合方法 |
WO2008149584A1 (ja) * | 2007-06-04 | 2008-12-11 | Murata Manufacturing Co., Ltd. | 電子部品装置およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020009953A (ja) * | 2018-07-10 | 2020-01-16 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
US11508672B2 (en) | 2018-07-10 | 2022-11-22 | Sumitomo Electric Device Innovations, Inc. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
US9013034B2 (en) | 2015-04-21 |
TW201501262A (zh) | 2015-01-01 |
TWI579993B (zh) | 2017-04-21 |
KR20140123893A (ko) | 2014-10-23 |
US20140306334A1 (en) | 2014-10-16 |
CN104103600A (zh) | 2014-10-15 |
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