JP4519637B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4519637B2 JP4519637B2 JP2004381897A JP2004381897A JP4519637B2 JP 4519637 B2 JP4519637 B2 JP 4519637B2 JP 2004381897 A JP2004381897 A JP 2004381897A JP 2004381897 A JP2004381897 A JP 2004381897A JP 4519637 B2 JP4519637 B2 JP 4519637B2
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- dielectric substrate
- conductor
- side wall
- base substrate
- circuit pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Microwave Amplifiers (AREA)
Description
11…半導体素子
12…第1誘電体基板
12a…回路パターン
13…第2誘電体基板
13a…回路パターン
14…第3誘電体基板
14a…線路導体
15…第4誘電体基板
15a…線路導体
16…側壁
17…蓋
18a…入力用帯状導体
18b…出力用帯状導体
19a…入力用リード線
19b…出力用リード線
S…ベース基板の面
Claims (2)
- 金属製ベース基板と、このベース基板上に配置された半導体素子と、前記ベース基板上に配置され、表面に回路パターンを形成した第1誘電体基板と、前記半導体素子および前記第1誘電体基板を囲んで前記ベース基板上に設けた枠状の側壁と、前記側壁の一部に設けられた絶縁物からなる側壁部分と、前記ベース基板の面を基準にして、前記回路パターンよりも高い位置で前記側壁部分を貫通する帯状導体と、前記ベース基板の面を基準にして、前記回路パターンよりも高く、前記帯状導体よりも低い位置の表面に線路導体パターンを形成し、前記第1誘電体基板と前記帯状導体との間に位置する第2誘電体基板と、前記第2誘電体基板の表面に形成した前記線路導体パターンを介して前記帯状導体と前記回路パターンとの間および前記回路パターンと前記半導体素子との間をそれぞれ接続するワイヤーとを具備したことを特徴とする半導体装置。
- 金属製ベース基板と、このベース基板上に配置された半導体素子と、前記ベース基板上に配置され、表面に回路パターンを形成した第1誘電体基板と、前記半導体素子および前記第1誘電体基板を囲んで前記ベース基板上に設けた枠状の側壁と、前記側壁の一部に設けられた絶縁物からなる側壁部分と、前記ベース基板の面を基準にして、前記回路パターンよりも高い位置で前記側壁部分を貫通する帯状導体と、前記ベース基板の面を基準にして、前記回路パターンよりも高く、前記帯状導体よりも低い位置の表面に第1線路導体パターンを形成し、前記第1誘電体基板と前記帯状導体との間に位置する第2誘電体基板と、前記ベース基板の面を基準にして前記帯状導体と同じ高さに第2線路導体パターンを設け、前記第2誘電体基板と前記帯状導体との間に配置した第3誘電体基板と、前記第2誘電体基板表面に形成した前記第1線路導体パターンおよび前記第3誘電体基板表面に形成した前記第2線路導体パターンを介して前記帯状導体と前記回路パターンとの間および前記回路パターンと前記半導体素子との間をそれぞれ接続するワイヤーとを具備したことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004381897A JP4519637B2 (ja) | 2004-12-28 | 2004-12-28 | 半導体装置 |
US11/317,024 US7411288B2 (en) | 2004-12-28 | 2005-12-27 | Semiconductor device |
US12/137,620 US7576423B2 (en) | 2004-12-28 | 2008-06-12 | Semiconductor device |
US12/137,611 US7659613B2 (en) | 2004-12-28 | 2008-06-12 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004381897A JP4519637B2 (ja) | 2004-12-28 | 2004-12-28 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010086000A Division JP5135376B2 (ja) | 2010-04-02 | 2010-04-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006190712A JP2006190712A (ja) | 2006-07-20 |
JP4519637B2 true JP4519637B2 (ja) | 2010-08-04 |
Family
ID=36611237
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004381897A Active JP4519637B2 (ja) | 2004-12-28 | 2004-12-28 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (3) | US7411288B2 (ja) |
JP (1) | JP4519637B2 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4575247B2 (ja) * | 2005-07-11 | 2010-11-04 | 株式会社東芝 | 高周波パッケージ装置 |
US8125081B2 (en) * | 2006-01-16 | 2012-02-28 | Nec Corporation | Semiconductor device, printed wiring board for mounting the semiconductor device and connecting structure for these |
US8431973B2 (en) * | 2008-12-10 | 2013-04-30 | Kabushiki Kaisha Toshiba | High frequency semiconductor device |
KR101502655B1 (ko) * | 2009-03-13 | 2015-03-13 | 지멘스 악티엔게젤샤프트 | 층상으로 형성된 절연 측벽을 구비한 파워 반도체 모듈 |
JP5631607B2 (ja) * | 2009-08-21 | 2014-11-26 | 株式会社東芝 | マルチチップモジュール構造を有する高周波回路 |
JP5806464B2 (ja) * | 2010-02-03 | 2015-11-10 | 株式会社東芝 | 半導体素子収納用パッケージ及びそれを用いた半導体装置 |
US7990223B1 (en) | 2010-05-31 | 2011-08-02 | Kabushiki Kaisha Toshiba | High frequency module and operating method of the same |
US8637873B2 (en) | 2010-11-18 | 2014-01-28 | Kabushiki Kaisha Toshiba | Package and high frequency terminal structure for the same |
JP5269864B2 (ja) | 2010-12-07 | 2013-08-21 | 株式会社東芝 | 半導体装置 |
JP5588419B2 (ja) * | 2011-10-26 | 2014-09-10 | 株式会社東芝 | パッケージ |
JP6051814B2 (ja) | 2012-11-27 | 2016-12-27 | 三菱電機株式会社 | 高周波装置 |
KR101686745B1 (ko) | 2015-08-07 | 2016-12-15 | 재단법인 다차원 스마트 아이티 융합시스템 연구단 | 파워 앰프 모듈 패키지 및 그 패키징 방법 |
JP6494474B2 (ja) * | 2015-09-08 | 2019-04-03 | 株式会社東芝 | 高周波半導体装置 |
JP6412900B2 (ja) * | 2016-06-23 | 2018-10-24 | 株式会社東芝 | 高周波半導体用パッケージ |
FR3066643B1 (fr) * | 2017-05-16 | 2020-03-13 | Stmicroelectronics (Grenoble 2) Sas | Boitier electronique pourvu d'une fente locale formant un event |
US20190006254A1 (en) * | 2017-06-30 | 2019-01-03 | Kyocera International, Inc. | Microelectronic package construction enabled through ceramic insulator strengthening and design |
JP6967910B2 (ja) * | 2017-08-09 | 2021-11-17 | 新光電気工業株式会社 | 電子部品用パッケージ及び電子部品装置 |
JP7254156B2 (ja) * | 2018-11-26 | 2023-04-07 | 三菱電機株式会社 | 半導体パッケージ、及び、半導体装置 |
DE112018008167T5 (de) * | 2018-11-26 | 2021-08-12 | Mitsubishi Electric Corporation | Halbleiterbaugruppe und Herstellungsverfahren dafür und Halbleitervorrichtung |
US11264251B2 (en) * | 2018-11-29 | 2022-03-01 | Wavepia Co., Ltd. | Method of manufacturing power amplifier package embedded with input-output circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57138421U (ja) * | 1981-02-25 | 1982-08-30 | ||
JPH03263897A (ja) * | 1990-03-14 | 1991-11-25 | Fujitsu Ltd | 混成集積回路の実装方法 |
JP2002335136A (ja) * | 2001-05-11 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 高周波半導体装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04373155A (ja) | 1991-06-24 | 1992-12-25 | Nippon Telegr & Teleph Corp <Ntt> | 半導体用ヒートシンク |
US6956283B1 (en) * | 2000-05-16 | 2005-10-18 | Peterson Kenneth A | Encapsulants for protecting MEMS devices during post-packaging release etch |
US6876071B2 (en) * | 2001-06-30 | 2005-04-05 | Texas Instruments Incorporated | Masking layer in substrate cavity |
KR100461721B1 (ko) * | 2002-05-27 | 2004-12-14 | 삼성전기주식회사 | 리드 방열 세라믹 패키지 |
US7274094B2 (en) * | 2002-08-28 | 2007-09-25 | Micron Technology, Inc. | Leadless packaging for image sensor devices |
US20040046247A1 (en) * | 2002-09-09 | 2004-03-11 | Olin Corporation, A Corporation Of The Commonwealth Of Virginia | Hermetic semiconductor package |
JP2004247514A (ja) | 2003-02-13 | 2004-09-02 | Kyocera Corp | 半導体素子収納用パッケージおよび半導体装置 |
US7005720B2 (en) * | 2004-01-23 | 2006-02-28 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with photosensitive chip and fabrication method thereof |
US7091594B1 (en) * | 2004-01-28 | 2006-08-15 | Amkor Technology, Inc. | Leadframe type semiconductor package having reduced inductance and its manufacturing method |
-
2004
- 2004-12-28 JP JP2004381897A patent/JP4519637B2/ja active Active
-
2005
- 2005-12-27 US US11/317,024 patent/US7411288B2/en active Active
-
2008
- 2008-06-12 US US12/137,620 patent/US7576423B2/en not_active Expired - Fee Related
- 2008-06-12 US US12/137,611 patent/US7659613B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57138421U (ja) * | 1981-02-25 | 1982-08-30 | ||
JPH03263897A (ja) * | 1990-03-14 | 1991-11-25 | Fujitsu Ltd | 混成集積回路の実装方法 |
JP2002335136A (ja) * | 2001-05-11 | 2002-11-22 | Matsushita Electric Ind Co Ltd | 高周波半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US7411288B2 (en) | 2008-08-12 |
US7659613B2 (en) | 2010-02-09 |
JP2006190712A (ja) | 2006-07-20 |
US20080246140A1 (en) | 2008-10-09 |
US20080246141A1 (en) | 2008-10-09 |
US7576423B2 (en) | 2009-08-18 |
US20060139903A1 (en) | 2006-06-29 |
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