JP2015165527A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2015165527A JP2015165527A JP2014039968A JP2014039968A JP2015165527A JP 2015165527 A JP2015165527 A JP 2015165527A JP 2014039968 A JP2014039968 A JP 2014039968A JP 2014039968 A JP2014039968 A JP 2014039968A JP 2015165527 A JP2015165527 A JP 2015165527A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- metal
- alloy
- copper
- less
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53233—Copper alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Materials Engineering (AREA)
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
第1の実施形態の半導体装置1の構造について図1及び図2を参照して説明する。図1は第1の実施形態に係る半導体装置1の一例を示す模式的平面図であり、図2は図1のA−A’における断面図を示している。
以下に、図2を用いて第2の実施形態について説明する。なお、第2の実施形態について、第1の実施形態と同様の点については説明を省略し、異なる点について説明する。
Claims (8)
- 半導体素子と、
銅を含む配線層を有する実装基板と、
前記半導体素子と前記配線層との間に設けられた銅と銅以外の金属との合金を含み、前記合金の融点が、前記金属の融点よりも高い接合層と、
を備えた半導体装置。 - 前記金属は亜鉛であり、前記合金は銅が40wt%以上、亜鉛が60wt%以下である請求項1に記載の半導体装置。
- 前記金属は亜鉛及びアルミニウムであり、前記合金は銅が40wt%以上、亜鉛が60wt%以下、アルミニウムが亜鉛の20wt%以下である請求項1に記載の半導体装置。
- 前記接合層の厚さは1μm以上100μm以下である請求項2または3に記載の半導体装置。
- 銅を含む配線層の上に銅以外の金属を設ける工程と、
前記金属の上に半導体素子を搭載する工程と、
前記金属を前記金属の融点よりも高い温度に加熱して、前記半導体素子と前記配線層との間で前記金属の融点よりも高く、銅と前記金属から成る合金を形成する工程と、
を備えた半導体装置の製造方法。 - 前記金属は亜鉛であり、前記合金は銅が40wt%以上、亜鉛が60wt%以下である請求項5に記載の半導体装置の製造方法。
- 前記金属は亜鉛及びアルミニウムであり、前記合金は銅が40wt%以上、亜鉛が60wt%以下、アルミニウムが亜鉛の20wt%以下である請求項5に記載の半導体装置の製造方法。
- 前記接合層の厚さを1μm以上100μm以下に形成する請求項6または7に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014039968A JP2015165527A (ja) | 2014-02-28 | 2014-02-28 | 半導体装置及びその製造方法 |
CN201410341174.4A CN104882433A (zh) | 2014-02-28 | 2014-07-17 | 半导体装置及其制造方法 |
US14/448,667 US9466558B2 (en) | 2014-02-28 | 2014-07-31 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014039968A JP2015165527A (ja) | 2014-02-28 | 2014-02-28 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2015165527A true JP2015165527A (ja) | 2015-09-17 |
Family
ID=53949865
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014039968A Pending JP2015165527A (ja) | 2014-02-28 | 2014-02-28 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9466558B2 (ja) |
JP (1) | JP2015165527A (ja) |
CN (1) | CN104882433A (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017118386A1 (de) * | 2017-08-11 | 2019-02-14 | Grohe Ag | Kupferlegierung, Verwendung einer Kupferlegierung, Sanitärarmatur und Verfahren zur Herstellung einer Sanitärarmatur |
WO2021208006A1 (zh) * | 2020-04-16 | 2021-10-21 | 华为技术有限公司 | 封装结构、电动车辆和电子装置 |
TWI829986B (zh) * | 2020-12-28 | 2024-01-21 | 財團法人工業技術研究院 | 積層體及積層體的製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038330A (ja) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5038996A (en) | 1988-10-12 | 1991-08-13 | International Business Machines Corporation | Bonding of metallic surfaces |
DE50011346D1 (de) | 2000-09-07 | 2006-02-23 | Infineon Technologies Ag | Lotmittel zur verwendung bei diffusionslotprozessen |
DE10124770C1 (de) | 2001-05-21 | 2002-10-17 | Infineon Technologies Ag | Verfahren zur Kontaktierung eines elektrischen Bauelementes mit einem eine Leiterstruktur aufweisenden Substrat |
US6727587B2 (en) | 2002-04-30 | 2004-04-27 | Infineon Technologies Ag | Connection device and method for producing the same |
JP5160201B2 (ja) * | 2007-11-20 | 2013-03-13 | 株式会社豊田中央研究所 | はんだ材料及びその製造方法、接合体及びその製造方法、並びにパワー半導体モジュール及びその製造方法 |
JP5376356B2 (ja) | 2008-08-19 | 2013-12-25 | 国立大学法人大阪大学 | 電子素子の実装方法および該実装方法によって実装された電子部品 |
CN101930804A (zh) * | 2008-12-01 | 2010-12-29 | 日立电线株式会社 | 表面处理金属材料及其制造方法 |
JP2010165923A (ja) * | 2009-01-16 | 2010-07-29 | Renesas Electronics Corp | 半導体装置、及びその製造方法 |
JP2010179336A (ja) * | 2009-02-05 | 2010-08-19 | Toyota Central R&D Labs Inc | 接合体、半導体モジュール、及び接合体の製造方法 |
EP2398046A1 (en) * | 2010-06-18 | 2011-12-21 | Nxp B.V. | Integrated circuit package with a copper-tin joining layer and manufacturing method thereof |
JP5601275B2 (ja) | 2010-08-31 | 2014-10-08 | 日立金属株式会社 | 接合材料、その製造方法、および接合構造の製造方法 |
DE102011083931A1 (de) * | 2011-09-30 | 2013-04-04 | Robert Bosch Gmbh | Schichtverbund aus einem elektronischen Substrat und einer Schichtanordnung umfassend ein Reaktionslot |
JP5588419B2 (ja) * | 2011-10-26 | 2014-09-10 | 株式会社東芝 | パッケージ |
-
2014
- 2014-02-28 JP JP2014039968A patent/JP2015165527A/ja active Pending
- 2014-07-17 CN CN201410341174.4A patent/CN104882433A/zh active Pending
- 2014-07-31 US US14/448,667 patent/US9466558B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038330A (ja) * | 2011-08-10 | 2013-02-21 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US9466558B2 (en) | 2016-10-11 |
CN104882433A (zh) | 2015-09-02 |
US20150249046A1 (en) | 2015-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10790214B2 (en) | Circuit substrate and semiconductor device | |
US9807865B2 (en) | Substrate for power modules, substrate with heat sink for power modules, and power module | |
JP5670412B2 (ja) | 合金線材およびその製造方法 | |
WO2014061588A1 (ja) | ヒートシンク付パワーモジュール用基板、ヒートシンク付パワーモジュール、及びヒートシンク付パワーモジュール用基板の製造方法 | |
JP5991102B2 (ja) | ヒートシンク付パワーモジュール用基板、ヒートシンク付パワーモジュール、及びヒートシンク付パワーモジュール用基板の製造方法 | |
JP5991103B2 (ja) | ヒートシンク付パワーモジュール用基板、ヒートシンク付パワーモジュール、及びヒートシンク付パワーモジュール用基板の製造方法 | |
JP2015062953A (ja) | 接合体及びパワーモジュール用基板 | |
JP2015165527A (ja) | 半導体装置及びその製造方法 | |
JP2012160548A (ja) | 絶縁基板とその絶縁基板を有するパワーモジュール | |
JP2022023954A (ja) | セラミックス/アルミニウム接合体、絶縁回路基板、ledモジュール、セラミックス部材 | |
US20190035710A1 (en) | Bonded body, power module substrate, method for manufacturing bonded body, and method for manufacturing power module substrate | |
JP6613144B2 (ja) | 絶縁基板の製造方法 | |
JP6221590B2 (ja) | 絶縁基板と冷却器の接合構造体、その製造方法、パワー半導体モジュール、及びその製造方法 | |
US9123704B2 (en) | Semiconductor device and method for manufacturing the same | |
JP2017028207A (ja) | 熱拡散板およびその製造方法 | |
JP5668506B2 (ja) | パワーモジュール用基板の製造方法及びパワーモジュール用基板 | |
JP2014192272A (ja) | Led用のメタル基板 | |
JP2015072959A (ja) | 絶縁基板と冷却器の接合構造体、その製造方法、パワー半導体モジュール、及びその製造方法 | |
JP2017135374A (ja) | 接合体、パワーモジュール用基板、パワーモジュール、接合体の製造方法及びパワーモジュール用基板の製造方法 | |
JP6116857B2 (ja) | Au系はんだダイアタッチメント半導体装置及びその製造方法 | |
JP6237058B2 (ja) | 銅板付きパワーモジュール用基板、及び銅板付きパワーモジュール用基板の製造方法 | |
JP6848493B2 (ja) | 半導体モジュールとその製造方法 | |
JP2009027158A (ja) | 電子デバイスおよびこれに複数の結合を形成する方法 | |
JP2012178438A (ja) | n型半導体基板にダイボンド用金属層が設けられた構造体およびその製造方法 | |
JP2014150228A (ja) | 積層電極 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160216 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20170125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170127 |
|
RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20170220 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20170714 |