JP5516717B2 - 基板上にパターンを形成する方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Micromachines (AREA)
- Element Separation (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Shaping Of Tube Ends By Bending Or Straightening (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Drying Of Semiconductors (AREA)
Description
Claims (19)
- 基板上にパターンを形成する方法であって、
基板上に、間隔を置いた第一フィーチャを形成することであって、前記間隔を置いた第一フィーチャは相対する側壁を備える、ことと、
前記間隔を置いた第一フィーチャの前記相対する側壁の上に材料を形成することであって、前記材料のうち前記相対する側壁のそれぞれで受けられた部分の組成は前記相対する側壁のそれぞれの組成とは異なる、ことと、
前記材料の前記部分と前記間隔を置いた第一フィーチャのうちの少なくとも一方を緻密化し、前記少なくとも一方を他方から横方向に離れるよう移動させて、前記相対する側壁のそれぞれと前記材料の前記部分との間に空隙空間を形成することと、
を含むことを特徴とする方法。 - 前記間隔を置いた第一フィーチャと前記材料のうちの少なくとも一方がフォトレジストを含む、ことを特徴とする請求項1に記載の方法。
- 前記間隔を置いた第一フィーチャと前記材料のどちらもフォトレジストを含まない、ことを特徴とする請求項1に記載の方法。
- 前記緻密化と前記移動は前記一方のみの緻密化と移動である、ことを特徴とする請求項1に記載の方法。
- 前記緻密化と前記移動は前記一方と前記他方の両方の緻密化と移動である、ことを特徴とする請求項1に記載の方法。
- 前記緻密化は加熱を含む、ことを特徴とする請求項1に記載の方法。
- 前記緻密化は光化学照射を含む、ことを特徴とする請求項1に記載の方法。
- 前記空隙空間は、断面において高さ方向外側が、前記材料によって封止される、ことを特徴とする請求項1に記載の方法。
- 前記材料の一部を除去して、前記空隙空間の高さ方向外側を開口させ、かつ、前記間隔を置いた第一フィーチャから間隔を置き且つ前記間隔を置いた第一フィーチャと交互に並ぶ、切り離された、間隔を置いた第二フィーチャを形成すること、を更に含む、ことを特徴とする請求項8に記載の方法。
- 前記空隙空間は、断面において高さ方向外側が開口している、ことを特徴とする請求項1に記載の方法。
- 前記緻密化の後に、前記材料の側壁の上と、前記第一フィーチャの前記相対する側壁の上に、間隔を置いたスペーサーを形成することと、
前記材料と前記第一フィーチャを、前記間隔を置いたスペーサーに対して選択的に前記基板から除去することと、
前記除去の後に、前記間隔を置いたスペーサーを備えるマスクパターンを介して前記基板を加工することと、
を含むことを特徴とする請求項1に記載の方法。 - 基板上にパターンを形成する方法であって、
基板上に、間隔を置いた第一フィーチャを形成することであって、前記間隔を置いた第一フィーチャは相対する側壁と頂上壁とを備える、ことと、
前記間隔を置いた第一フィーチャの前記相対する側壁及び前記頂上壁の上に材料を形成することであって、前記材料のうち前記相対する側壁のそれぞれと前記頂上壁とで受けられた部分の組成は前記相対する側壁のそれぞれ及び前記頂上壁の組成とは異なる、ことと、
前記材料の前記部分と前記間隔を置いた第一フィーチャのうちの少なくとも一方を緻密化して、少なくとも一つの断面において前記間隔を置いた第一フィーチャのそれぞれの周囲に逆U字形の空隙空間を形成することと、
を含むことを特徴とする方法。 - 前記逆U字形の空隙空間は、前記少なくとも一つの断面において、前記相対する側壁に沿って延びる一対の脚部と、該一対の脚部を互いに連結する、前記頂上壁に沿って延びるベースと、を備え、
前記方法は、前記逆U字形の空隙空間の前記ベースを除去して、前記間隔を置いた第一フィーチャから間隔を置き且つ前記間隔を置いた第一フィーチャと交互に並ぶ、切り離された、間隔を置いた第二フィーチャを形成すること、を更に含む、ことを特徴とする請求項12に記載の方法。 - 基板上にパターンを形成する方法であって、
基板上に、間隔を置いた第一フィーチャを形成することであって、前記間隔を置いた第一フィーチャは、互いに略平行である相対する側壁を備える、ことと、
前記間隔を置いた第一フィーチャの前記相対する側壁の上に材料を形成することであって、前記材料のうち前記相対する側壁のそれぞれで受けられる部分の組成は前記相対する側壁のそれぞれの組成とは異なる、ことと、
前記材料を含み且つ前記間隔を置いた第一フィーチャから間隔を置かれ且つ前記間隔を置いた第一フィーチャの間で受けられる、間隔を置いた第二フィーチャを、前記基板上に形成することであって、前記間隔を置いた第二フィーチャの前記形成は、前記材料の前記部分と前記間隔を置いた第一フィーチャのうちの少なくとも一方を緻密化し、前記少なくとも一方を他方から横方向に離れるよう移動させて、前記相対する側壁のそれぞれと前記材料の前記部分との間に空隙空間を形成する、ことと、
を含むことを特徴とする方法。 - 前記間隔を置いた第一フィーチャの高さ方向最外表面の上を覆って前記材料を形成することを更に含む、ことを特徴とする請求項14に記載の方法。
- 前記材料は、前記緻密化中に、前記間隔を置いた第一フィーチャの前記高さ方向最外表面上で受けられる、ことを特徴とする請求項15に記載の方法。
- 前記緻密化の前に、前記間隔を置いた第一フィーチャの前記高さ方向最外表面上で受けられている前記材料を除去すること、を更に含む、ことを特徴とする請求項15に記載の方法。
- 前記間隔を置いた第二フィーチャを形成した後に、前記間隔を置いた第一フィーチャを横方向にトリミングして、それぞれの幅を狭くすることと、
前記緻密化を完了した後に、前記間隔を置いた第二フィーチャを横方向にトリミングして、それぞれの幅を狭くすることと、
を含むことを特徴とする請求項15に記載の方法。 - 基板上にパターンを形成する方法であって、
基板上に、間隔を置いた第一フィーチャを形成することであって、前記間隔を置いた第一フィーチャは相対する側壁を備える、ことと、
前記間隔を置いた第一フィーチャの前記相対する側壁の上に材料を形成することであって、前記材料のうち前記相対する側壁のうちの少なくとも一方の側壁で受けられた部分の組成は、前記相対する側壁のうちの前記少なくとも一方の側壁の組成とは異なる、ことと、
前記材料の前記部分と前記間隔を置いた第一フィーチャの前記少なくとも一方の側壁のうちの少なくとも一方を緻密化し、前記部分と前記少なくとも一方の側壁のうちの前記少なくとも一方を、前記部分と前記少なくとも一方の側壁のうちの他方から横方向に離れるよう移動させて、前記少なくとも一方の側壁と前記材料の前記部分との間に空隙空間を形成することと、
を含むことを特徴とする方法。
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US12/409,308 US8268543B2 (en) | 2009-03-23 | 2009-03-23 | Methods of forming patterns on substrates |
US12/409,308 | 2009-03-23 | ||
PCT/US2010/025495 WO2010110987A2 (en) | 2009-03-23 | 2010-02-26 | Methods of forming patterns on substrates |
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JP2012521661A JP2012521661A (ja) | 2012-09-13 |
JP5516717B2 true JP5516717B2 (ja) | 2014-06-11 |
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US (2) | US8268543B2 (ja) |
EP (1) | EP2412004B1 (ja) |
JP (1) | JP5516717B2 (ja) |
KR (1) | KR101327577B1 (ja) |
CN (1) | CN102362334B (ja) |
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WO (1) | WO2010110987A2 (ja) |
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US8956808B2 (en) * | 2012-12-04 | 2015-02-17 | Globalfoundries Inc. | Asymmetric templates for forming non-periodic patterns using directed self-assembly materials |
US9213239B2 (en) | 2013-01-22 | 2015-12-15 | Micron Technology, Inc. | Methods of forming patterns for semiconductor device structures |
US8790522B1 (en) | 2013-02-11 | 2014-07-29 | Globalfoundries Inc. | Chemical and physical templates for forming patterns using directed self-assembly materials |
US8999623B2 (en) | 2013-03-14 | 2015-04-07 | Wiscousin Alumni Research Foundation | Degradable neutral layers for block copolymer lithography applications |
US9583381B2 (en) | 2013-06-14 | 2017-02-28 | Micron Technology, Inc. | Methods for forming semiconductor devices and semiconductor device structures |
KR102323456B1 (ko) * | 2014-12-26 | 2021-11-10 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 제조 방법 |
US10147611B1 (en) * | 2017-08-28 | 2018-12-04 | Nanya Technology Corporation | Method for preparing semiconductor structures |
WO2023091734A1 (en) * | 2021-11-22 | 2023-05-25 | Meta Platforms Technologies, Llc | Tunable shrinkage and trim process for fabricating gratings |
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JPH01292829A (ja) * | 1988-05-19 | 1989-11-27 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
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