TWI396227B - 在基板上形成圖案之方法 - Google Patents
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
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Description
本文中所揭示之實施例係關於在基板上形成圖案之方法。
積體電路通常形成於諸如一矽晶圓或其他半導電材料之一半導體基板上。通常,利用係半導電、導電或絕緣之各種材料層來形成積體電路。舉例而言,使用各種製程對該等各種材料進行摻雜、離子植入、沈積、蝕刻、生長等。半導體處理之一持續目標係繼續努力減小個別電子組件之大小,藉此達成較小且較密集之積體電路。
一種用於圖案化及處理半導體基板之技術係光微影。此技術包含沈積通常稱作光阻劑之一可圖案化遮蔽層。此等材料可經處理以改良其在某些溶劑中之可溶性,且藉此可易於用於在一基板上形成圖案。舉例而言,可經由諸如一遮罩或光罩(reticle)之一輻射圖案化工具中之開口使一光阻劑層之部分曝露至光化能,以與沈積後狀態中之可溶性相比改變所曝露區域對未曝露區域之溶劑可溶性。此後,端視光阻劑類型,可移除所曝露區域或未曝露區域,藉此在基板上留下該光阻劑之一遮蔽圖案。可(例如)藉由蝕刻或離子植入來處理下伏基板中緊鄰被遮掩部分之毗鄰區,以實現對毗鄰該遮蔽材料之基板之所期望處理。在某些情形下,利用多個不同光阻劑層及/或光阻劑與非輻射敏感遮蔽材料之一組合。另外,可在不使用光阻劑之情形下在基板上形成圖案。
不斷減小特徵大小對用於形成該等特徵之技術提出越來越高之要求。舉例而言,通常使用光微影來形成圖案化特徵,例如導線。可使用通常稱作「間距」之一概念來描述重複特徵連同緊鄰其之空間的大小。間距可定義為在一直線剖面中一重複圖案之兩個相鄰特徵中之一相同點之間的距離,藉此包含特徵及空間至下一緊鄰特徵之最大寬度。然而,由於諸如光學及光或輻射波長等因素,光微影技術往往具有最小間距,低於此最小間距,一特定光微影技術便無法可靠地形成特徵。因此,一光微影技術之最小間距係使用光微影達成特徵大小不斷減小之一障礙。
間距加倍或間距倍增係一種用於使光微影技術之能力延伸超出其最小間距的建議方法。此方法通常藉由沈積一或多個間隔件形成層來形成窄於最小光微影解析度之特徵以具有小於最小可光微影特徵大小之一總體橫向厚度。通常各向異性地蝕刻該等間隔件形成層以形成次微影特徵,且然後自基板蝕刻形成為最小光微影特徵大小之該等特徵。
使用其中間距實際上減半之此技術,此間距減小通常稱作間距「加倍」。更一般而言,「間距倍增」囊括將間距增加兩倍或更多倍,且亦囊括將間距增加除整數以外之分數值。因此,傳統上,將間距「倍增」某一因數實際上涉及使間距減小彼因數。
參照圖1至24描述本發明某些實施例之在基板上形成圖案之實例性方法。參照圖1,通常使用參考編號10指示一基板片段。此可包括一半導體基板或其他基板。在本文件之上下文中,術語「半導體基板」或「半導電基板」係定義為意指包括半導電材料之任一構造,該半導電材料包含但不限於諸如一半導電晶圓之體半導電材料(單獨或在其上包括其他材料之總成中)及半導電材料層(單獨或在包括其他材料之總成中)。術語「基板」係指任一支撐結構,其包含但不限於上述半導電基板。
基板片段10包括基板材料12,例如,其可為同質或非同質材料且包含導電、半導電及絕緣材料中之任一者。舉例而言,此可用於製造積體電路。間隔開之第一特徵14已形成於基板12上方,且亦可為同質或非同質特徵。間隔開之第一特徵14可部分地或完全地為犧牲特徵,且因此可包括或可不包括其中製造有電路之一成品電路構造的一部分。可藉由任一現有或尚待開發技術來製造間隔開之第一特徵14。實例包含微影,例如光微影。可將間隔開之第一特徵14圖案化為製造基板10之最小光微影解析度、大於該最小光微影解析度或小於該最小光微影解析度。間隔開之第一特徵14係展示為具有相同之形狀及相對於另一者之間隔且剖面為大體矩形。可使用該等特徵形狀中之其他形狀、不同形狀及兩個或更多個不同間隔。間隔開之第一特徵14中之個別特徵可視為包括相對橫向側壁16及一沿立面最外之頂壁或表面18。在一項實施例中,側壁16大體彼此平行。在一項實施例中,側壁16大體彼此平行且相對於基板12大體垂直延伸。
參照圖2,已將材料形成至間隔開之第一特徵14之相對橫向側壁16上及間隔開之第一特徵14之沿立面最外之表面/頂壁18上方。材料20可為同質材料或可非為同質材料,而無論可否形成其中製造有積體電路之成品積體電路構造之一部分。無論如何,材料20之經接納抵靠在相對橫向側壁16中之每一者上之彼部分的組合物不同於相對橫向側壁16中之每一者之組合物。另外,在材料20被接納於最高處表面/頂壁18上方且抵靠其之情形下,材料20之經接納抵靠在一表面/壁18上之彼部分的組合物可不同於表面/壁18之組合物。出於繼續論述之目的,材料20及間隔開之第一特徵14可視為在各別界面22處彼此接觸。在此等界面22處接觸之材料20之彼等部分及間隔開之第一特徵14之實例性組合物更詳細地描述於下文中。
參照圖3及4,使材料20之經接納抵靠在橫向側壁16上之部分及間隔開之第一特徵14中之至少一者緻密化,以使材料20之此部分或間隔開之第一特徵14中之至少一者移動遠離另一者,以在相對橫向側壁16中之每一者與材料20之先前經接納抵靠在其上之部分之間形成一空隙空間25。圖3及4繪示其中已緻密化材料20及間隔開之第一特徵14二者以使得每一者之材料皆橫向移動遠離界面22之一實例性實施例。圖3亦繪示使材料20之抵靠在頂壁18上之部分或間隔開之特徵14中之至少一者緻密化,以使得空隙空間25延伸跨越每一間隔開之第一特徵14之頂壁18且在其上方延伸。在一項實施例中,舉例而言,如圖3中所示,基板10已經處理以在實例性繪示之剖面中將空隙空間25形成為一倒置大體U形(具有一基底27),且接納於間隔開之第一特徵14中之每一者周圍。緻密化後材料20之組合物及/或間隔開之第一特徵14之材料之組合物在緻密化後可與任一者在緻密化前之此等組合物相同或不同。無論如何,端視各種材料之組合物,所形成之空隙空間可僅接納於一個橫向側壁16或兩個橫向側壁16與材料20之先前經接納抵靠在其上之部分之間,而並不形成於特徵14之頂部上。
無論如何,圖3繪示在基板12上方形成之一實例性圖案28。圖案28可視為包括互連之間隔開之第二特徵30(其包括材料20),其中間隔開之第二特徵30與間隔開之第一特徵14間隔開且接納於間隔開之第一特徵14之間。
圖5及6繪示替代實例性實施例基板片段10a及10b。在適當處使用來自第一所述實施例之相同編號,其中某些構造差別分別係以後置字「a」及「b」指示。圖5繪示其中僅材料20之先前接納在界面22處之彼部分已橫向移動遠離間隔開之第一特徵材料14a之另一者以形成空隙空間25a之一實例。圖6繪示其中僅先前接納在界面22處之間隔開之第一特徵材料14已橫向移動遠離界面22之一實例。因此,緻密化及移動以形成空隙空間25a或25b之動作係由僅一種材料相對於另一者之緻密化及移動而產生,此與圖3及4之實施例中所示之兩者相反。
圖7繪示另一實例性實施例基板片段10c。在適當處使用來自上述實施例之相同編號,其中某些構造差別係以後置字「c」指示。在圖7中,間隔開之第一特徵材料14c實際上已擴展(藉此減小其密度),且朝向材料20之先前接納在界面22處之部分移動。材料20之緻密化已大於特徵14c之材料之擴展以便形成一空隙空間25c。此當然可顛倒,舉例而言,其中致使材料20擴展且致使材料14以大於材料20擴展之速率緻密化(圖中未繪示)以形成一空隙空間。
熟習此項技術者可選擇材料20及間隔開之第一特徵14之不同組合物,以使一種材料或兩種材料能夠相對於另一者緻密化,以便形成一空隙空間。另外,端視所選材料,可以不同方式來達成緻密化。舉例而言,間隔開之第一特徵14及材料20中之一者或兩者可包括不同組合物光阻劑。可(例如)藉由對圖2之實例性基板進行光化輻射而發生一者或兩者相對於另一者緻密化以形成一空隙空間,及/或可藉由加熱圖2之基板而發生緻密化。理想地,緻密化係在不存在對基板10之材料之任一蝕刻下發生以便僅藉由緻密化發生空隙形成。
作為一額外實例,某些澆注聚合物可收縮且藉此藉由一可自其驅走溶劑之退火來加以緻密化。舉例而言,第一特徵14可包括任一適合光阻劑,其中其上方所形成之材料20包括聚甲基丙烯酸甲酯。舉例而言,將圖2中由聚甲基丙烯酸甲酯20及光阻劑14構成之基板在至少50℃之一溫度下(理想地為自100℃至130℃)加熱達約60秒至90秒將導致對任一者之緻密化以及空隙空間25之相稱形成。另外,作為一實例,若第一特徵14係抗蝕劑或任一聚合物,則在其上方形成材料20之前可或可不對其進行處理以致該處理使得第一特徵14不溶於自其溶劑(旋轉)澆注出材料20(若材料20係來自溶劑澆注)之溶劑中。實例性處理包含用於雙重圖案化中之習用抗蝕劑「冷凍」技術,例如熱交聯、光交聯、熱生成酸隨後光誘導酸催化聚合或在第一特徵14上方形成一保護囊封層,舉例而言,藉由(例如)氧化物原子層沈積來形成一不溶性化學塗層或形成一不溶性薄塗層。
亦可藉由使某些材料反應來發生緻密化與相稱體積變化,舉例而言,藉由材料之熱裂解或酸水解,例如將聚丙烯酸第三丁基酯轉化成聚丙烯酸。在反應時發生緻密化及體積變化之其他實例性材料包含熱可固化之環氧樹脂,例如乙烯基酯、不飽和聚酯及其摻合物。此等材料可(例如)使用在100℃或低於100℃下之適合高溫來加以固化。其他環氧樹脂及其摻合物可在(例如)自120℃至500℃之更高溫度下加以固化。在此等材料用於所有或某些材料20之情形下,第一特徵14可不包括光阻劑或不能夠在該等溫度下經受處理而不熔化之其他材料。因此,在此等情形下,間隔開之第一特徵14可由任一適合之現有或尚待開發之硬遮罩材料製造而成,該硬遮罩材料本身先前已利用光微影及/或以其他方式進行圖案化。
亦可藉由光化輻照來發生緻密化及相稱體積變化,例如藉由在存在光激活自由基或陽離子起始劑之情形下將丙烯酸酯或環氧單體或預聚物光聚合。舉例而言,使用可見光將胺基甲酸酯二甲基丙烯酸酯光聚合以賦予一緻密化及5.3%之體積收縮。類似地,單體或預聚物本身可係光敏性且可不存在一單獨起始劑物質。實例包含完全醯亞胺化、可溶、自身具有光敏性之聚醯亞胺。無論如何,此等實例性光阻劑可為正性光阻劑或負性光阻劑。
作為其他實例,因將光化學過程之副產物脫氣,故可致使某些正性光阻劑收縮,該光化學過程包含自抗蝕劑分子移除保護基團。一實例係第三丁氧基羰基、乙縮醛、或丙烯酸第三丁基酯基團(包含其共聚物,例如,包括羥基苯乙烯單體)之去保護。光裂解或酸裂解之保護基團在曝露及/或曝露後烘烤期間可自抗蝕劑膜脫氣。藉由脫氣使正性光阻劑緻密化之額外實例包含在光酸生成過程中於化學增幅抗蝕劑中形成副產物。實例包含其中光酸產生劑分子係鎓鹽(例如全氟磺酸鋶)、及其中在光解期間生成之陰離子及反應陽離子之殘餘物可在曝露及/或曝露後烘烤期間自抗蝕劑膜脫氣之情況。
在適合處理時能夠發生緻密化及相稱體積變化之其他實例性材料包含熱敏聚合物凝膠,例如水凝膠,例如聚(N-異丙基丙烯醯胺)。熱敏水凝膠在低於其低臨界溶解溫度時膨脹且在高於其低臨界溶解溫度時收縮。對於聚(N-異丙基丙烯醯胺)而言,此因隨著溫度改變可逆地形成及裂解NH或C=O基團與周圍水分子之間之氫鍵而發生。某些熱敏水凝膠之其他水凝膠觸發刺激(除溫度外)包含電場、pH、及/或第三體溶質濃度。
其他實例性材料包含彼等可熱收縮者,例如收縮纏繞材料。可使用在膜澆注期間經由剪切稀化提供之拉伸來沈積該等材料。實例性材料包含線性分子,例如聚氯乙烯或聚烯烴(例如聚乙烯)。其他實例包含分段嵌段共聚物及彈性體-塑膠摻合物,例如,乙烯與乙酸乙烯酯之一共聚物,包含其摻合物。可在一塗覆後熱烘烤期間發生緻密化及相稱體積變化以形成空隙,其中(例如)向經拉伸之聚合物分子賦予流動性且其收縮至一平衡捲曲組態。
可經處理賦予緻密化且藉此賦予體積變化以形成一空隙空間之額外實例性材料包含可逆摻雜之共軛聚合物,例如聚吡咯。此等材料在其摻雜及未摻雜期間發生可逆之體積變化。舉例而言,可將一導電可逆摻雜共軛聚合物(例如聚吡咯)浸於一電解質溶液中。在向聚合物施加一適合電壓(電場)時,離子在聚合物與電解質之間進行交換。因在此發生電荷及質量傳輸,故聚合物藉由緻密化而產生多達幾個百分比之體積變化。舉例而言,在聚吡咯中,體積變化主要係由於鏈因摻雜劑插入或提取而發生物理分離所致。若自聚合物排除離子,則聚合物發生收縮且密度增加。
僅舉例而言,可選擇各種上述材料及技術來至少用於間隔開之第一特徵14及材料20中在界面22處相對於另一者接觸之彼等部分以形成期望之適合空隙空間25/25a/25b/25c。無論如何,為空隙形成提供核心之界面22理想地可在收縮過程期間促進去濕潤或分離,或至少不涉及一種材料相對於另一者之牢固黏著。在一實例中,為空隙形成提供核心之界面理想地係化學上特定界面以促進不同組合物材料在緻密化過程期間之去濕潤或分離。舉例而言,相對橫向側壁16及/或頂壁18可在其上沈積材料20之前或期間進行處理。表面16/18之化學剪裁可包含經由氟電漿蝕刻來選擇性形成氟碳聚合物。另外,諸多光阻劑材料之氟化組份之擴散及表面遷移可固有地促進去濕潤或分離。此外或另一選擇,可將官能化自組裝單體選擇性地沈積於間隔開之第一特徵14之表面上然後沈積材料20。理想地,收縮材料與下伏基板間之界面應使得該收縮材料與該下伏基板間之接觸角為約90°,此可經由或可不經由對欲緻密化之材料實施單獨化學官能化來達成。
圖3繪示其中在所繪示剖面中藉由材料22沿立面向外密封初始形成之後的空隙空間25之一實例。參照圖8,已移除材料20中之某些材料以在空隙空間25初始形成之後沿立面向外敞開該空隙空間。此形成一圖案32,其中間隔開之第二特徵30與間隔開之第一特徵14分離且間隔開並交替。因此,圖8繪示對圖3之圖案28之改良以在基板12上形成一圖案32。無論如何,可發生交替處理。
舉例而言,圖2至4繪示其中在緻密化動作期間將材料20沿立面接納於間隔開之第一特徵14之最外表面18上方以形成空隙空間25的一實施例。另一選擇係,可在緻密化期間移除材料20而使其不接納於間隔開之第一特徵14之沿立面最外之表面上方。舉例而言,圖9繪示一基板片段10d。在適當處使用來自第一所述實施例之相同編號,其中某些構造差別係以後置字「d」指示。此繪示對由圖2所繪示者之後續處理,其中已對材料20進行化學蝕刻、拋光或以其他方式向內移除以至少到達間隔開之第一特徵14之沿立面最外之表面18。此後可對圖9基板之緻密化進行處理以直接產生圖8之基板。因此,在此實例性實施例中,所形成之空隙空間25在初始形成之後在剖面係沿立面向外敞開的,舉例而言,此將在緻密化期間不將材料接納於間隔開之第一特徵14之沿立面最外之表面18上方時發生。
在基板10上方形成之圖案32可包括或可不包括基板10之成品構造之一部分。另外,無論如何,可隨後改良圖案32。舉例而言,可橫向修整圖8之間隔開之第一特徵14及間隔開之第二特徵30中之一者或兩者以減小其各別寬度。圖10繪示其中已橫向修整間隔開之第二特徵30及間隔開之第一特徵14中之每一者之各別寬度(例如,藉由適合之濕式及/或乾式化學蝕刻)以減小其各別寬度的一實例性實施例圖案34。端視圖8中間隔開之第一特徵14及間隔開之第二特徵30之組合物,可使用一單一化學物同時發生圖10之橫向修整。另一選擇係或此外,可使用不同蝕刻化學物在不同時間發生間隔開之第一特徵14及間隔開之第二特徵30之橫向修整,其中橫向修整之此動作係相對於任一者在另一者之前發生。另外,可僅修整此等間隔開之特徵中之一者或二者皆不修整。另外,圖1之間隔開之第一特徵14可在形成之後且在其上方沈積材料20之前進行橫向修整。
本發明實施例亦可包括經由包括間隔開之第一特徵及由其形成間隔開之第二特徵之材料之一遮罩圖案來處理基板。圖11繪示一個此種實例,其中已藉由經由由圖案34構成之一遮罩圖案進行蝕刻以蝕刻至材料12中來處理基板10。此外或另一選擇係,可實施任一替代現有或尚待開發之處理,例如,摻雜、離子植入、選擇性沈積等。
接下來針對圖12至15中之一基板10e來描述替代或額外處理。在適當處使用來自第一所述實施例之相同編號,其中某些構造差別係以後置字「e」或不同編號指示。參照圖12,已形成包括間隔開之第一特徵14e及間隔開之第二特徵30e之一圖案34e。可根據針對間隔開之第一特徵14及間隔開之第二特徵30之任一上述技術來製造此圖案。
參照圖13,已在特徵14e及30e上方沈積一間隔件形成層40。可包括可由其選擇性地蝕刻出特徵14e及特徵30e之一材料。在本文件之上下文中,一選擇性蝕刻需要將一種材料相對於另一者以至少2:1之一比率移除。已將間隔件形成層40沈積至不足以填充緊鄰間隔件14e與30e之間的空間的一厚度。
參照圖14,已各向異性地蝕刻間隔件形成層40以在第一特徵14e及第二特徵30e之材料之橫向側壁上方形成間隔開之間隔件42。
參照圖15,已端視材料14e、30e及42之組合物使用(例如)任一適合蝕刻化學物相對於間隔開之間隔件42自基板選擇性地移除間隔開之第一特徵14e(圖中未繪示)及間隔開之第二特徵30e(圖中未繪示)。藉此,已在基板12上形成一圖案44。此圖案可或可不在隨後經由其處理基板12中用作一遮罩圖案。
參照圖16至24中之一基板10f描述另一實例性實施例。在適當處使用來自第一所述實施例之相同編號,其中某些構造差別係以後置字「f」或不同編號指示。圖16繪示間隔開之遮罩特徵50之形成,舉例而言,該等間隔開之遮罩特徵包括光阻劑、基本上由其組合物或由其組合物。已在基板12上方以一間距「P」之一重複圖案製造遮罩特徵50。遮罩特徵50可包括除光阻劑以外之材料。無論如何,間距P可等於、大於或小於製造基板10f之最小光微影解析度。
參照圖17,已橫向修整遮罩特徵50以減小其各別寬度。
參照圖18,已在基板12上方(包含在間隔開之特徵50上方)沈積一間隔件形成層52。
參照圖19,已各向異性地蝕刻間隔件形成層52以在間隔開之特徵50之側壁周圍形成間隔開之第一特徵14f。
參照圖20,已相對於間隔開之第一特徵14f自基板選擇性地移除間隔開之特徵50(圖中未繪示)。
參照圖21,已形成材料20f。間隔開之第一特徵14f之材料52及材料20f之組合物對應於如上所述之材料14及20之組合物。
參照圖22,已使材料20f之毗鄰材料52之部分及間隔開之第一特徵14f中之至少一者緻密化以橫向移動遠離其界面。此形成一空隙空間25f,其至少接納於間隔開之第一特徵14f之相對橫向側壁中之每一者與材料20f之間,且形成一圖案28f。
參照圖23,已移除材料20f之最外部分以向外敞開空隙空間25f。此形成分離之間隔件30f及一圖案32f。
參照圖24,已橫向修整材料20f以減小其各別寬度。間隔開之第一特徵14f係展示為尚未進行橫向修整。無論如何,繪示在基板12上方形成一圖案60。圖案60係繪示為具有係圖16中間隔開之遮罩特徵50之間距「P」之1/4(4的整數倍)的一間距。
上述實施例中之任一實施例中之任一程度之間距減小(包含非整數之分數減小)(若發生)當然將在很大程度上取決於任一橫向修整之程度,該任一橫向修整可針對各別間隔開之特徵與沈積層厚度之組合發生以產生特徵及位於各特徵之間的空間。
按照條例,已使用或多或少關於結構及方法特徵之特定語言描述了本文中所揭示之標的物。然而,應理解,由於本文所揭示之方法包括實例性實施例,故申請專利範圍不限於所展示及描述之具體特徵。因此,申請專利範圍係由字面措辭來提供完整範疇,且根據等效內容之教義適當地予以解釋。
10...基板片段
10a...基板片段
10b...基板片段
10c...基板片段
10d...基板片段
10e...基板
10f...基板
12...基板材料
14...間隔開之第一特徵
14a...間隔開之第一特徵材料
14c...間隔開之第一特徵材料
14e...間隔開之第一特徵
14f...間隔開之第一特徵
16...相對橫向側壁
18...頂壁或表面
20...材料
20f...材料
22...界面
25...空隙空間
25a...空隙空間
25b...空隙空間
25c...空隙空間
25f...空隙空間
27...基底
28...圖案
28f...圖案
30...互連之間隔開之第二特徵
30e...間隔開之第二特徵
30f...分離之間隔件
32...圖案
32f...圖案
34...圖案
34e...圖案
40...間隔件形成層
42...間隔開之間隔件
44...圖案
50...間隔開之遮罩特徵
52...間隔件形成層
60...圖案
圖1係本發明一實施例之製程中之基板之一示意性剖視圖。
圖2係繼圖1所展示步驟之後的一處理步驟處之圖1基板之一視圖。
圖3係繼圖2所展示步驟之後的一處理步驟處之圖2基板之一視圖。
圖4係圖3基板之一部分之一放大視圖。
圖5係一替代實施例基板之一視圖,且對應於圖4之基板之比例及位置。
圖6係一替代實施例基板之一視圖,且對應於圖4之基板之比例及位置。
圖7係一替代實施例基板之一視圖,且對應於圖4之基板之比例及位置。
圖8係繼圖3所展示步驟之後的一處理步驟處之圖3基板之一視圖。
圖9係一替代實施例基板之一視圖。
圖10係繼圖8所展示步驟之後的一處理步驟處之圖8基板之一視圖。
圖11係繼圖10所展示步驟之後的一處理步驟處之圖10基板之一視圖。
圖12係一替代實施例基板之一視圖。
圖13係繼圖12所展示步驟之後的一處理步驟處之圖12基板之一視圖。
圖14係繼圖13所展示步驟之後的一處理步驟處之圖13基板之一視圖。
圖15係繼圖14所展示步驟之後的一處理步驟處之圖14基板之一視圖。
圖16係一替代實施例基板之一視圖。
圖17係繼圖16所展示步驟之後的一處理步驟處之圖16基板之一視圖。
圖18係繼圖17所展示步驟之後的一處理步驟處之圖17基板之一視圖。
圖19係繼圖18所展示步驟之後的一處理步驟處之圖18基板之一視圖。
圖20係繼圖19所展示步驟之後的一處理步驟處之圖19基板之一視圖。
圖21係繼圖20所展示步驟之後的一處理步驟處之圖20基板之一視圖。
圖22係繼圖21所展示步驟之後的一處理步驟處之圖21基板之一視圖。
圖23係繼圖22所展示步驟之後的一處理步驟處之圖22基板之一視圖。
圖24係繼圖23所展示步驟之後的一處理步驟處之圖23基板之一視圖。
10...基板片段
12...基板材料
14...間隔開之第一特徵
16...相對橫向側壁
18...頂壁或表面
20...材料
22...界面
25...空隙空間
27...基底
28...圖案
30...互連之間隔開之第二特徵
Claims (35)
- 一種在一基板上形成一圖案之方法,其包括:在一基板上方形成間隔開之第一特徵,該等間隔開之第一特徵包括相對橫向側壁;將材料形成至該等間隔開之第一特徵之該等相對橫向側壁上,該材料之經接納抵靠在該等相對橫向側壁中之每一者上之彼部分之組合物不同於該等相對橫向側壁中之每一者之組合物;及使該材料之該部分及該等間隔開之第一特徵中之至少一者緻密化以使該至少一者橫向移動遠離該至少一者之另一者,以在該等相對橫向側壁中之每一者與該材料之該部分之間形成一空隙空間。
- 如請求項1之方法,其中該等間隔開之第一特徵及該材料中之至少一者包括光阻劑。
- 如請求項1之方法,其中該等間隔開之第一特徵及該材料兩者皆包括光阻劑。
- 如請求項1之方法,其中該等間隔開之第一特徵及該材料中之任一者皆不包括光阻劑。
- 如請求項1之方法,其中該緻密化及該移動係僅針對一者。
- 如請求項5之方法,其中該緻密化及該移動係針對該等間隔開之第一特徵。
- 如請求項5之方法,其中該緻密化及該移動係針對該材料。
- 如請求項5之方法,其中該另一者擴展以減小其密度並朝向該一者移動。
- 如請求項1之方法,其中該緻密化及該移動係針對該一者及該另一者兩者。
- 如請求項1之方法,其中該緻密化包括加熱。
- 如請求項10之方法,其中該緻密化係在不存在蝕刻之情形下進行。
- 如請求項1之方法,其中該緻密化包括光化輻照。
- 如請求項1之方法,其中在剖面中藉由該材料沿立面向外密封初始形成之後的該空隙空間。
- 如請求項13之方法,其包括移除該材料中之某些材料以在該空隙空間初始形成之後沿立面向外敞開該空隙空間並形成分離之間隔開之第二特徵,該等間隔開之第二特徵與該等間隔開之第一特徵間隔開且交替。
- 如請求項1之方法,其中初始形成之後的該空隙空間在剖面中係沿立面向外敞開的。
- 如請求項1之方法,其中在該緻密化期間將該材料接納於該等間隔開之第一特徵之沿立面最外之表面上方。
- 如請求項1之方法,其中在該緻密化期間不將該材料接納於該等間隔開之第一特徵之沿立面最外之表面上方。
- 如請求項1之方法,其中在該緻密化期間不將材料接納於該等間隔開之第一特徵之沿立面最外之表面上方。
- 如請求項1之方法,其包括在該緻密化之後經由包括該等間隔開之第一特徵及該材料之一遮罩圖案處理該基板。
- 如請求項1之方法,其包括:在該緻密化之後,在該材料之橫向側壁上方及該等第一特徵之該等相對橫向側壁上方形成間隔開之間隔件;相對於該等間隔開之間隔件自該基板選擇性地移除該材料及該等第一特徵;及在該移除之後,經由包括該等間隔開之間隔件之一遮罩圖案處理該基板。
- 一種在一基板上形成一圖案之方法,其包括:在一基板上方形成間隔開之第一特徵,該等間隔開之第一特徵包括相對橫向側壁及一頂壁;將材料形成至該等間隔開之第一特徵之該等相對橫向側壁及該頂壁上,該材料之經接納抵靠在該等相對橫向側壁中之每一者及該頂壁上之彼部分之組合物不同於該等相對橫向側壁中之每一者及該頂壁之組合物;及處理該基板以在至少一個剖面中在該等間隔開之第一特徵中之每一者周圍形成一倒置大體U形空隙空間。
- 如請求項21之方法,其包括移除該倒置大體U形空隙空間之一基底以形成分離之間隔開之第二特徵,該等間隔開之第二特徵與該等間隔開之第一特徵間隔開且交替。
- 如請求項22之方法,其包括橫向修整該等分離之間隔開之第二特徵以減小其各別寬度。
- 如請求項22之方法,其包括在該移除之後橫向修整該等間隔開之第一特徵以減小其各別寬度。
- 一種在一基板上形成一圖案之方法,其包括:在一基板上方形成間隔開之第一特徵,該等間隔開之第一特徵包括大體彼此平行之相對橫向側壁;將材料形成至該等間隔開之第一特徵之該等相對橫向側壁上,該材料之經接納抵靠在該等相對橫向側壁中之每一者上之彼部分之組合物不同於該等相對橫向側壁中之每一者之組合物;及在該基板上方形成間隔開之第二特徵,該等間隔開之第二特徵包括該材料且與該等間隔開之第一特徵間隔開並接納於該等間隔開之第一特徵之間,該等間隔開之第二特徵之該形成包括使該材料之該部分及該等間隔開之第一特徵中之至少一者緻密化以使該至少一者橫向移動遠離該至少一者之另一者,以在該等相對橫向側壁中之每一者與該材料之該部分之間形成一空隙空間。
- 如請求項25之方法,其中該等間隔開之第一特徵係同質特徵。
- 如請求項25之方法,其包括在該等間隔開之第一特徵之沿立面最外之表面上方形成該材料。
- 如請求項27之方法,其中在該緻密化期間將該材料接納於該等間隔開之第一特徵之沿立面最外之表面上方。
- 如請求項27之方法,其包括在該緻密化之前移除該材料而使其不接納於該等間隔開之第一特徵之沿立面最外之表面上方。
- 如請求項27之方法,其包括在形成該等間隔開之第二特徵之後橫向修整該等間隔開之第一特徵以減小其各別寬度。
- 如請求項27之方法,其包括在完成該緻密化之後橫向修整該等間隔開之第二特徵以減小其各別寬度。
- 如請求項27之方法,其包括:在形成該等間隔開之第二特徵後,橫向修整該等間隔開之第一特徵以減小其各別寬度;及在完成該緻密化之後,橫向修整該等間隔開之第二特徵以減小其各別寬度。
- 如請求項32之方法,其包括在橫向修整該等間隔開之第一特徵之後橫向修整該等間隔開之第二特徵。
- 如請求項32之方法,其包括在橫向修整該等間隔開之第一特徵之前橫向修整該等間隔開之第二特徵。
- 如請求項32之方法,其包括同時橫向修整該等間隔開之第一特徵及第二特徵。
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8791447B2 (en) | 2011-01-20 | 2014-07-29 | Micron Technology, Inc. | Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells |
US20140110805A1 (en) | 2012-10-18 | 2014-04-24 | Infineon Technologies Dresden Gmbh | Silicon light trap devices, systems and methods |
US8956808B2 (en) * | 2012-12-04 | 2015-02-17 | Globalfoundries Inc. | Asymmetric templates for forming non-periodic patterns using directed self-assembly materials |
US9213239B2 (en) | 2013-01-22 | 2015-12-15 | Micron Technology, Inc. | Methods of forming patterns for semiconductor device structures |
US8790522B1 (en) | 2013-02-11 | 2014-07-29 | Globalfoundries Inc. | Chemical and physical templates for forming patterns using directed self-assembly materials |
US8999623B2 (en) | 2013-03-14 | 2015-04-07 | Wiscousin Alumni Research Foundation | Degradable neutral layers for block copolymer lithography applications |
US9583381B2 (en) | 2013-06-14 | 2017-02-28 | Micron Technology, Inc. | Methods for forming semiconductor devices and semiconductor device structures |
KR102323456B1 (ko) * | 2014-12-26 | 2021-11-10 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 제조 방법 |
US10147611B1 (en) * | 2017-08-28 | 2018-12-04 | Nanya Technology Corporation | Method for preparing semiconductor structures |
WO2023091734A1 (en) * | 2021-11-22 | 2023-05-25 | Meta Platforms Technologies, Llc | Tunable shrinkage and trim process for fabricating gratings |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030006410A1 (en) * | 2000-03-01 | 2003-01-09 | Brian Doyle | Quantum wire gate device and method of making same |
US20040198065A1 (en) * | 2003-04-04 | 2004-10-07 | Sung-Kwon Lee | Method for fabricating semiconductor device with fine patterns |
US20070202697A1 (en) * | 2006-02-24 | 2007-08-30 | Hynix Semiconductor Inc. | Method for forming fine pattern of semiconductor device |
TW200814140A (en) * | 2006-09-12 | 2008-03-16 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
US20080305636A1 (en) * | 2007-06-07 | 2008-12-11 | Samsung Electronics Co., Ltd. | Method of forming fine pattern employing self-aligned double patterning |
Family Cites Families (217)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE900156A (fr) | 1984-07-13 | 1985-01-14 | Itt Ind Belgium | Procede pour superposer deux couches de vernis photosensibles positifs. |
JPH01292829A (ja) * | 1988-05-19 | 1989-11-27 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPH02266517A (ja) * | 1989-04-06 | 1990-10-31 | Rohm Co Ltd | 半導体装置の製造方法 |
US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US5047117A (en) | 1990-09-26 | 1991-09-10 | Micron Technology, Inc. | Method of forming a narrow self-aligned, annular opening in a masking layer |
US5420067A (en) * | 1990-09-28 | 1995-05-30 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricatring sub-half-micron trenches and holes |
US5382315A (en) * | 1991-02-11 | 1995-01-17 | Microelectronics And Computer Technology Corporation | Method of forming etch mask using particle beam deposition |
US5372916A (en) | 1991-09-12 | 1994-12-13 | Hitachi, Ltd. | X-ray exposure method with an X-ray mask comprising phase shifter sidewalls |
US5703675A (en) * | 1992-01-17 | 1997-12-30 | Nikon Corporation | Projection-exposing apparatus with deflecting grating member |
US5573837A (en) | 1992-04-22 | 1996-11-12 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5254218A (en) | 1992-04-22 | 1993-10-19 | Micron Technology, Inc. | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer |
US5386132A (en) | 1992-11-02 | 1995-01-31 | Wong; Chun C. D. | Multimedia storage system with highly compact memory device |
JP3270227B2 (ja) | 1993-05-26 | 2002-04-02 | 富士写真フイルム株式会社 | 電動巻き上げ装置 |
US5429988A (en) * | 1994-06-13 | 1995-07-04 | United Microelectronics Corporation | Process for producing high density conductive lines |
KR970007173B1 (ko) * | 1994-07-14 | 1997-05-03 | 현대전자산업 주식회사 | 미세패턴 형성방법 |
US5905279A (en) * | 1996-04-09 | 1999-05-18 | Kabushiki Kaisha Toshiba | Low resistant trench fill for a semiconductor device |
US7064376B2 (en) * | 1996-05-24 | 2006-06-20 | Jeng-Jye Shau | High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines |
US5998256A (en) * | 1996-11-01 | 1999-12-07 | Micron Technology, Inc. | Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry |
TW454339B (en) | 1997-06-20 | 2001-09-11 | Hitachi Ltd | Semiconductor integrated circuit apparatus and its fabricating method |
JP2006245625A (ja) | 1997-06-20 | 2006-09-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6207523B1 (en) * | 1997-07-03 | 2001-03-27 | Micron Technology, Inc. | Methods of forming capacitors DRAM arrays, and monolithic integrated circuits |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
KR100247862B1 (ko) * | 1997-12-11 | 2000-03-15 | 윤종용 | 반도체 장치 및 그 제조방법 |
US6087263A (en) * | 1998-01-29 | 2000-07-11 | Micron Technology, Inc. | Methods of forming integrated circuitry and integrated circuitry structures |
US6605541B1 (en) | 1998-05-07 | 2003-08-12 | Advanced Micro Devices, Inc. | Pitch reduction using a set of offset masks |
US6140217A (en) | 1998-07-16 | 2000-10-31 | International Business Machines Corporation | Technique for extending the limits of photolithography |
US6303272B1 (en) | 1998-11-13 | 2001-10-16 | International Business Machines Corporation | Process for self-alignment of sub-critical contacts to wiring |
EP1039533A3 (en) | 1999-03-22 | 2001-04-04 | Infineon Technologies North America Corp. | High performance dram and method of manufacture |
US6667502B1 (en) | 1999-08-31 | 2003-12-23 | Micron Technology, Inc. | Structurally-stabilized capacitors and method of making of same |
KR100620651B1 (ko) | 2000-06-22 | 2006-09-13 | 주식회사 하이닉스반도체 | 반도체 소자의 미세패턴 제조방법 |
US6339241B1 (en) | 2000-06-23 | 2002-01-15 | International Business Machines Corporation | Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch |
KR100340879B1 (ko) | 2000-06-29 | 2002-06-20 | 박종섭 | 반도체 소자의 미세 패턴 형성방법 및 이를 이용한 게이트 전극 형성방법 |
JP3406302B2 (ja) | 2001-01-16 | 2003-05-12 | 株式会社半導体先端テクノロジーズ | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 |
US6580136B2 (en) * | 2001-01-30 | 2003-06-17 | International Business Machines Corporation | Method for delineation of eDRAM support device notched gate |
US6383952B1 (en) | 2001-02-28 | 2002-05-07 | Advanced Micro Devices, Inc. | RELACS process to double the frequency or pitch of small feature formation |
CA2340985A1 (en) | 2001-03-14 | 2002-09-14 | Atmos Corporation | Interleaved wordline architecture |
US6545904B2 (en) * | 2001-03-16 | 2003-04-08 | Micron Technology, Inc. | 6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array |
TW527592B (en) * | 2001-03-19 | 2003-04-11 | Matsushita Electric Ind Co Ltd | Optical information recording media, and the manufacturing method and record regeneration method of the same |
JP2002299202A (ja) * | 2001-03-29 | 2002-10-11 | Sony Corp | 半導体装置の製造方法 |
US6627524B2 (en) | 2001-06-06 | 2003-09-30 | Micron Technology, Inc. | Methods of forming transistor gates; and methods of forming programmable read-only memory constructions |
US20030008968A1 (en) | 2001-07-05 | 2003-01-09 | Yoshiki Sugeta | Method for reducing pattern dimension in photoresist layer |
US6590817B2 (en) * | 2001-07-23 | 2003-07-08 | Micron Technology, Inc. | 6F2 DRAM array with apparatus for stress testing an isolation gate and method |
DE10142590A1 (de) * | 2001-08-31 | 2003-04-03 | Infineon Technologies Ag | Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße |
US6760805B2 (en) * | 2001-09-05 | 2004-07-06 | M-Systems Flash Disk Pioneers Ltd. | Flash management system for large page size |
US6951822B2 (en) | 2001-09-28 | 2005-10-04 | Infineon Technologies North America Corp. | Method for forming inside nitride spacer for deep trench device DRAM cell |
KR100569536B1 (ko) * | 2001-12-14 | 2006-04-10 | 주식회사 하이닉스반도체 | Relacs 물질을 이용하여 패턴 붕괴를 방지하는 방법 |
KR100843888B1 (ko) | 2001-12-14 | 2008-07-03 | 주식회사 하이닉스반도체 | Relacs 물질을 이용하여 식각 내성이 향상된포토레지스트 패턴을 형성하는 방법 |
KR20030056601A (ko) | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 소스 라인 형성 방법 |
US6638441B2 (en) | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
US6548401B1 (en) * | 2002-01-23 | 2003-04-15 | Micron Technology, Inc. | Semiconductor processing methods, and semiconductor constructions |
JP2003234279A (ja) | 2002-02-08 | 2003-08-22 | Sony Corp | レジストパターンの形成方法、半導体装置の製造方法およびレジストパターンの形成装置 |
JP3976598B2 (ja) * | 2002-03-27 | 2007-09-19 | Nec液晶テクノロジー株式会社 | レジスト・パターン形成方法 |
KR20030089063A (ko) | 2002-05-16 | 2003-11-21 | 주식회사 하이닉스반도체 | 포토레지스트 패턴 형성방법 |
US6734107B2 (en) | 2002-06-12 | 2004-05-11 | Macronix International Co., Ltd. | Pitch reduction in semiconductor fabrication |
US6774051B2 (en) | 2002-06-12 | 2004-08-10 | Macronix International Co., Ltd. | Method for reducing pitch |
US6548385B1 (en) | 2002-06-12 | 2003-04-15 | Jiun-Ren Lai | Method for reducing pitch between conductive features, and structure formed using the method |
US6756619B2 (en) * | 2002-08-26 | 2004-06-29 | Micron Technology, Inc. | Semiconductor constructions |
US6566280B1 (en) | 2002-08-26 | 2003-05-20 | Intel Corporation | Forming polymer features on a substrate |
US7205598B2 (en) * | 2002-08-29 | 2007-04-17 | Micron Technology, Inc. | Random access memory device utilizing a vertically oriented select transistor |
JP2004134574A (ja) | 2002-10-10 | 2004-04-30 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2004177952A (ja) | 2002-11-20 | 2004-06-24 | Rohm & Haas Electronic Materials Llc | 多層フォトレジスト系 |
KR20040057582A (ko) | 2002-12-26 | 2004-07-02 | 주식회사 하이닉스반도체 | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 |
US6916594B2 (en) | 2002-12-30 | 2005-07-12 | Hynix Semiconductor Inc. | Overcoating composition for photoresist and method for forming photoresist pattern using the same |
JP2004247399A (ja) | 2003-02-12 | 2004-09-02 | Renesas Technology Corp | 半導体装置の製造方法 |
JP4287383B2 (ja) * | 2003-05-09 | 2009-07-01 | 富士通株式会社 | レジストの加工方法及び半導体装置の製造方法 |
US6905975B2 (en) * | 2003-07-03 | 2005-06-14 | Micron Technology, Inc. | Methods of forming patterned compositions |
US7230292B2 (en) * | 2003-08-05 | 2007-06-12 | Micron Technology, Inc. | Stud electrode and process for making same |
US7125781B2 (en) | 2003-09-04 | 2006-10-24 | Micron Technology, Inc. | Methods of forming capacitor devices |
US7067385B2 (en) * | 2003-09-04 | 2006-06-27 | Micron Technology, Inc. | Support for vertically oriented capacitors during the formation of a semiconductor device |
US7030008B2 (en) * | 2003-09-12 | 2006-04-18 | International Business Machines Corporation | Techniques for patterning features in semiconductor devices |
US7033735B2 (en) | 2003-11-17 | 2006-04-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Water soluble negative tone photoresist |
JP4143023B2 (ja) * | 2003-11-21 | 2008-09-03 | 株式会社東芝 | パターン形成方法および半導体装置の製造方法 |
US7049652B2 (en) * | 2003-12-10 | 2006-05-23 | Sandisk Corporation | Pillar cell flash memory technology |
KR100554514B1 (ko) | 2003-12-26 | 2006-03-03 | 삼성전자주식회사 | 반도체 장치에서 패턴 형성 방법 및 이를 이용한 게이트형성방법. |
US7354847B2 (en) | 2004-01-26 | 2008-04-08 | Taiwan Semiconductor Manufacturing Company | Method of trimming technology |
US7037840B2 (en) | 2004-01-26 | 2006-05-02 | Micron Technology, Inc. | Methods of forming planarized surfaces over semiconductor substrates |
US6864184B1 (en) * | 2004-02-05 | 2005-03-08 | Advanced Micro Devices, Inc. | Method for reducing critical dimension attainable via the use of an organic conforming layer |
KR100781538B1 (ko) | 2004-02-07 | 2007-12-03 | 삼성전자주식회사 | 성능이 향상된 멀티 게이트 트랜지스터용 액티브 구조의제조 방법, 이에 의해 제조된 액티브 구조 및 멀티 게이트트랜지스터 |
JP2005243681A (ja) | 2004-02-24 | 2005-09-08 | Tokyo Electron Ltd | 膜改質方法、膜改質装置及びスリミング量の制御方法 |
US7390750B1 (en) * | 2004-03-23 | 2008-06-24 | Cypress Semiconductor Corp. | Method of patterning elements within a semiconductor topography |
JP2005302748A (ja) * | 2004-04-06 | 2005-10-27 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US7098105B2 (en) * | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US20050272220A1 (en) | 2004-06-07 | 2005-12-08 | Carlo Waldfried | Ultraviolet curing process for spin-on dielectric materials used in pre-metal and/or shallow trench isolation applications |
US7132333B2 (en) * | 2004-09-10 | 2006-11-07 | Infineon Technologies Ag | Transistor, memory cell array and method of manufacturing a transistor |
US7521378B2 (en) * | 2004-07-01 | 2009-04-21 | Micron Technology, Inc. | Low temperature process for polysilazane oxidation/densification |
US7387939B2 (en) * | 2004-07-19 | 2008-06-17 | Micron Technology, Inc. | Methods of forming semiconductor structures and capacitor devices |
US7202127B2 (en) * | 2004-08-27 | 2007-04-10 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US7439152B2 (en) | 2004-08-27 | 2008-10-21 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) * | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7442976B2 (en) | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
KR100640587B1 (ko) | 2004-09-23 | 2006-11-01 | 삼성전자주식회사 | 반도체 소자 제조용 마스크 패턴 및 그 형성 방법과 미세패턴을 가지는 반도체 소자의 제조 방법 |
CN100438040C (zh) | 2004-10-14 | 2008-11-26 | 茂德科技股份有限公司 | 动态随机存取存储器的结构 |
US7595141B2 (en) | 2004-10-26 | 2009-09-29 | Az Electronic Materials Usa Corp. | Composition for coating over a photoresist pattern |
US7298004B2 (en) * | 2004-11-30 | 2007-11-20 | Infineon Technologies Ag | Charge-trapping memory cell and method for production |
US7320911B2 (en) * | 2004-12-06 | 2008-01-22 | Micron Technology, Inc. | Methods of forming pluralities of capacitors |
US7390616B2 (en) | 2005-01-12 | 2008-06-24 | International Business Machines Corporation | Method for post lithographic critical dimension shrinking using post overcoat planarization |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7557015B2 (en) | 2005-03-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming pluralities of capacitors |
US7981595B2 (en) * | 2005-03-23 | 2011-07-19 | Asml Netherlands B.V. | Reduced pitch multiple exposure process |
US7166533B2 (en) | 2005-04-08 | 2007-01-23 | Infineon Technologies, Ag | Phase change memory cell defined by a pattern shrink material process |
KR100674970B1 (ko) | 2005-04-21 | 2007-01-26 | 삼성전자주식회사 | 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법 |
EP1880410A2 (en) | 2005-05-13 | 2008-01-23 | Sachem, Inc. | Selective wet etching of oxides |
US7517753B2 (en) * | 2005-05-18 | 2009-04-14 | Micron Technology, Inc. | Methods of forming pluralities of capacitors |
US7544563B2 (en) * | 2005-05-18 | 2009-06-09 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
KR100732289B1 (ko) * | 2005-05-30 | 2007-06-25 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 콘택 형성방법 |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7541632B2 (en) | 2005-06-14 | 2009-06-02 | Micron Technology, Inc. | Relaxed-pitch method of aligning active area to digit line |
JP4197691B2 (ja) | 2005-06-21 | 2008-12-17 | 株式会社東芝 | 半導体装置の製造方法 |
US20060288795A1 (en) | 2005-06-27 | 2006-12-28 | Vishay Measurements Group, Inc. | Strain gage with off axis creep compensation feature |
US7459362B2 (en) | 2005-06-27 | 2008-12-02 | Micron Technology, Inc. | Methods of forming DRAM arrays |
US7282401B2 (en) * | 2005-07-08 | 2007-10-16 | Micron Technology, Inc. | Method and apparatus for a self-aligned recessed access device (RAD) transistor gate |
US7689918B2 (en) * | 2005-07-19 | 2010-03-30 | Cisco Technology, Inc. | Graphical indicator for the multiplexed display of line graph information |
KR100640657B1 (ko) * | 2005-07-25 | 2006-11-01 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
US7776715B2 (en) * | 2005-07-26 | 2010-08-17 | Micron Technology, Inc. | Reverse construction memory cell |
US7291560B2 (en) * | 2005-08-01 | 2007-11-06 | Infineon Technologies Ag | Method of production pitch fractionizations in semiconductor technology |
US7199005B2 (en) * | 2005-08-02 | 2007-04-03 | Micron Technology, Inc. | Methods of forming pluralities of capacitors |
TWI264058B (en) | 2005-08-09 | 2006-10-11 | Powerchip Semiconductor Corp | Method of correcting mask pattern and method of forming the same |
US7875464B2 (en) * | 2005-08-25 | 2011-01-25 | The University Of Wyoming Research Corporation | Processing and analysis techniques involving in-vessel material generation |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7687342B2 (en) * | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7557032B2 (en) * | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7416943B2 (en) * | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7262135B2 (en) * | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Methods of forming layers |
KR101200938B1 (ko) * | 2005-09-30 | 2012-11-13 | 삼성전자주식회사 | 반도체 장치의 패턴 형성 방법 |
US7265059B2 (en) * | 2005-09-30 | 2007-09-04 | Freescale Semiconductor, Inc. | Multiple fin formation |
US20070085152A1 (en) * | 2005-10-14 | 2007-04-19 | Promos Technologies Pte.Ltd. Singapore | Reduced area dynamic random access memory (DRAM) cell and method for fabricating the same |
US7696101B2 (en) * | 2005-11-01 | 2010-04-13 | Micron Technology, Inc. | Process for increasing feature density during the manufacture of a semiconductor device |
US7390749B2 (en) | 2005-11-30 | 2008-06-24 | Lam Research Corporation | Self-aligned pitch reduction |
US7768055B2 (en) * | 2005-11-30 | 2010-08-03 | International Business Machines Corporation | Passive components in the back end of integrated circuits |
KR100784062B1 (ko) | 2006-01-20 | 2007-12-10 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
KR100672123B1 (ko) * | 2006-02-02 | 2007-01-19 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
KR100703985B1 (ko) | 2006-02-17 | 2007-04-09 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR100694412B1 (ko) | 2006-02-24 | 2007-03-12 | 주식회사 하이닉스반도체 | 반도체소자의 미세패턴 형성방법 |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7759253B2 (en) * | 2006-08-07 | 2010-07-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and material for forming a double exposure lithography pattern |
JP4801477B2 (ja) | 2006-03-24 | 2011-10-26 | 富士通株式会社 | レジスト組成物、レジストパターンの形成方法、半導体装置及びその製造方法 |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US7557013B2 (en) | 2006-04-10 | 2009-07-07 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8158333B2 (en) | 2006-04-11 | 2012-04-17 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor device |
JP2007294511A (ja) | 2006-04-21 | 2007-11-08 | Tdk Corp | レジストパターンの形成方法、薄膜パターンの形成方法及びマイクロデバイスの製造方法 |
US7488685B2 (en) * | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7314810B2 (en) | 2006-05-09 | 2008-01-01 | Hynix Semiconductor Inc. | Method for forming fine pattern of semiconductor device |
US7429533B2 (en) | 2006-05-10 | 2008-09-30 | Lam Research Corporation | Pitch reduction |
US7537866B2 (en) * | 2006-05-24 | 2009-05-26 | Synopsys, Inc. | Patterning a single integrated circuit layer using multiple masks and multiple masking layers |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7625776B2 (en) | 2006-06-02 | 2009-12-01 | Micron Technology, Inc. | Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon |
US7628932B2 (en) | 2006-06-02 | 2009-12-08 | Micron Technology, Inc. | Wet etch suitable for creating square cuts in si |
US7709341B2 (en) | 2006-06-02 | 2010-05-04 | Micron Technology, Inc. | Methods of shaping vertical single crystal silicon walls and resulting structures |
KR20070122049A (ko) * | 2006-06-23 | 2007-12-28 | 주식회사 하이닉스반도체 | 이중 노광 공정을 이용한 미세 패턴 형성방법 |
KR100801078B1 (ko) * | 2006-06-29 | 2008-02-11 | 삼성전자주식회사 | 수직 채널을 갖는 비휘발성 메모리 집적 회로 장치 및 그제조 방법 |
US8852851B2 (en) * | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
KR100843870B1 (ko) | 2006-07-14 | 2008-07-03 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성 방법 |
JP4724072B2 (ja) * | 2006-08-17 | 2011-07-13 | 富士通株式会社 | レジストパターンの形成方法、半導体装置及びその製造方法 |
US7521371B2 (en) * | 2006-08-21 | 2009-04-21 | Micron Technology, Inc. | Methods of forming semiconductor constructions having lines |
JP4319671B2 (ja) | 2006-08-22 | 2009-08-26 | 富士通株式会社 | レジストパターン及びその製造方法、並びに、半導体装置及びその製造方法 |
US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
KR100761857B1 (ko) * | 2006-09-08 | 2007-09-28 | 삼성전자주식회사 | 반도체 소자의 미세패턴 형성방법 및 이를 이용한 반도체소자의 제조방법 |
US7790357B2 (en) | 2006-09-12 | 2010-09-07 | Hynix Semiconductor Inc. | Method of forming fine pattern of semiconductor device |
KR100855845B1 (ko) | 2006-09-12 | 2008-09-01 | 주식회사 하이닉스반도체 | 반도체 소자의 미세패턴 형성방법 |
US7959818B2 (en) | 2006-09-12 | 2011-06-14 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
US7666578B2 (en) * | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US8129289B2 (en) * | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
US7902081B2 (en) * | 2006-10-11 | 2011-03-08 | Micron Technology, Inc. | Methods of etching polysilicon and methods of forming pluralities of capacitors |
US7553760B2 (en) * | 2006-10-19 | 2009-06-30 | International Business Machines Corporation | Sub-lithographic nano interconnect structures, and method for forming same |
KR100913005B1 (ko) * | 2006-10-31 | 2009-08-20 | 주식회사 하이닉스반도체 | 마스크 패턴 형성 방법 |
KR20080038963A (ko) | 2006-10-31 | 2008-05-07 | 주식회사 하이닉스반도체 | 콘택을 갖는 반도체소자의 제조방법 |
KR100771891B1 (ko) | 2006-11-10 | 2007-11-01 | 삼성전자주식회사 | 더블 패터닝 공정을 이용하는 반도체 소자의 미세 패턴형성 방법 |
WO2008059440A2 (en) | 2006-11-14 | 2008-05-22 | Nxp B.V. | Double patterning for lithography to increase feature spatial density |
US20080113483A1 (en) * | 2006-11-15 | 2008-05-15 | Micron Technology, Inc. | Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures |
US20080120900A1 (en) * | 2006-11-29 | 2008-05-29 | Femo Operations, Lp | Systems and Methods for Repelling and/or Killing Pests Using Mulch |
US7807575B2 (en) * | 2006-11-29 | 2010-10-05 | Micron Technology, Inc. | Methods to reduce the critical dimension of semiconductor devices |
WO2008070060A2 (en) | 2006-12-06 | 2008-06-12 | Fujifilm Electronic Materials U.S.A., Inc. | Device manufacturing process utilizing a double pattering process |
US7786016B2 (en) | 2007-01-11 | 2010-08-31 | Micron Technology, Inc. | Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide |
US8236592B2 (en) | 2007-01-12 | 2012-08-07 | Globalfoundries Inc. | Method of forming semiconductor device |
US7842616B2 (en) | 2007-01-22 | 2010-11-30 | Advanced Technology Development Facility, Inc. | Methods for fabricating semiconductor structures |
US7741015B2 (en) | 2007-02-16 | 2010-06-22 | Shin-Etsu Chemical Co., Ltd. | Patterning process and resist composition |
US7785962B2 (en) | 2007-02-26 | 2010-08-31 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US7790360B2 (en) | 2007-03-05 | 2010-09-07 | Micron Technology, Inc. | Methods of forming multiple lines |
US8083953B2 (en) | 2007-03-06 | 2011-12-27 | Micron Technology, Inc. | Registered structure formation via the application of directed thermal energy to diblock copolymer films |
KR100880323B1 (ko) | 2007-05-11 | 2009-01-28 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
US20080292991A1 (en) | 2007-05-24 | 2008-11-27 | Advanced Micro Devices, Inc. | High fidelity multiple resist patterning |
US7709390B2 (en) | 2007-05-31 | 2010-05-04 | Micron Technology, Inc. | Methods of isolating array features during pitch doubling processes and semiconductor device structures having isolated array features |
US20080306636A1 (en) | 2007-06-06 | 2008-12-11 | Paccar Inc | Enhanced display for presenting tachometer information |
KR101101785B1 (ko) * | 2007-06-08 | 2012-01-05 | 도쿄엘렉트론가부시키가이샤 | 패터닝 방법 |
US7682924B2 (en) * | 2007-08-13 | 2010-03-23 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
JP2009049338A (ja) | 2007-08-23 | 2009-03-05 | Toshiba Corp | 半導体装置及びその製造方法 |
US20090074958A1 (en) * | 2007-09-13 | 2009-03-19 | Dequan Xiao | Polymeric nanocompositions comprising self-assembled organic quantum dots |
DE102007052050B4 (de) | 2007-10-31 | 2010-04-08 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement und Verfahren zum Erhöhen der Ätzselektivität während der Strukturierung einer Kontaktstruktur des Halbleiterbauelements |
KR100874433B1 (ko) * | 2007-11-02 | 2008-12-17 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
KR20090050699A (ko) | 2007-11-16 | 2009-05-20 | 주식회사 동부하이텍 | 미세 패턴 제조 방법 및 반도체 소자의 제조 방법 |
US8530147B2 (en) * | 2007-11-21 | 2013-09-10 | Macronix International Co., Ltd. | Patterning process |
US7851135B2 (en) | 2007-11-30 | 2010-12-14 | Hynix Semiconductor Inc. | Method of forming an etching mask pattern from developed negative and positive photoresist layers |
US8083958B2 (en) | 2007-12-05 | 2011-12-27 | International Business Machines Corporation | Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques |
JP2009194196A (ja) | 2008-02-15 | 2009-08-27 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置 |
US7906031B2 (en) * | 2008-02-22 | 2011-03-15 | International Business Machines Corporation | Aligning polymer films |
JP2009252830A (ja) | 2008-04-02 | 2009-10-29 | Toshiba Corp | 半導体装置の製造方法 |
US7713818B2 (en) * | 2008-04-11 | 2010-05-11 | Sandisk 3D, Llc | Double patterning method |
US8440576B2 (en) | 2008-04-25 | 2013-05-14 | Macronix International Co., Ltd. | Method for pitch reduction in integrated circuit fabrication |
US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
JP2009289974A (ja) | 2008-05-29 | 2009-12-10 | Toshiba Corp | 半導体装置の製造方法 |
US7759193B2 (en) * | 2008-07-09 | 2010-07-20 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8158335B2 (en) * | 2008-09-15 | 2012-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | High etch resistant material for double patterning |
JP2010087301A (ja) | 2008-09-30 | 2010-04-15 | Toshiba Corp | 半導体装置の製造方法 |
US8492282B2 (en) * | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US8796155B2 (en) * | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8273634B2 (en) * | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8247302B2 (en) * | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
-
2009
- 2009-03-23 US US12/409,308 patent/US8268543B2/en active Active
-
2010
- 2010-02-26 JP JP2012502066A patent/JP5516717B2/ja active Active
- 2010-02-26 EP EP10756541.8A patent/EP2412004B1/en active Active
- 2010-02-26 CN CN201080013110.1A patent/CN102362334B/zh active Active
- 2010-02-26 WO PCT/US2010/025495 patent/WO2010110987A2/en active Application Filing
- 2010-02-26 KR KR1020117024878A patent/KR101327577B1/ko active IP Right Grant
- 2010-03-16 TW TW099107690A patent/TWI396227B/zh active
-
2012
- 2012-05-30 US US13/483,339 patent/US8563228B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030006410A1 (en) * | 2000-03-01 | 2003-01-09 | Brian Doyle | Quantum wire gate device and method of making same |
US20040198065A1 (en) * | 2003-04-04 | 2004-10-07 | Sung-Kwon Lee | Method for fabricating semiconductor device with fine patterns |
US20070202697A1 (en) * | 2006-02-24 | 2007-08-30 | Hynix Semiconductor Inc. | Method for forming fine pattern of semiconductor device |
TW200814140A (en) * | 2006-09-12 | 2008-03-16 | Hynix Semiconductor Inc | Method for forming fine pattern of semiconductor device |
US20080305636A1 (en) * | 2007-06-07 | 2008-12-11 | Samsung Electronics Co., Ltd. | Method of forming fine pattern employing self-aligned double patterning |
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US20100239983A1 (en) | 2010-09-23 |
JP2012521661A (ja) | 2012-09-13 |
EP2412004B1 (en) | 2018-01-10 |
CN102362334A (zh) | 2012-02-22 |
EP2412004A2 (en) | 2012-02-01 |
US8563228B2 (en) | 2013-10-22 |
KR101327577B1 (ko) | 2013-11-12 |
WO2010110987A2 (en) | 2010-09-30 |
US8268543B2 (en) | 2012-09-18 |
CN102362334B (zh) | 2014-07-16 |
WO2010110987A3 (en) | 2011-01-06 |
EP2412004A4 (en) | 2013-07-10 |
JP5516717B2 (ja) | 2014-06-11 |
TW201113930A (en) | 2011-04-16 |
KR20120001770A (ko) | 2012-01-04 |
US20120237880A1 (en) | 2012-09-20 |
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