JP5408880B2 - ストレインド・チャネル領域を伴った非平面mos構造 - Google Patents
ストレインド・チャネル領域を伴った非平面mos構造 Download PDFInfo
- Publication number
- JP5408880B2 JP5408880B2 JP2007551294A JP2007551294A JP5408880B2 JP 5408880 B2 JP5408880 B2 JP 5408880B2 JP 2007551294 A JP2007551294 A JP 2007551294A JP 2007551294 A JP2007551294 A JP 2007551294A JP 5408880 B2 JP5408880 B2 JP 5408880B2
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- Japan
- Prior art keywords
- silicon
- germanium
- layer
- substrate
- strained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6733—Multi-gate TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
- H10D30/6748—Group IV materials, e.g. germanium or silicon carbide having a multilayer structure or superlattice structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/011—Manufacture or treatment comprising FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
- H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
Landscapes
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/039,197 US7193279B2 (en) | 2005-01-18 | 2005-01-18 | Non-planar MOS structure with a strained channel region |
| US11/039,197 | 2005-01-18 | ||
| PCT/US2006/000378 WO2006078469A1 (en) | 2005-01-18 | 2006-01-04 | Non-planar mos structure with a strained channel region |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008527742A JP2008527742A (ja) | 2008-07-24 |
| JP2008527742A5 JP2008527742A5 (enExample) | 2011-10-27 |
| JP5408880B2 true JP5408880B2 (ja) | 2014-02-05 |
Family
ID=36295351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007551294A Expired - Fee Related JP5408880B2 (ja) | 2005-01-18 | 2006-01-04 | ストレインド・チャネル領域を伴った非平面mos構造 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US7193279B2 (enExample) |
| JP (1) | JP5408880B2 (enExample) |
| KR (1) | KR100903902B1 (enExample) |
| CN (1) | CN101142688B (enExample) |
| DE (1) | DE112006000229B4 (enExample) |
| GB (1) | GB2437867B (enExample) |
| TW (1) | TWI309091B (enExample) |
| WO (1) | WO2006078469A1 (enExample) |
Families Citing this family (143)
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- 2005-01-18 US US11/039,197 patent/US7193279B2/en not_active Expired - Fee Related
-
2006
- 2006-01-04 JP JP2007551294A patent/JP5408880B2/ja not_active Expired - Fee Related
- 2006-01-04 GB GB0714637A patent/GB2437867B/en not_active Expired - Fee Related
- 2006-01-04 WO PCT/US2006/000378 patent/WO2006078469A1/en not_active Ceased
- 2006-01-04 DE DE112006000229.5T patent/DE112006000229B4/de not_active Expired - Fee Related
- 2006-01-04 CN CN2006800087117A patent/CN101142688B/zh not_active Expired - Fee Related
- 2006-01-04 KR KR1020077016441A patent/KR100903902B1/ko not_active Expired - Fee Related
- 2006-01-06 TW TW095100641A patent/TWI309091B/zh not_active IP Right Cessation
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Also Published As
| Publication number | Publication date |
|---|---|
| DE112006000229T5 (de) | 2007-11-08 |
| US20060157687A1 (en) | 2006-07-20 |
| WO2006078469A1 (en) | 2006-07-27 |
| DE112006000229B4 (de) | 2016-04-14 |
| GB2437867B (en) | 2008-07-09 |
| US7531393B2 (en) | 2009-05-12 |
| CN101142688B (zh) | 2012-05-23 |
| KR20070089743A (ko) | 2007-08-31 |
| CN101142688A (zh) | 2008-03-12 |
| US7193279B2 (en) | 2007-03-20 |
| TW200711157A (en) | 2007-03-16 |
| US20060157794A1 (en) | 2006-07-20 |
| JP2008527742A (ja) | 2008-07-24 |
| TWI309091B (en) | 2009-04-21 |
| KR100903902B1 (ko) | 2009-06-19 |
| GB0714637D0 (en) | 2007-09-05 |
| GB2437867A (en) | 2007-11-07 |
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