KR20070089743A - 변형 채널 영역을 갖는 비평면형 mos 구조 - Google Patents
변형 채널 영역을 갖는 비평면형 mos 구조 Download PDFInfo
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- KR20070089743A KR20070089743A KR1020077016441A KR20077016441A KR20070089743A KR 20070089743 A KR20070089743 A KR 20070089743A KR 1020077016441 A KR1020077016441 A KR 1020077016441A KR 20077016441 A KR20077016441 A KR 20077016441A KR 20070089743 A KR20070089743 A KR 20070089743A
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- silicon
- germanium
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 98
- 229910052710 silicon Inorganic materials 0.000 claims description 98
- 239000010703 silicon Substances 0.000 claims description 98
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 81
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 81
- 238000000034 method Methods 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 30
- 229910052732 germanium Inorganic materials 0.000 claims description 14
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- -1 lanthanum aluminate Chemical class 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 3
- 229910002113 barium titanate Inorganic materials 0.000 claims description 3
- 229910052735 hafnium Inorganic materials 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- JQJCSZOEVBFDKO-UHFFFAOYSA-N lead zinc Chemical compound [Zn].[Pb] JQJCSZOEVBFDKO-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052706 scandium Inorganic materials 0.000 claims description 3
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 13
- 230000008021 deposition Effects 0.000 description 13
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 238000002513 implantation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000005923 long-lasting effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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Abstract
Description
Claims (22)
- 기판 상에 형성되고 상기 기판과 전기적으로 분리된 실리콘 게르마늄 바디(body);상기 실리콘 게르마늄 바디 상에 형성된 변형 실리콘(strained silicon);상기 변형 실리콘 상에 형성된 게이트 유전체;상기 게이트 유전체 상에 형성된 게이트; 및상기 변형 실리콘에 형성된 소스 및 드레인을 포함하는 비평면형 트랜지스터(non-planar transistor)
- 제1항에 있어서,상기 실리콘 게르마늄 바디는 약 5%와 80% 사이의 게르마늄 농도를 포함하는 비평면형 트랜지스터.
- 제2항에 있어서,상기 실리콘 게르마늄 바디는 약 15%의 게르마늄 농도를 포함하는 비평면형 트랜지스터.
- 제1항에 있어서,상기 게이트 유전체는 이산화규소(silicon dioxide), 하프늄 산화물(hafnium oxide), 하프늄 실리케이트(hafnium silicate), 란타늄 산화물(lanthanum oxide), 란타늄 알루미네이트(lanthanum aluminate), 지르코늄 산화물(zirconium oxide), 지르코늄 실리케이트(zirconium silicate), 탄탈륨 산화물(tantalum oxide), 티타늄 산화물(titanium oxide), 바륨 스트론튬 티타네이트(barium strontium titanate), 바륨 티타네이트(barium titanate), 스트론튬 티타네이트(strontium titanate), 이트륨 산화물(yttrium oxide), 알루미늄 산화물(aluminum oxide), 납 스칸듐 탄타네이트(lead scandium tantanate), 및 납 아연 니오베이트(lead zinc niobate)를 포함하는 군에서 선택된 물질을 포함하는 비평면형 트랜지스터.
- 제1항에 있어서,상기 게이트는 폴리실리콘(polysilicon), 금속, 및 그들의 조합을 포함하는 군에서 선택된 물질을 포함하는 비평면형 트랜지스터.
- 제1항에 있어서,상기 실리콘 게르마늄 바디는 실질적으로 사각형 단면을 갖고 상기 변형 실리콘이 상기 실리콘 게르마늄 바디의 상부 및 양쪽 측벽 상에 형성된 비평면형 트랜지스터.
- 제1항에 있어서,상기 실리콘 게르마늄 바디는 실질적으로 사다리꼴 단면을 갖고 상기 변형 실리콘이 상기 실리콘 게르마늄 바디의 상부 및 양쪽 측벽 상에 형성된 비평면형 트랜지스터.
- 제1항에 있어서,상기 변형 실리콘은 약 2㎚와 10㎚ 사이의 두께를 갖는 비평면형 트랜지스터.
- 제8항에 있어서,상기 변형 실리콘은 약 4㎚와 5㎚ 사이의 두께를 갖는 비평면형 트랜지스터.
- 상부 표면 및 2개의 측벽 표면을 포함하는, 절연체 상에 형성된 실리콘 게르마늄 핀(fin);상기 실리콘 게르마늄 핀의 상기 상부 표면 및 2개의 측벽 표면 상에 형성된 변형 실리콘 막;상기 변형 실리콘 막 상에 형성된 게이트 유전체;게이트가 상기 실리콘 게르마늄 핀의 상기 상부 표면 위로 연장하는, 상기 게이트 유전체 상에 형성된 상기 게이트; 및상기 변형 실리콘 막에 형성된 소스 및 드레인을 포함하는 3중 게이트 트랜지스터(tri-gate transistor).
- 제10항에 있어서,상기 실리콘 게르마늄 핀은 약 5%와 80% 사이의 게르마늄 농도를 포함하는 3중 게이트 트랜지스터.
- 제11항에 있어서,상기 실리콘 게르마늄 핀은 약 15%의 게르마늄 농도를 포함하는 3중 게이트 트랜지스터.
- 제10항에 있어서,상기 변형 실리콘 막은 약 2㎚와 10㎚ 사이의 두께를 갖는 3중 게이트 트랜지스터.
- 제13항에 있어서,상기 변형 실리콘 막은 약 4㎚와 5㎚ 사이의 두께를 갖는 3중 게이트 트랜지스터.
- SOI(silicon on insulator) 기판 상에 실리콘 게르마늄을 형성하는 단계;상기 실리콘 게르마늄을 이완(relax)시키기 위해 상기 실리콘 게르마늄을 어닐링하는 단계;상부 표면 및 2개의 측벽 표면을 포함하는 핀을 상기 이완된 실리콘 게르마 늄에 형성하는 단계; 및상기 핀의 상기 상부 표면 및 2개의 측벽 표면 상에 변형 실리콘을 형성하는 단계를 포함하는 방법.
- 제15항에 있어서,상기 실리콘 게르마늄을 어닐링하는 단계는 상기 SOI 기판의 상기 실리콘 내로 게르마늄을 확산시키는 단계를 더 포함하는 방법.
- 제16항에 있어서,이산화규소, 하프늄 산화물, 하프늄 실리케이트, 란타늄 산화물, 란타늄알루미네이트, 지르코늄 산화물, 지르코늄 실리케이트, 탄탈륨 산화물, 티타늄 산화물, 바륨 스트론튬 티타네이트, 바륨 티타네이트, 스트론튬 티타네이트, 이트륨 산화물, 알루미늄 산화물, 납 스칸듐 탄타네이트, 및 납 아연 니오베이트를 포함하는 군에서 선택된 물질로 된 게이트 유전체를 상기 변형 실리콘 막 상에 형성하는 단계를 더 포함하는 방법.
- 제17항에 있어서,상기 게이트 유전체 상에 게이트를 형성하는 단계를 더 포함하고, 상기 게이 트를 구성하는 물질은 폴리실리콘, 금속, 및 그들의 조합을 포함하는 군에서 선택되는 방법.
- 제18항에 있어서,소스 및 드레인을 형성하기 위해서 상기 변형 실리콘을 도핑하는 단계를 더 포함하는 방법.
- 변형 실리콘 채널 영역을 포함하는 3중 게이트 트랜지스터를 포함하는 장치.
- 제20항에 있어서,상기 변형 실리콘 채널 영역은 약 2㎚와 10㎚ 사이의 두께를 갖는 장치.
- 제21항에 있어서,상기 변형 실리콘 채널 영역은 약 4㎚와 5㎚ 사이의 두께를 갖는 장치.
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- 2006-01-04 DE DE112006000229.5T patent/DE112006000229B4/de not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
TW200711157A (en) | 2007-03-16 |
DE112006000229B4 (de) | 2016-04-14 |
US7531393B2 (en) | 2009-05-12 |
CN101142688B (zh) | 2012-05-23 |
GB2437867A (en) | 2007-11-07 |
GB0714637D0 (en) | 2007-09-05 |
KR100903902B1 (ko) | 2009-06-19 |
US20060157794A1 (en) | 2006-07-20 |
JP2008527742A (ja) | 2008-07-24 |
DE112006000229T5 (de) | 2007-11-08 |
US20060157687A1 (en) | 2006-07-20 |
JP5408880B2 (ja) | 2014-02-05 |
TWI309091B (en) | 2009-04-21 |
CN101142688A (zh) | 2008-03-12 |
GB2437867B (en) | 2008-07-09 |
US7193279B2 (en) | 2007-03-20 |
WO2006078469A1 (en) | 2006-07-27 |
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