JP5119426B2 - 複数のキャパシタを形成する方法 - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims description 145
- 238000000034 method Methods 0.000 title claims description 92
- 239000000463 material Substances 0.000 claims description 285
- 239000000758 substrate Substances 0.000 claims description 44
- 230000000873 masking effect Effects 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 37
- 239000000203 mixture Substances 0.000 claims description 27
- 230000014759 maintenance of location Effects 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 239000007772 electrode material Substances 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 description 30
- 239000004065 semiconductor Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000005380 borophosphosilicate glass Substances 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H10B—ELECTRONIC MEMORY DEVICES
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- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
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Description
図1に注目すると、本発明の或る態様に係る工程に存る半導体基板に、参照番号 10 を付してある。これには、或る例示的な実施形態においては例えばバルク単結晶珪素もしくは他の物質から成る半導体基板を含む基板が含まれる。本明細書の文章では、「半導体基板」("semiconductor substrate")もしくは「半導電性基板」("semiconductive substrate")という語は、半導電性物質を含む任意の構造物を意味するものとして定義される。ここで云う半導電性物質には、半導体ウェハ(単独であるか、もしくは他の物質をその上に含めた組立材)などのバルクの半導体材料、ならびに、半導体層(単独であるか、もしくは他の物質を含めた組立材)、が含まれるがこれらに限定はされない。また、「基板」("substrate")という語は、任意の支持構造のことを指し、上述した半導体基板を含むがこれに限定はされない。さらに、本明細書の文章では、「層」("layer")という語は、(特に定めない限りは)単層と複層の両方を包含する。
Claims (28)
- 複数のキャパシタを形成する方法であって、
キャパシタ電極形成材料としての第一の材料(20)の上に、互いに異なる組成の第二、第三、および第四の材料(25〜33、36、44)を形成するステップであって、前記第二、第三、および第四の材料(25〜33、36、44)の少なくとも一部が、前記第一の材料(20)の上に同じ高さとなるように設けられ、また、前記第三の材料(36)が、異方性エッチングされた保持構造を含む、ステップと、
前記第二の材料(25〜33)を、前記第三の材料(36)および前記第四の材料(44)に対して選択的にエッチングして、その後に、前記第一の材料(20)を、前記第三の材料(36)および前記第四の材料(44)に対して選択的にエッチングすることで、複数のキャパシタ電極開口部を形成するステップと、
個々のキャパシタ電極を、前記キャパシタ電極開口部のそれぞれの内部に形成するステップと、
前記第四の材料(44)を、前記第三の材料(36)に対して選択的に且つ前記キャパシタ電極に対して選択的にエッチングして、エッチングされた前記第四の材料(44)の下に在る第一の材料(20)を露出させ、その後、前記第一の材料(20)を、前記第三の材料(36)に対して選択的に且つ前記キャパシタ電極に対して選択的にエッチングして、前記キャパシタ電極の側方外壁を露出させ、かつ、前記キャパシタ電極を支持する前記保持構造の少なくとも一部を残すステップと、
前記複数のキャパシタ電極を複数のキャパシタ内に組み込むステップと、
を含むことを特徴とする方法。 - 前記第二の材料の組成が、前記第一の材料の組成と異なることを特徴とする、請求項1記載の方法。
- 前記第二の材料の組成が、前記第一の材料の組成と同一であることを特徴とする、請求項1記載の方法。
- 前記第一の材料が少なくとも二つの層を含み、前記二つの層のうちのひとつが、前記第二、第三、および第四の材料の近傍に設けられるエッチング停止層を含むことを特徴とする、請求項1記載の方法。
- 前記第二の材料が、前記第三の材料の前に形成され、
前記第三の材料が、前記第四の材料の前に形成され、また、
前記第四の材料を形成する前に、前記保持構造をファセットエッチングするステップをさらに含むことを特徴とする、請求項1記載の方法。 - 前記第二の材料が、前記第三の材料の前に形成され、
前記第三の材料が、前記第四の材料の前に形成され、また、
前記第四の材料を形成する前に、前記保持構造をウェットエッチングするステップをさらに含むことを特徴とする、請求項1記載の方法。 - 前記キャパシタ電極のそれぞれが、容器形状を具えることを特徴とする、請求項1記載の方法。
- 前記キャパシタ電極開口部が、前記基板上のキャパシタアレイ領域内に形成され、また、
前記基板が、前記キャパシタアレイ領域の周辺に位置する回路領域を含み、また、
前記保持構造を形成するための前記第三の材料の前記異方性エッチングが、前記保持構造を形成する前記キャパシタアレイ領域内の前記第三の材料をマスクすること無く行われることを特徴とする、請求項1記載の方法。 - 前記保持構造を形成するための前記第三の材料への前記異方性エッチングが、前記保持構造を形成する前記基板上の前記第三の材料をどこもマスクすること無く行われることを特徴とする、請求項8記載の方法。
- 前記保持構造が、前記複数のキャパシタを組み込んで完成した集積回路構造物の一部として残ることを特徴とする、請求項1記載の方法。
- 前記第三の材料が、電気的絶縁性であることを特徴とする、請求項1記載の方法。
- 前記第三の材料が、導電性であることを特徴とする、請求項1記載の方法。
- 前記第三の材料が、半導電性であることを特徴とする、請求項1記載の方法。
- 複数のキャパシタを形成する方法であって、
第一の材料(20)の上に、互いに離間配置された複数の第二の材料(25〜33)をマスキング材として形成するステップであって、前記第二の材料(25〜33)が、それぞれのキャパシタ電極開口部の輪郭を前記第二の材料(25〜33)の下に画定する、ステップと、
第三の材料(36)の層を、前記第二の材料(25〜33)の上と、前記第二の材料(25〜33)間に設けられた第一の材料(20)の上とに、堆積するステップであって、前記第三の材料(36)の組成は前記第二の材料(25〜33)の組成とは異なる、ステップと、
前記第三の材料(36)の層を異方性エッチングして、前記第二の材料(25〜33)を露出させ、かつ、前記第二の材料(25〜33)の側壁にもたれる相互接続保持構造を形成するステップであって、前記相互接続保持構造は、前記第二の材料(25〜33)間に設けられた前記第一の材料(20)の一部を露出させている、ステップと、
前記異方性エッチングの後に、前記第二の材料(25〜33)間に設けられた前記露出された前記第一の材料(20)を、第四の材料(44)でマスクするステップであって、前記第四の材料(44)の組成は、前記第一の材料(20)の組成とも、前記第二の材料(25〜33)の組成とも、前記第三の材料(36)の組成とも異なる、ステップと、
前記第二の材料(25〜33)をエッチングし、続いて、前記第二の材料(25〜33)の下に在る前記第一の材料(20)を、前記第三の材料(36)および前記第四の材料(44)に対して選択的にエッチングすることで、前記第一の材料(20)内にキャパシタ電極開口部を形成するステップと、
キャパシタ電極を、それぞれ、個々の前記キャパシタ電極開口部の内部に、前記相互接続保持構造にもたれるように形成するステップと、
前記第四の材料(44)を、前記第三の材料(36)に対して選択的に且つ前記キャパシタ電極に対して選択的にエッチングして、該エッチングされた前記第四の材料(44)の下の第一の材料(20)を露出させるステップと、
前記第四の材料(44)の前記エッチングの後に、前記露出された前記第一の材料(20)の少なくとも一部を、前記キャパシタ電極に対して選択的に且つ前記第三の材料(36)に対して選択的にエッチングすることで、前記キャパシタ電極の側方外壁を露出させ、かつ、前記キャパシタ電極を少なくとも部分的に支持する前記相互接続保持構造の前記第三の材料(36)の少なくとも一部を残すステップと、
前記第一の材料(20)をエッチングして前記キャパシタ電極の側方外壁を露出させる前記ステップの後に、キャパシタ誘電体材料およびキャパシタ電極材料を、前記保持構造の下の、前記側方外壁の少なくとも一部の上に堆積させるステップと、
を含むことを特徴とする方法。 - 前記第二の材料の組成が、前記第一の材料の組成と異なることを特徴とする、請求項14記載の方法。
- 前記第二の材料の組成が、前記第一の材料の組成と同一であることを特徴とする、請求項14記載の方法。
- 前記第二の材料を、マスク開口部を通じて前記第一の材料を時間制御エッチングすることによって形成することを特徴とする、請求項16記載の方法。
- 前記時間制御エッチングが、フォトマスク内に形成された開口部を通して行われることを特徴とする、請求項17記載の方法。
- エッチング停止層が、前記第二の材料と前記第一の材料との中間に設けられることを特徴とする、請求項14記載の方法。
- 前記キャパシタ電極開口部が、前記基板上のキャパシタアレイ領域内に形成され、また、
前記基板が、前記キャパシタアレイ領域の周辺に位置する回路領域を含み、また、
前記保持構造を形成するための前記第三の材料の前記異方性エッチングが、前記保持構造を形成する前記キャパシタアレイ領域内の前記第三の材料の層をマスクすること無く行われることを特徴とする、請求項14記載の方法。 - 前記保持構造を形成するための前記第三の材料の層の前記異方性エッチングが、前記保持構造を形成する前記基板上の前記第三の材料の層をどこもマスクすること無く行われることを特徴とする、請求項20記載の方法。
- 前記キャパシタ電極のそれぞれが、容器形状を具えることを特徴とする、請求項14記載の方法。
- 前記保持構造が、前記複数のキャパシタを組み込んで完成した集積回路構造物の一部として残ることを特徴とする、請求項14記載の方法。
- 前記第一、第三、および第四の材料のうちの少なくともひとつが、非晶質炭素を含むことを特徴とする、請求項14記載の方法。
- 前記第一、第三、および第四の材料のうちの少なくともひとつが、ポリシリコンを含むことを特徴とする、請求項14記載の方法。
- 前記第一、第三、および第四の材料のうちの少なくともひとつが、非晶質炭素を含み、また、
前記第一、第三、および第四の材料のうちの別の少なくともひとつが、ポリシリコンを含むことを特徴とする、請求項14記載の方法。 - 前記第四の材料を形成する前に、前記保持構造をファセットエッチングするステップをさらに含むことを特徴とする、請求項14記載の方法。
- 前記第四の材料を形成する前に、前記保持構造をウェットエッチングするステップをさらに含むことを特徴とする、請求項14記載の方法。
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US7125781B2 (en) * | 2003-09-04 | 2006-10-24 | Micron Technology, Inc. | Methods of forming capacitor devices |
US7067385B2 (en) | 2003-09-04 | 2006-06-27 | Micron Technology, Inc. | Support for vertically oriented capacitors during the formation of a semiconductor device |
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2005
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WO2006101669A1 (en) | 2006-09-28 |
US7919386B2 (en) | 2011-04-05 |
SG146611A1 (en) | 2008-10-30 |
CN102064093A (zh) | 2011-05-18 |
CN101142657B (zh) | 2011-08-03 |
TW200642033A (en) | 2006-12-01 |
US7557015B2 (en) | 2009-07-07 |
US20060211211A1 (en) | 2006-09-21 |
KR20070104675A (ko) | 2007-10-26 |
TWI317982B (en) | 2009-12-01 |
EP1859476B1 (en) | 2015-11-04 |
US20090209080A1 (en) | 2009-08-20 |
CN101142657A (zh) | 2008-03-12 |
EP1859476A1 (en) | 2007-11-28 |
CN102064093B (zh) | 2013-01-02 |
KR100920016B1 (ko) | 2009-10-05 |
JP2008533739A (ja) | 2008-08-21 |
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