JP4624170B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4624170B2
JP4624170B2 JP2005126392A JP2005126392A JP4624170B2 JP 4624170 B2 JP4624170 B2 JP 4624170B2 JP 2005126392 A JP2005126392 A JP 2005126392A JP 2005126392 A JP2005126392 A JP 2005126392A JP 4624170 B2 JP4624170 B2 JP 4624170B2
Authority
JP
Japan
Prior art keywords
semiconductor device
leads
lead
suspension
metal plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005126392A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006303371A5 (https=
JP2006303371A (ja
Inventor
賢治 天野
一 長谷部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2005126392A priority Critical patent/JP4624170B2/ja
Priority to TW095110598A priority patent/TWI401751B/zh
Priority to CN2006100763766A priority patent/CN1855409B/zh
Priority to US11/409,014 priority patent/US7429500B2/en
Priority to KR1020060036485A priority patent/KR101254803B1/ko
Publication of JP2006303371A publication Critical patent/JP2006303371A/ja
Priority to US12/191,503 priority patent/US7514293B2/en
Priority to US12/401,075 priority patent/US7948068B2/en
Publication of JP2006303371A5 publication Critical patent/JP2006303371A5/ja
Application granted granted Critical
Publication of JP4624170B2 publication Critical patent/JP4624170B2/ja
Priority to US13/084,600 priority patent/US8102035B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/456Materials
    • H10W70/457Materials of metallic layers on leadframes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/04Manufacture or treatment of leadframes
    • H10W70/048Mechanical treatments, e.g. punching, cutting, deforming or cold welding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • H10W70/424Cross-sectional shapes
    • H10W70/427Bent parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2005126392A 2005-04-25 2005-04-25 半導体装置の製造方法 Expired - Fee Related JP4624170B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP2005126392A JP4624170B2 (ja) 2005-04-25 2005-04-25 半導体装置の製造方法
TW095110598A TWI401751B (zh) 2005-04-25 2006-03-27 半導體裝置之製造方法
CN2006100763766A CN1855409B (zh) 2005-04-25 2006-04-20 制造半导体器件的方法
KR1020060036485A KR101254803B1 (ko) 2005-04-25 2006-04-24 반도체 장치의 제조 방법
US11/409,014 US7429500B2 (en) 2005-04-25 2006-04-24 Method of manufacturing a semiconductor device
US12/191,503 US7514293B2 (en) 2005-04-25 2008-08-14 Method of manufacturing a semiconductor device
US12/401,075 US7948068B2 (en) 2005-04-25 2009-03-10 Semiconductor device having a chip mounting portion and a plurality of suspending leads supporting the chip mounting portion and each suspension lead having a bent portion
US13/084,600 US8102035B2 (en) 2005-04-25 2011-04-12 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005126392A JP4624170B2 (ja) 2005-04-25 2005-04-25 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010210916A Division JP5562780B2 (ja) 2010-09-21 2010-09-21 半導体装置

Publications (3)

Publication Number Publication Date
JP2006303371A JP2006303371A (ja) 2006-11-02
JP2006303371A5 JP2006303371A5 (https=) 2010-08-12
JP4624170B2 true JP4624170B2 (ja) 2011-02-02

Family

ID=37187473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005126392A Expired - Fee Related JP4624170B2 (ja) 2005-04-25 2005-04-25 半導体装置の製造方法

Country Status (5)

Country Link
US (4) US7429500B2 (https=)
JP (1) JP4624170B2 (https=)
KR (1) KR101254803B1 (https=)
CN (1) CN1855409B (https=)
TW (1) TWI401751B (https=)

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US9214586B2 (en) 2010-04-30 2015-12-15 Solar Junction Corporation Semiconductor solar cell package
JP2012113919A (ja) * 2010-11-24 2012-06-14 Toshiba Corp 照明装置
US9524928B2 (en) 2010-12-13 2016-12-20 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package having control and driver circuits
US9711437B2 (en) 2010-12-13 2017-07-18 Infineon Technologies Americas Corp. Semiconductor package having multi-phase power inverter with internal temperature sensor
US9362215B2 (en) 2010-12-13 2016-06-07 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter
US9355995B2 (en) 2010-12-13 2016-05-31 Infineon Technologies Americas Corp. Semiconductor packages utilizing leadframe panels with grooves in connecting bars
US9443795B2 (en) 2010-12-13 2016-09-13 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package having bootstrap diodes on a common integrated circuit (IC)
US9449957B2 (en) 2010-12-13 2016-09-20 Infineon Technologies Americas Corp. Control and driver circuits on a power quad flat no-lead (PQFN) leadframe
US8587101B2 (en) * 2010-12-13 2013-11-19 International Rectifier Corporation Multi-chip module (MCM) power quad flat no-lead (PQFN) semiconductor package utilizing a leadframe for electrical interconnections
US9324646B2 (en) 2010-12-13 2016-04-26 Infineon Technologies America Corp. Open source power quad flat no-lead (PQFN) package
US9659845B2 (en) 2010-12-13 2017-05-23 Infineon Technologies Americas Corp. Power quad flat no-lead (PQFN) package in a single shunt inverter circuit
US9620954B2 (en) 2010-12-13 2017-04-11 Infineon Technologies Americas Corp. Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values
US8962989B2 (en) 2011-02-03 2015-02-24 Solar Junction Corporation Flexible hermetic semiconductor solar cell package with non-hermetic option
KR20130064477A (ko) * 2011-12-08 2013-06-18 삼성전자주식회사 단층 배선 패턴을 포함하는 인쇄회로기판
JP5919087B2 (ja) * 2012-05-10 2016-05-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP5947107B2 (ja) * 2012-05-23 2016-07-06 ルネサスエレクトロニクス株式会社 半導体装置
JP2016072376A (ja) * 2014-09-29 2016-05-09 ルネサスエレクトロニクス株式会社 半導体装置
US10090420B2 (en) 2016-01-22 2018-10-02 Solar Junction Corporation Via etch method for back contact multijunction solar cells
US9680035B1 (en) 2016-05-27 2017-06-13 Solar Junction Corporation Surface mount solar cell with integrated coverglass
US20190221502A1 (en) * 2018-01-17 2019-07-18 Microchip Technology Incorporated Down Bond in Semiconductor Devices
CN109576676B (zh) * 2018-12-25 2023-12-29 西安立芯光电科技有限公司 一种用于半导体激光器侧腔面镀膜的夹具
CN112151489B (zh) * 2020-09-01 2023-06-06 通富微电科技(南通)有限公司 引线框架、引线框架的形成方法及引线框架封装体
CN113013039B (zh) * 2021-02-02 2023-02-10 江西新菲新材料有限公司 引线框架的制备方法

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Also Published As

Publication number Publication date
US7514293B2 (en) 2009-04-07
TW200723414A (en) 2007-06-16
TWI401751B (zh) 2013-07-11
US20060240599A1 (en) 2006-10-26
US20110186976A1 (en) 2011-08-04
US7948068B2 (en) 2011-05-24
US20080305586A1 (en) 2008-12-11
US7429500B2 (en) 2008-09-30
JP2006303371A (ja) 2006-11-02
KR101254803B1 (ko) 2013-04-15
CN1855409B (zh) 2010-06-23
CN1855409A (zh) 2006-11-01
US8102035B2 (en) 2012-01-24
US20090176335A1 (en) 2009-07-09
KR20060112611A (ko) 2006-11-01

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