JP4034073B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4034073B2
JP4034073B2 JP2002004435A JP2002004435A JP4034073B2 JP 4034073 B2 JP4034073 B2 JP 4034073B2 JP 2002004435 A JP2002004435 A JP 2002004435A JP 2002004435 A JP2002004435 A JP 2002004435A JP 4034073 B2 JP4034073 B2 JP 4034073B2
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JP
Japan
Prior art keywords
semiconductor device
substrate
external electrode
view
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002004435A
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English (en)
Japanese (ja)
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JP2003031730A (ja
JP2003031730A5 (https=
Inventor
好彦 嶋貫
雅之 鈴木
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Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002004435A priority Critical patent/JP4034073B2/ja
Priority to TW091103201A priority patent/TW544883B/zh
Priority to KR1020020011892A priority patent/KR20020086219A/ko
Priority to US10/091,302 priority patent/US20020168796A1/en
Publication of JP2003031730A publication Critical patent/JP2003031730A/ja
Priority to US10/902,785 priority patent/US7407834B2/en
Publication of JP2003031730A5 publication Critical patent/JP2003031730A5/ja
Application granted granted Critical
Publication of JP4034073B2 publication Critical patent/JP4034073B2/ja
Priority to KR1020080059219A priority patent/KR100868608B1/ko
Priority to US12/213,779 priority patent/US7459347B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/042—Etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
JP2002004435A 2001-05-11 2002-01-11 半導体装置の製造方法 Expired - Fee Related JP4034073B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2002004435A JP4034073B2 (ja) 2001-05-11 2002-01-11 半導体装置の製造方法
TW091103201A TW544883B (en) 2001-05-11 2002-02-22 Manufacturing method of semiconductor device
US10/091,302 US20020168796A1 (en) 2001-05-11 2002-03-06 Manufacturing method of a semiconductor device
KR1020020011892A KR20020086219A (ko) 2001-05-11 2002-03-06 반도체 장치의 제조 방법
US10/902,785 US7407834B2 (en) 2001-05-11 2004-08-02 Manufacturing method of a semiconductor device
KR1020080059219A KR100868608B1 (ko) 2001-05-11 2008-06-23 반도체 장치의 제조 방법
US12/213,779 US7459347B2 (en) 2001-05-11 2008-06-24 Manufacturing method of a semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001-142164 2001-05-11
JP2001142164 2001-05-11
JP2002004435A JP4034073B2 (ja) 2001-05-11 2002-01-11 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007158390A Division JP4503632B2 (ja) 2001-05-11 2007-06-15 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2003031730A JP2003031730A (ja) 2003-01-31
JP2003031730A5 JP2003031730A5 (https=) 2005-07-28
JP4034073B2 true JP4034073B2 (ja) 2008-01-16

Family

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JP2002004435A Expired - Fee Related JP4034073B2 (ja) 2001-05-11 2002-01-11 半導体装置の製造方法

Country Status (4)

Country Link
US (3) US20020168796A1 (https=)
JP (1) JP4034073B2 (https=)
KR (2) KR20020086219A (https=)
TW (1) TW544883B (https=)

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250352B2 (en) * 2002-04-24 2007-07-31 Sanyo Electric Co., Ltd. Methods for manufacturing a hybrid integrated circuit device
KR100701378B1 (ko) * 2002-12-30 2007-03-28 동부일렉트로닉스 주식회사 반도체 소자 패키징 방법
US7405468B2 (en) * 2003-04-11 2008-07-29 Dai Nippon Printing Co., Ltd. Plastic package and method of fabricating the same
WO2005004200A2 (en) * 2003-06-25 2005-01-13 Advanced Interconnect Technologies Limited Lead frame routed chip pads for semiconductor packages
US7049683B1 (en) * 2003-07-19 2006-05-23 Ns Electronics Bangkok (1993) Ltd. Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound
JP2005129900A (ja) * 2003-09-30 2005-05-19 Sanyo Electric Co Ltd 回路装置およびその製造方法
US7259460B1 (en) 2004-06-18 2007-08-21 National Semiconductor Corporation Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit package
US7087986B1 (en) * 2004-06-18 2006-08-08 National Semiconductor Corporation Solder pad configuration for use in a micro-array integrated circuit package
US7064419B1 (en) 2004-06-18 2006-06-20 National Semiconductor Corporation Die attach region for use in a micro-array integrated circuit package
TWI288885B (en) * 2004-06-24 2007-10-21 Checkpoint Systems Inc Die attach area cut-on-fly method and apparatus
US20060170081A1 (en) * 2005-02-03 2006-08-03 Gerber Mark A Method and apparatus for packaging an electronic chip
KR100819799B1 (ko) * 2005-02-22 2008-04-07 삼성테크윈 주식회사 다열리드형 반도체 패키지 제조 방법
CN100370589C (zh) * 2005-04-07 2008-02-20 江苏长电科技股份有限公司 新型集成电路或分立元件超薄无脚封装工艺
US20080258273A1 (en) * 2005-04-07 2008-10-23 Jiangsu Changjiang Electronics Technology Co., Ltd Package Structure With Flat Bumps For Electronic Device and Method of Manufacture the Same
KR101298225B1 (ko) 2005-06-30 2013-08-27 페어차일드 세미컨덕터 코포레이션 반도체 다이 패키지 및 그의 제조 방법
US7504716B2 (en) * 2005-10-26 2009-03-17 Texas Instruments Incorporated Structure and method of molded QFN device suitable for miniaturization, multiple rows and stacking
WO2007089209A1 (en) * 2006-02-01 2007-08-09 Infineon Technologies Ag Fabrication of a qfn integrated circuit package
JP4770514B2 (ja) * 2006-02-27 2011-09-14 株式会社デンソー 電子装置
WO2007104444A1 (de) 2006-03-14 2007-09-20 Institut Für Mikroelektronik Stuttgart Verfahren zum herstellen einer integrierten schaltung
US8487451B2 (en) * 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
JP4799385B2 (ja) * 2006-05-11 2011-10-26 パナソニック株式会社 樹脂封止型半導体装置の製造方法およびそのための配線基板
JP4671932B2 (ja) * 2006-08-22 2011-04-20 株式会社ユニバーサルエンターテインメント 紙幣処理装置
JP4533875B2 (ja) * 2006-09-12 2010-09-01 株式会社三井ハイテック 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法
DE102006044690B4 (de) * 2006-09-22 2010-07-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
JP2008098529A (ja) * 2006-10-13 2008-04-24 Toshiba Corp 半導体装置及びその製造方法
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US7608482B1 (en) 2006-12-21 2009-10-27 National Semiconductor Corporation Integrated circuit package with molded insulation
JP4270282B2 (ja) * 2007-01-23 2009-05-27 セイコーエプソン株式会社 半導体装置の製造方法
WO2008122959A2 (en) * 2007-04-10 2008-10-16 Nxp B.V. Package, method of manufacturing a package and frame
US7951688B2 (en) * 2007-10-01 2011-05-31 Fairchild Semiconductor Corporation Method and structure for dividing a substrate into individual devices
US20090115026A1 (en) * 2007-11-05 2009-05-07 Texas Instruments Incorporated Semiconductor device having through-silicon vias for high current,high frequency, and heat dissipation
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
KR100984132B1 (ko) * 2007-11-12 2010-09-28 삼성에스디아이 주식회사 반도체 패키지 및 그 실장방법
US7948066B2 (en) * 2007-12-26 2011-05-24 Stats Chippac Ltd. Integrated circuit package system with lead locking structure
KR101006907B1 (ko) * 2008-02-20 2011-01-13 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법
US8120152B2 (en) * 2008-03-14 2012-02-21 Advanced Semiconductor Engineering, Inc. Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof
US8063470B1 (en) * 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
US8076180B2 (en) * 2008-07-07 2011-12-13 Infineon Technologies Ag Repairable semiconductor device and method
US20100015340A1 (en) * 2008-07-17 2010-01-21 Zenergy Power Inc. COMPOSITIONS AND METHODS FOR THE MANUFACTURE OF RARE EARTH METAL-Ba2Cu3O7-delta THIN FILMS
CN101651126A (zh) * 2008-08-12 2010-02-17 三星电子株式会社 芯片封装件及其制造方法
US8174099B2 (en) * 2008-08-13 2012-05-08 Atmel Corporation Leadless package with internally extended package leads
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
US9947605B2 (en) * 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US7935571B2 (en) * 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
JP5131206B2 (ja) * 2009-01-13 2013-01-30 セイコーエプソン株式会社 半導体装置
US10199311B2 (en) 2009-01-29 2019-02-05 Semiconductor Components Industries, Llc Leadless semiconductor packages, leadframes therefor, and methods of making
US10163766B2 (en) 2016-11-21 2018-12-25 Semiconductor Components Industries, Llc Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
US9899349B2 (en) 2009-01-29 2018-02-20 Semiconductor Components Industries, Llc Semiconductor packages and related methods
US8288207B2 (en) * 2009-02-13 2012-10-16 Infineon Technologies Ag Method of manufacturing semiconductor devices
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
US8569877B2 (en) * 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US8124447B2 (en) 2009-04-10 2012-02-28 Advanced Semiconductor Engineering, Inc. Manufacturing method of advanced quad flat non-leaded package
US8133759B2 (en) * 2009-04-28 2012-03-13 Macronix International Co., Ltd. Leadframe
US7993981B2 (en) * 2009-06-11 2011-08-09 Lsi Corporation Electronic device package and method of manufacture
US8866296B2 (en) 2009-06-24 2014-10-21 Aoi Electronics Co., Ltd. Semiconductor device comprising thin-film terminal with deformed portion
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US8709870B2 (en) 2009-08-06 2014-04-29 Maxim Integrated Products, Inc. Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages
JP5554543B2 (ja) * 2009-11-06 2014-07-23 株式会社三井ハイテック リードフレーム及び半導体装置の中間製品
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) * 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
TWI469289B (zh) 2009-12-31 2015-01-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
JP5512292B2 (ja) * 2010-01-08 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8575732B2 (en) * 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8203201B2 (en) * 2010-03-26 2012-06-19 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
US8138595B2 (en) * 2010-03-26 2012-03-20 Stats Chippac Ltd. Integrated circuit packaging system with an intermediate pad and method of manufacture thereof
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
US20110248392A1 (en) * 2010-04-12 2011-10-13 Texas Instruments Incorporated Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe
KR101713640B1 (ko) * 2010-09-10 2017-03-08 메이코 일렉트로닉스 컴파니 리미티드 부품 내장 기판
US8936971B2 (en) * 2010-09-16 2015-01-20 Stats Chippac Ltd. Integrated circuit packaging system with die paddles and method of manufacture thereof
TW201241970A (en) * 2011-04-08 2012-10-16 Advanced Semiconductor Eng Semiconductor package with recesses in the edged leadas
CN102789994B (zh) * 2011-05-18 2016-08-10 飞思卡尔半导体公司 侧面可浸润半导体器件
CN102956574A (zh) * 2011-08-25 2013-03-06 力成科技股份有限公司 小基板存储卡封装构造
US8841173B2 (en) * 2011-10-20 2014-09-23 Stats Chippac Ltd. Integrated circuit packaging system with leadframe lead array routing and method of manufacture thereof
JP2013093534A (ja) * 2011-10-26 2013-05-16 Jjtech Co Ltd 半導体装置及びその製造方法、並びにシステム
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9397031B2 (en) 2012-06-11 2016-07-19 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US8877564B2 (en) 2012-06-29 2014-11-04 Intersil Americas LLC Solder flow impeding feature on a lead frame
KR101794820B1 (ko) 2012-11-28 2017-11-07 현대자동차주식회사 차량용 트랜스미션마운팅브라켓의 장착구조
US8710636B1 (en) * 2013-02-04 2014-04-29 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach
US9554453B2 (en) * 2013-02-26 2017-01-24 Mediatek Inc. Printed circuit board structure with heat dissipation function
JP6173024B2 (ja) * 2013-05-09 2017-08-02 株式会社ディスコ 積層ウェーハの加工方法及び粘着シート
US9219019B2 (en) * 2014-03-17 2015-12-22 Texas Instruments Incorporated Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
US20160071788A1 (en) * 2014-03-17 2016-03-10 Texas Instruments Incorporated Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
TW201539674A (zh) 2014-04-10 2015-10-16 南茂科技股份有限公司 四方扁平無引腳封裝及其製造方法
TWI550784B (zh) * 2014-04-18 2016-09-21 南茂科技股份有限公司 扁平無引腳封裝及其製造方法
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
JP6617955B2 (ja) * 2014-09-16 2019-12-11 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
CN105720036A (zh) * 2014-12-03 2016-06-29 恒劲科技股份有限公司 封装结构及其制法
KR101537537B1 (ko) * 2014-12-05 2015-07-17 룩씨스 주식회사 글라스 또는 사파이어 기반의 디지털 기기용 패널 제조방법
CN105895611B (zh) 2014-12-17 2019-07-12 恩智浦美国有限公司 具有可湿性侧面的无引线方形扁平半导体封装
EP3058590A4 (en) * 2014-12-23 2017-08-02 Intel Corporation Integrated package design with wire leads for package-on-package product
US9570381B2 (en) 2015-04-02 2017-02-14 Advanced Semiconductor Engineering, Inc. Semiconductor packages and related manufacturing methods
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9373569B1 (en) * 2015-09-01 2016-06-21 Texas Instruments Incorporation Flat no-lead packages with electroplated edges
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
JP6770853B2 (ja) * 2016-08-31 2020-10-21 新光電気工業株式会社 リードフレーム及び電子部品装置とそれらの製造方法
US9847283B1 (en) 2016-11-06 2017-12-19 Nexperia B.V. Semiconductor device with wettable corner leads
JP6961337B2 (ja) * 2016-11-25 2021-11-05 ルネサスエレクトロニクス株式会社 半導体装置
EP3624180A4 (en) * 2017-05-09 2020-04-01 Mitsubishi Electric Corporation SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF
JP6924411B2 (ja) * 2017-08-28 2021-08-25 大日本印刷株式会社 リードフレームおよび半導体装置の製造方法
CN108090267B (zh) * 2017-12-11 2022-02-11 广州全界通讯科技有限公司 一种pcb版图结构
JP7304145B2 (ja) * 2018-11-07 2023-07-06 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
WO2020185192A1 (en) 2019-03-08 2020-09-17 Siliconix Incorporated Semiconductor package having side wall plating
WO2020185193A1 (en) 2019-03-08 2020-09-17 Siliconix Incorporated Semiconductor package having side wall plating
CN113035722A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 具有选择性模制的用于镀覆的封装工艺
CN113035721A (zh) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 用于侧壁镀覆导电膜的封装工艺
US11729915B1 (en) 2022-03-22 2023-08-15 Tactotek Oy Method for manufacturing a number of electrical nodes, electrical node module, electrical node, and multilayer structure
TWI896088B (zh) * 2024-04-19 2025-09-01 復盛精密工業股份有限公司 具有多排引腳墊的封裝導線架及其製作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0179404B1 (ko) * 1993-02-02 1999-05-15 모리시타 요이찌 세라믹기판과 그 제조방법
AU682947B2 (en) * 1994-05-27 1997-10-23 Mochida Pharmaceutical Co., Ltd. Novel azolyl methyl phenyl derivatives having aromatase inhibitory activity
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
JP3310499B2 (ja) * 1995-08-01 2002-08-05 富士通株式会社 半導体装置
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
KR100244580B1 (ko) * 1997-06-24 2000-02-15 윤종용 금속 범프를 갖는 회로 기판의 제조 방법 및 그를 이용한 반도체 칩 패키지의 제조 방법
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6667541B1 (en) * 1998-10-21 2003-12-23 Matsushita Electric Industrial Co., Ltd. Terminal land frame and method for manufacturing the same
JP3965813B2 (ja) 1999-01-26 2007-08-29 松下電器産業株式会社 ターミナルランドフレームの製造方法
JP3913397B2 (ja) 1999-03-30 2007-05-09 三洋電機株式会社 半導体装置の製造方法
JP2001185651A (ja) * 1999-12-27 2001-07-06 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6261864B1 (en) * 2000-01-28 2001-07-17 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
EP1122778A3 (en) * 2000-01-31 2004-04-07 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6562660B1 (en) * 2000-03-08 2003-05-13 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
JP3759572B2 (ja) * 2000-03-28 2006-03-29 三洋電機株式会社 半導体装置
TW511401B (en) * 2000-09-04 2002-11-21 Sanyo Electric Co Method for manufacturing circuit device
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging

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