KR100701378B1 - 반도체 소자 패키징 방법 - Google Patents

반도체 소자 패키징 방법 Download PDF

Info

Publication number
KR100701378B1
KR100701378B1 KR1020020086651A KR20020086651A KR100701378B1 KR 100701378 B1 KR100701378 B1 KR 100701378B1 KR 1020020086651 A KR1020020086651 A KR 1020020086651A KR 20020086651 A KR20020086651 A KR 20020086651A KR 100701378 B1 KR100701378 B1 KR 100701378B1
Authority
KR
South Korea
Prior art keywords
substrate
heat sink
semiconductor device
present
heat dissipation
Prior art date
Application number
KR1020020086651A
Other languages
English (en)
Other versions
KR20040060122A (ko
Inventor
강병영
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020020086651A priority Critical patent/KR100701378B1/ko
Priority to US10/751,199 priority patent/US6953710B2/en
Publication of KR20040060122A publication Critical patent/KR20040060122A/ko
Application granted granted Critical
Publication of KR100701378B1 publication Critical patent/KR100701378B1/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 소바 패키징 방법에 관한 것이다. 즉, 본 발명은 기존의 BGA용 서브스트레이트에 오목한 홈을 형성시키고 열방출이 용이하도록 열싱크를 부착 패키징 수행함으로써, 패키지의 소형화가 가능하도록 하며, 열싱크를 통해 열방출이 용이하게 수행되어 소자의 동작 특성이 개선되는 이점이 있다. 또한 서브스트레이트에 오목한 홈을 형성하여 에폭시 몰딩 콤파운드와의 접착면적을 증가시켜 소자의 신뢰성을 향상시키는 이점이 있다.

Description

반도체 소자 패키징 방법{METHOD FOR PACKAGING SEMICONDUCTOR DEVICE}
도 1은 종래 BGA 패키징 공정 단면도,
도 2는 본 발명의 실시 예에 따른 BGA 패키징 공정 단면도.
본 발명은 반도체 소자 패키징 방법에 관한 것으로, 특히 BGA(Ball Grid Array)용 서브스트레이트(Substrate)에 오목한 홈을 형성시키고, 열방출이 용이하도록 열싱크(Heat sink)를 부착하는 반도체 소자 패키징 방법에 관한 것이다.
도 1은 종래 BGA 패키징 공정 단면도를 도시한 것으로, 종래에는 상기 도 1에서와 같이 서브스트레이트(100)에 어드히시브(Adhesive)(102)를 도포한 후, 칩을 접착시킨다. 이어 골드 와이어(Gold wire)(104)를 사용하여 칩(Chip)(106)과 서브스트레이트(100)간 와이어 본딩(Wire bonding)을 통해 인터커넥션(Interconnection)을 수행하고, 외부환경으로부터 칩(106)과 인터커넥션된 와이어를 보호하기 위하여 에폭시 몰딩 콤파운드(Epoxy molding compound)(108)로 봉지시킨다. 그런 후, 서브스트레이트(100)에 솔더 볼(Solder ball)(110)을 접착하여 개별화(Singulation)시키고 개개의 패키지 조립을 완료하게 된다.
그러나 상기한 바와 같은 종래 BGA 패키징에서는 패키징의 소형화가 어려우며, 칩에서 발생하는 열방출로 인해 반도체 소자의 동작 특성이 저하되는 문제점이 있었다.
따라서, 본 발명의 목적은 패키지의 소형화, 실장면적의 최소화가 가능하며, 소자 동작시 발생되는 열방출을 히트 싱크를 통해 외부로 방출시켜 동작 특성을 개선시키는 BGA 패키징 방법을 제공함에 있다.
상술한 목적을 달성하기 위한 본 발명은 반도체 소자 패키징 방법에 있어서, (a)서브스트레이트 상부면에 일련의 오목한 홈을 형성시키는 단계와; (b)상기 오목한 홈이 형성된 서브스트레이트에 열싱크를 부착시키는 단계와; (c)상기 열싱크가 부착된 웨이퍼를 다이 소잉하여 개개의 칩으로 분리시키는 단계와; (d)칩을 서브스트레이트에 어드히시브를 사용하여 부착시키는 단계와; (e)와이어 본딩을 수행한 후 에폭시 몰딩 콤파운드로 봉지시키는 단계;를 포함하는 것을 특징으로 한다.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.
도 2는 본 발명의 실시 예에 따른 BGA 패키징 공정 단면도를 도시한 것이다. 이하 상기 도 2를 참조하여 본 발명의 BGA 패키징 공정을 상세히 설명하기로 한다.
먼저 본 발명에서는 상기 도 2에서 보여지는 바와 같이 서브스트레이트(200)면에 오목한 홈(202)을 형성시키고, 열방출을 위한 열싱크(204)를 부착시킨다. 이 에 따라 상기 서브스트레이트(200)면상의 오목한 홈 형성으로 에폭시 몰딩 콤파운드(206)와의 접착면적이 증가되어 소자의 신뢰성이 향상되며, 상기 열싱크(204) 부착으로 소자가 동작시 발생하는 열이 쉽게 외부로 방출될 수 있도록 함으로써 소자의 오동작을 방지시키게 된다.
BGA 패키징 공정을 살펴보면, 상기와 같이 상부면에 오목한 홈(202)을 형성하고, 열싱크(204)를 부착시킨 웨이퍼(200)를 개개의 칩으로 분리하기 위해 소잉(Sawing)시키며, 칩(208)을 서브스트레이트(200)에 어드히시브(210)를 사용하여 접착시킨다. 이어 골드 와이어(212)를 이용하여 와이어 본딩을 수행한 후, 에폭시 몰딩 콤파운드(206)로 봉지하고, 솔더 볼(214)을 접착하고 리플로우(Reflow)시킨다. 그런 후 서브스트레이트를 개별화하여 개개의 패키지로 완성하여 조립을 완성시키게 된다.
즉, 상기한 바와 같이 본 발명에서는 기존의 BGA용 서브스트레이트에 오목한 홈을 형성시키고 열방출이 용이하도록 열싱크를 부착 패키징 수행함으로써, 패키지의 소형화가 가능하도록 하며, 열싱크를 통해 열방출이 용이하게 수행되어 소자의 동작 특성이 개선된다. 또한 서브스트레이트에 오목한 홈을 형성하여 에폭시 몰딩 콤파운드와의 접착면적을 증가시켜 소자의 신뢰성을 향상시키게 된다.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.
이상에서 설명한 바와 같이, 본 발명에서는 기존의 BGA용 서브스트레이트에 오목한 홈을 형성시키고 열방출이 용이하도록 열싱크를 부착 패키징 수행함으로써, 패키지의 소형화가 가능하도록 하며, 열싱크를 통해 열방출이 용이하게 수행되어 소자의 동작 특성이 개선되는 이점이 있다. 또한 서브스트레이트에 오목한 홈을 형성하여 에폭시 몰딩 콤파운드와의 접착면적을 증가시켜 소자의 신뢰성을 향상시키는 이점이 있다.

Claims (2)

  1. 반도체 소자 패키징 방법에 있어서,
    (a)서브스트레이트 상부면에 일련의 오목한 홈을 형성시키는 단계와;
    (b)상기 오목한 홈이 형성된 서브스트레이트에 열싱크를 부착시키는 단계와;
    (c)상기 열싱크가 부착된 웨이퍼를 다이 소잉하여 개개의 칩으로 분리시키는 단계와;
    (d)칩을 서브스트레이트에 어드히시브를 사용하여 부착시키는 단계와;
    (e)와이어 본딩을 수행한 후 에폭시 몰딩 콤파운드로 봉지시키는 단계;를 포함하는 것을 특징으로 하는 반도체 소자 패키징 방법.
  2. 제1항에 있어서,
    상기 서브스트레이트에 부착되는 열싱크는, 패키징시 외부로 노출되도록 하는 것을 특징으로 하는 반도체 소자 패키징 방법.
KR1020020086651A 2002-12-30 2002-12-30 반도체 소자 패키징 방법 KR100701378B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020020086651A KR100701378B1 (ko) 2002-12-30 2002-12-30 반도체 소자 패키징 방법
US10/751,199 US6953710B2 (en) 2002-12-30 2003-12-30 Method for packaging a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020086651A KR100701378B1 (ko) 2002-12-30 2002-12-30 반도체 소자 패키징 방법

Publications (2)

Publication Number Publication Date
KR20040060122A KR20040060122A (ko) 2004-07-06
KR100701378B1 true KR100701378B1 (ko) 2007-03-28

Family

ID=32822550

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020086651A KR100701378B1 (ko) 2002-12-30 2002-12-30 반도체 소자 패키징 방법

Country Status (2)

Country Link
US (1) US6953710B2 (ko)
KR (1) KR100701378B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100701378B1 (ko) 2002-12-30 2007-03-28 동부일렉트로닉스 주식회사 반도체 소자 패키징 방법
DE102005051036A1 (de) * 2005-10-25 2007-04-26 Infineon Technologies Ag Verfahren zum Aufbau eines integrierten Bausteins sowie integrierter Baustein
US20090108473A1 (en) * 2007-10-26 2009-04-30 Broadcom Corporation Die-attach material overflow control for die protection in integrated circuit packages
US8866296B2 (en) * 2009-06-24 2014-10-21 Aoi Electronics Co., Ltd. Semiconductor device comprising thin-film terminal with deformed portion
KR102031731B1 (ko) 2012-12-18 2019-10-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923076A (ja) * 1995-05-12 1997-01-21 Ind Technol Res Inst 熱放散増強のための多熱導伝路とパッケージ統合性及び信頼性向上のための縁の周りを囲むキャップからなる集積回路パッケージ
JPH09102559A (ja) * 1995-10-04 1997-04-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2001168244A (ja) 1999-12-13 2001-06-22 Fujitsu Ltd 半導体装置及びその製造方法
KR20020073260A (ko) * 2001-03-13 2002-09-23 닛뽕덴끼 가부시끼가이샤 반도체 장치 제조 방법
KR20020088300A (ko) * 2001-05-21 2002-11-27 앰코 테크놀로지 코리아 주식회사 냉매를 방열재로 사용한 반도체 패키지
US20040157366A1 (en) 2002-12-30 2004-08-12 Kang Byoung Young Method for packaging a semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5271887A (en) * 1980-08-04 1993-12-21 Witec Cayman Patents, Ltd. Method of fabricating complex micro-circuit boards, substrates and microcircuits and the substrates and microcircuits
JP4034073B2 (ja) * 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
US6657296B2 (en) * 2001-09-25 2003-12-02 Siliconware Precision Industries Co., Ltd. Semicondctor package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0923076A (ja) * 1995-05-12 1997-01-21 Ind Technol Res Inst 熱放散増強のための多熱導伝路とパッケージ統合性及び信頼性向上のための縁の周りを囲むキャップからなる集積回路パッケージ
JPH09102559A (ja) * 1995-10-04 1997-04-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2001168244A (ja) 1999-12-13 2001-06-22 Fujitsu Ltd 半導体装置及びその製造方法
KR20020073260A (ko) * 2001-03-13 2002-09-23 닛뽕덴끼 가부시끼가이샤 반도체 장치 제조 방법
KR20020088300A (ko) * 2001-05-21 2002-11-27 앰코 테크놀로지 코리아 주식회사 냉매를 방열재로 사용한 반도체 패키지
US20040157366A1 (en) 2002-12-30 2004-08-12 Kang Byoung Young Method for packaging a semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
1020020073260 *
13168244 *

Also Published As

Publication number Publication date
US20040157366A1 (en) 2004-08-12
KR20040060122A (ko) 2004-07-06
US6953710B2 (en) 2005-10-11

Similar Documents

Publication Publication Date Title
US7315078B2 (en) Chip-stacked semiconductor package and method for fabricating the same
US6818980B1 (en) Stacked semiconductor package and method of manufacturing the same
US8049313B2 (en) Heat spreader for semiconductor package
US20030178719A1 (en) Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US20090096115A1 (en) Semiconductor package and method for fabricating the same
JP2007088453A (ja) スタックダイパッケージを製造する方法
JP2003273279A (ja) 半導体装置およびその製造方法
US20070122943A1 (en) Method of making semiconductor package having exposed heat spreader
TW200504963A (en) Multi-chip semiconductor package and manufacturing method thereof
KR100701378B1 (ko) 반도체 소자 패키징 방법
US8912664B1 (en) Leadless multi-chip module structure
US6836961B2 (en) Ceramic packaging method employing flip-chip bonding
US10468319B2 (en) Low-profile electronic package
US20050062155A1 (en) Window ball grid array semiconductor package and method for fabricating the same
KR20060036433A (ko) 방열구조 반도체 패캐지 및 이에 대한 제조.
US7579680B2 (en) Packaging system for semiconductor devices
US7229849B2 (en) Method for packaging a semiconductor device
US20200227388A1 (en) Semiconductor Packages, and Methods for Forming Semiconductor Packages
KR19990060856A (ko) 볼 그리드 어레이 패키지
KR20090106727A (ko) 방열판을 부착한 박막 웨이퍼 반도체 패키지
KR20040094165A (ko) 열 방출 스택 패키지
KR100640585B1 (ko) 열방출 특성을 개선한 반도체 패키지
KR100668866B1 (ko) 반도체 패키지
US20110180837A1 (en) Electronic Light Emitting Device and Method for Fabricating the Same
KR20080003032A (ko) 방열판을 포함하는 반도체 패키지 및 그 제조 방법

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120221

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee