JP3998373B2 - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法 Download PDF

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Publication number
JP3998373B2
JP3998373B2 JP18745099A JP18745099A JP3998373B2 JP 3998373 B2 JP3998373 B2 JP 3998373B2 JP 18745099 A JP18745099 A JP 18745099A JP 18745099 A JP18745099 A JP 18745099A JP 3998373 B2 JP3998373 B2 JP 3998373B2
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JP
Japan
Prior art keywords
film
groove
conductive film
forming
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18745099A
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English (en)
Japanese (ja)
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JP2001015712A5 (enExample
JP2001015712A (ja
Inventor
亮一 古川
一行 須向
雅幸 平沼
康一 齋藤
裕彦 山本
正義 吉田
正行 石坂
真岐 下田
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Renesas Technology Corp
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Renesas Technology Corp
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Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP18745099A priority Critical patent/JP3998373B2/ja
Priority to TW089111652A priority patent/TW466749B/zh
Priority to KR1020000034824A priority patent/KR100770468B1/ko
Priority to US09/610,114 priority patent/US6444405B1/en
Publication of JP2001015712A publication Critical patent/JP2001015712A/ja
Priority to US10/112,945 priority patent/US20020098678A1/en
Priority to US10/367,737 priority patent/US6770528B2/en
Priority to US10/846,571 priority patent/US20040214428A1/en
Publication of JP2001015712A5 publication Critical patent/JP2001015712A5/ja
Priority to KR1020060103766A priority patent/KR100757888B1/ko
Priority to KR1020070020994A priority patent/KR100802698B1/ko
Application granted granted Critical
Publication of JP3998373B2 publication Critical patent/JP3998373B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
JP18745099A 1999-07-01 1999-07-01 半導体集積回路装置の製造方法 Expired - Fee Related JP3998373B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP18745099A JP3998373B2 (ja) 1999-07-01 1999-07-01 半導体集積回路装置の製造方法
TW089111652A TW466749B (en) 1999-07-01 2000-06-14 Manufacturing method of semiconductor integrated circuit device
KR1020000034824A KR100770468B1 (ko) 1999-07-01 2000-06-23 반도체 집적회로장치의 제조방법
US09/610,114 US6444405B1 (en) 1999-07-01 2000-06-30 Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate
US10/112,945 US20020098678A1 (en) 1999-07-01 2002-04-02 Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate
US10/367,737 US6770528B2 (en) 1999-07-01 2003-02-19 Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate
US10/846,571 US20040214428A1 (en) 1999-07-01 2004-05-17 Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate
KR1020060103766A KR100757888B1 (ko) 1999-07-01 2006-10-25 반도체 집적회로장치의 제조방법
KR1020070020994A KR100802698B1 (ko) 1999-07-01 2007-03-02 반도체 집적회로장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18745099A JP3998373B2 (ja) 1999-07-01 1999-07-01 半導体集積回路装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006046189A Division JP2006191137A (ja) 2006-02-23 2006-02-23 半導体集積回路装置の製造方法

Publications (3)

Publication Number Publication Date
JP2001015712A JP2001015712A (ja) 2001-01-19
JP2001015712A5 JP2001015712A5 (enExample) 2006-04-13
JP3998373B2 true JP3998373B2 (ja) 2007-10-24

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US (4) US6444405B1 (enExample)
JP (1) JP3998373B2 (enExample)
KR (3) KR100770468B1 (enExample)
TW (1) TW466749B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3998373B2 (ja) * 1999-07-01 2007-10-24 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2001223345A (ja) * 1999-11-30 2001-08-17 Hitachi Ltd 半導体装置とその製造方法
KR100476399B1 (ko) * 2002-06-29 2005-03-16 주식회사 하이닉스반도체 반도체 장치의 캐패시터 제조방법
US20040084400A1 (en) 2002-10-30 2004-05-06 Gregory Costrini Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask
KR100526869B1 (ko) * 2003-06-19 2005-11-09 삼성전자주식회사 반도체 메모리에서의 커패시터 하부 전극 형성방법
US7199045B2 (en) * 2004-05-26 2007-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-filled openings for submicron devices and methods of manufacture thereof
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
KR100666380B1 (ko) * 2005-05-30 2007-01-09 삼성전자주식회사 포토레지스트 제거방법 및 이를 이용한 반도체 소자의 제조방법.
US9220301B2 (en) 2006-03-16 2015-12-29 R.J. Reynolds Tobacco Company Smoking article
JP2007311560A (ja) * 2006-05-18 2007-11-29 Toshiba Corp 半導体装置
US8669597B2 (en) 2008-05-06 2014-03-11 Spansion Llc Memory device interconnects and method of manufacturing
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
KR200452291Y1 (ko) * 2008-12-31 2011-02-15 엘에스산전 주식회사 배선용 차단기의 보조커버 고정장치
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) * 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
KR101883380B1 (ko) * 2011-12-26 2018-07-31 삼성전자주식회사 커패시터를 포함하는 반도체 소자
US9633847B2 (en) * 2015-04-10 2017-04-25 Tokyo Electron Limited Using sub-resolution openings to aid in image reversal, directed self-assembly, and selective deposition
US9576788B2 (en) 2015-04-24 2017-02-21 Applied Materials, Inc. Cleaning high aspect ratio vias
CN114361102A (zh) * 2021-11-30 2022-04-15 上海华力集成电路制造有限公司 接触孔工艺方法

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Also Published As

Publication number Publication date
KR100757888B1 (ko) 2007-09-11
KR100802698B1 (ko) 2008-02-12
US6444405B1 (en) 2002-09-03
KR20070034028A (ko) 2007-03-27
US20020098678A1 (en) 2002-07-25
US20040214428A1 (en) 2004-10-28
TW466749B (en) 2001-12-01
KR100770468B1 (ko) 2007-10-26
JP2001015712A (ja) 2001-01-19
KR20010029834A (ko) 2001-04-16
US20030148600A1 (en) 2003-08-07
US6770528B2 (en) 2004-08-03
KR20060128763A (ko) 2006-12-14

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