KR100770468B1 - 반도체 집적회로장치의 제조방법 - Google Patents

반도체 집적회로장치의 제조방법 Download PDF

Info

Publication number
KR100770468B1
KR100770468B1 KR1020000034824A KR20000034824A KR100770468B1 KR 100770468 B1 KR100770468 B1 KR 100770468B1 KR 1020000034824 A KR1020000034824 A KR 1020000034824A KR 20000034824 A KR20000034824 A KR 20000034824A KR 100770468 B1 KR100770468 B1 KR 100770468B1
Authority
KR
South Korea
Prior art keywords
film
delete delete
groove
photoresist
photoresist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020000034824A
Other languages
English (en)
Korean (ko)
Other versions
KR20010029834A (ko
Inventor
후루카와료이치
스코카즈유키
히라누마마사유키
사이토코이치
야마모토히로히코
요시다타다노리
이시자카마사유키
시모다마키
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 히타치세이사쿠쇼, 가부시키가이샤 히타치초에루. 에스. 아이. 시스테무즈 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20010029834A publication Critical patent/KR20010029834A/ko
Application granted granted Critical
Publication of KR100770468B1 publication Critical patent/KR100770468B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020000034824A 1999-07-01 2000-06-23 반도체 집적회로장치의 제조방법 Expired - Fee Related KR100770468B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP99-187450 1999-07-01
JP18745099A JP3998373B2 (ja) 1999-07-01 1999-07-01 半導体集積回路装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020060103766A Division KR100757888B1 (ko) 1999-07-01 2006-10-25 반도체 집적회로장치의 제조방법

Publications (2)

Publication Number Publication Date
KR20010029834A KR20010029834A (ko) 2001-04-16
KR100770468B1 true KR100770468B1 (ko) 2007-10-26

Family

ID=16206298

Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020000034824A Expired - Fee Related KR100770468B1 (ko) 1999-07-01 2000-06-23 반도체 집적회로장치의 제조방법
KR1020060103766A Expired - Fee Related KR100757888B1 (ko) 1999-07-01 2006-10-25 반도체 집적회로장치의 제조방법
KR1020070020994A Expired - Fee Related KR100802698B1 (ko) 1999-07-01 2007-03-02 반도체 집적회로장치의 제조방법

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020060103766A Expired - Fee Related KR100757888B1 (ko) 1999-07-01 2006-10-25 반도체 집적회로장치의 제조방법
KR1020070020994A Expired - Fee Related KR100802698B1 (ko) 1999-07-01 2007-03-02 반도체 집적회로장치의 제조방법

Country Status (4)

Country Link
US (4) US6444405B1 (enExample)
JP (1) JP3998373B2 (enExample)
KR (3) KR100770468B1 (enExample)
TW (1) TW466749B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3998373B2 (ja) * 1999-07-01 2007-10-24 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2001223345A (ja) * 1999-11-30 2001-08-17 Hitachi Ltd 半導体装置とその製造方法
KR100476399B1 (ko) * 2002-06-29 2005-03-16 주식회사 하이닉스반도체 반도체 장치의 캐패시터 제조방법
US20040084400A1 (en) 2002-10-30 2004-05-06 Gregory Costrini Patterning metal stack layers of magnetic switching device, utilizing a bilayer metal hardmask
KR100526869B1 (ko) * 2003-06-19 2005-11-09 삼성전자주식회사 반도체 메모리에서의 커패시터 하부 전극 형성방법
US7199045B2 (en) * 2004-05-26 2007-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-filled openings for submicron devices and methods of manufacture thereof
KR100668833B1 (ko) * 2004-12-17 2007-01-16 주식회사 하이닉스반도체 반도체소자의 캐패시터 제조방법
KR100666380B1 (ko) * 2005-05-30 2007-01-09 삼성전자주식회사 포토레지스트 제거방법 및 이를 이용한 반도체 소자의 제조방법.
US9220301B2 (en) 2006-03-16 2015-12-29 R.J. Reynolds Tobacco Company Smoking article
JP2007311560A (ja) * 2006-05-18 2007-11-29 Toshiba Corp 半導体装置
US8669597B2 (en) 2008-05-06 2014-03-11 Spansion Llc Memory device interconnects and method of manufacturing
US8513119B2 (en) 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
KR200452291Y1 (ko) * 2008-12-31 2011-02-15 엘에스산전 주식회사 배선용 차단기의 보조커버 고정장치
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) * 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
KR101883380B1 (ko) * 2011-12-26 2018-07-31 삼성전자주식회사 커패시터를 포함하는 반도체 소자
US9633847B2 (en) * 2015-04-10 2017-04-25 Tokyo Electron Limited Using sub-resolution openings to aid in image reversal, directed self-assembly, and selective deposition
US9576788B2 (en) 2015-04-24 2017-02-21 Applied Materials, Inc. Cleaning high aspect ratio vias
CN114361102A (zh) * 2021-11-30 2022-04-15 上海华力集成电路制造有限公司 接触孔工艺方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291526A (ja) * 1992-04-14 1993-11-05 Hitachi Ltd 半導体記憶装置
JPH10189898A (ja) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR19990007303A (ko) * 1997-06-25 1999-01-25 이데이 노부유키 반도체장치 및 그 제조방법
JPH11214646A (ja) * 1998-01-28 1999-08-06 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP2000156480A (ja) * 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
TW466749B (en) * 1999-07-01 2001-12-01 Hitachi Ltd Manufacturing method of semiconductor integrated circuit device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003864B1 (ko) 1992-01-06 1996-03-23 삼성전자주식회사 반도체 메모리장치 및 그 제조방법
US5270265A (en) * 1992-09-01 1993-12-14 Harris Corporation Stress relief technique of removing oxide from surface of trench-patterned semiconductor-on-insulator structure
US5670425A (en) * 1995-11-09 1997-09-23 Lsi Logic Corporation Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
US5900668A (en) * 1995-11-30 1999-05-04 Advanced Micro Devices, Inc. Low capacitance interconnection
US5914202A (en) * 1996-06-10 1999-06-22 Sharp Microeletronics Technology, Inc. Method for forming a multi-level reticle
US6051858A (en) * 1996-07-26 2000-04-18 Symetrix Corporation Ferroelectric/high dielectric constant integrated circuit and method of fabricating same
US5691215A (en) * 1996-08-26 1997-11-25 Industrial Technology Research Institute Method for fabricating a sub-half micron MOSFET device with insulator filled shallow trenches planarized via use of negative photoresist and de-focus exposure
US5716883A (en) * 1996-11-06 1998-02-10 Vanguard International Semiconductor Corporation Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns
JPH10173157A (ja) * 1996-12-06 1998-06-26 Toshiba Corp 半導体装置
US6150211A (en) * 1996-12-11 2000-11-21 Micron Technology, Inc. Methods of forming storage capacitors in integrated circuitry memory cells and integrated circuitry
US5981333A (en) * 1997-02-11 1999-11-09 Micron Technology, Inc. Methods of forming capacitors and DRAM arrays
US5905280A (en) * 1997-02-11 1999-05-18 Micron Technology, Inc. Capacitor structures, DRAM cell structures, methods of forming capacitors, methods of forming DRAM cells, and integrated circuits incorporating capacitor structures and DRAM cell structures
JPH1117144A (ja) 1997-06-26 1999-01-22 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6380096B2 (en) * 1998-07-09 2002-04-30 Applied Materials, Inc. In-situ integrated oxide etch process particularly useful for copper dual damascene
JP3337067B2 (ja) 1999-05-07 2002-10-21 日本電気株式会社 円筒形キャパシタ下部電極の製造方法
US6146517A (en) * 1999-05-19 2000-11-14 Infineon Technologies North America Corp. Integrated circuits with copper metallization for interconnections
US6403442B1 (en) * 1999-09-02 2002-06-11 Micron Technology, Inc. Methods of forming capacitors and resultant capacitor structures

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05291526A (ja) * 1992-04-14 1993-11-05 Hitachi Ltd 半導体記憶装置
JPH10189898A (ja) * 1996-12-24 1998-07-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR19990007303A (ko) * 1997-06-25 1999-01-25 이데이 노부유키 반도체장치 및 그 제조방법
JPH11214646A (ja) * 1998-01-28 1999-08-06 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
JP2000156480A (ja) * 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
TW466749B (en) * 1999-07-01 2001-12-01 Hitachi Ltd Manufacturing method of semiconductor integrated circuit device
US20020098678A1 (en) * 1999-07-01 2002-07-25 Hitachi, Ltd. Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate
US6444405B1 (en) * 1999-07-01 2002-09-03 Hitachi, Ltd. Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate
US20030148600A1 (en) * 1999-07-01 2003-08-07 Hitachi, Ltd. Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate
US6770528B2 (en) * 1999-07-01 2004-08-03 Hitachi Ulsi Systems Co., Ltd. Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate
US20040214428A1 (en) * 1999-07-01 2004-10-28 Renesas Technology Corporation Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate

Also Published As

Publication number Publication date
KR100757888B1 (ko) 2007-09-11
KR100802698B1 (ko) 2008-02-12
US6444405B1 (en) 2002-09-03
KR20070034028A (ko) 2007-03-27
JP3998373B2 (ja) 2007-10-24
US20020098678A1 (en) 2002-07-25
US20040214428A1 (en) 2004-10-28
TW466749B (en) 2001-12-01
JP2001015712A (ja) 2001-01-19
KR20010029834A (ko) 2001-04-16
US20030148600A1 (en) 2003-08-07
US6770528B2 (en) 2004-08-03
KR20060128763A (ko) 2006-12-14

Similar Documents

Publication Publication Date Title
KR100802698B1 (ko) 반도체 집적회로장치의 제조방법
KR100699335B1 (ko) 반도체 집적회로 장치 및 그 제조방법
US6258649B1 (en) Semiconductor integrated circuit device and method of manufacturing the same
US6037216A (en) Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process
US5686337A (en) Method for fabricating stacked capacitors in a DRAM cell
US6770527B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US6177307B1 (en) Process of planarizing crown capacitor for integrated circuit
US6806195B1 (en) Manufacturing method of semiconductor IC device
KR101168606B1 (ko) 반도체 장치의 배선 구조물 및 이의 형성 방법
US20080251824A1 (en) Semiconductor memory device and manufacturing method thereof
US6426255B1 (en) Process for making a semiconductor integrated circuit device having a dynamic random access memory
US5536673A (en) Method for making dynamic random access memory (DRAM) cells having large capacitor electrode plates for increased capacitance
US20100244271A1 (en) Semiconductor device and manufacturing method thereof
US6967161B2 (en) Method and resulting structure for fabricating DRAM cell structure using oxide line spacer
US6521522B2 (en) Method for forming contact holes for metal interconnection in semiconductor devices
JP3002665B2 (ja) ダイナミックランダムアクセスメモリのクラウンタイプキャパシタに関する方法
JPH11297951A (ja) 半導体集積回路装置およびその製造方法
US6617211B1 (en) Method for forming a memory integrated circuit
KR100548594B1 (ko) 디램의 커패시터 노드 형성방법
US6673719B2 (en) Method for etching using a multilevel hard mask
JP2006191137A (ja) 半導体集積回路装置の製造方法
JP4133039B2 (ja) 半導体集積回路装置の製造方法および半導体集積回路装置
JPH11186522A (ja) 半導体集積回路装置およびその製造方法
KR20010083349A (ko) 광범위하게 평탄화된 반도체 소자의 제조방법
JPH1187263A (ja) 半導体集積回路装置の製造方法

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R11-asn-PN2301

St.27 status event code: A-3-3-R10-R13-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

A107 Divisional application of patent
PA0107 Divisional application

St.27 status event code: A-0-1-A10-A16-div-PA0107

St.27 status event code: A-0-1-A10-A18-div-PA0107

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

T12-X000 Administrative time limit extension not granted

St.27 status event code: U-3-3-T10-T12-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

Fee payment year number: 1

St.27 status event code: A-2-2-U10-U11-oth-PR1002

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

Fee payment year number: 4

St.27 status event code: A-4-4-U10-U11-oth-PR1001

PR1001 Payment of annual fee

Fee payment year number: 5

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20120924

Year of fee payment: 6

PR1001 Payment of annual fee

Fee payment year number: 6

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20130924

Year of fee payment: 7

PR1001 Payment of annual fee

Fee payment year number: 7

St.27 status event code: A-4-4-U10-U11-oth-PR1001

FPAY Annual fee payment

Payment date: 20141001

Year of fee payment: 8

PR1001 Payment of annual fee

Fee payment year number: 8

St.27 status event code: A-4-4-U10-U11-oth-PR1001

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

R17-X000 Change to representative recorded

St.27 status event code: A-5-5-R10-R17-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20150917

Year of fee payment: 9

PR1001 Payment of annual fee

Fee payment year number: 9

St.27 status event code: A-4-4-U10-U11-oth-PR1001

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Not in force date: 20161020

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

St.27 status event code: A-4-4-U10-U13-oth-PC1903

PC1903 Unpaid annual fee

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20161020

St.27 status event code: N-4-6-H10-H13-oth-PC1903

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000