JP3615206B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3615206B2 JP3615206B2 JP2002247847A JP2002247847A JP3615206B2 JP 3615206 B2 JP3615206 B2 JP 3615206B2 JP 2002247847 A JP2002247847 A JP 2002247847A JP 2002247847 A JP2002247847 A JP 2002247847A JP 3615206 B2 JP3615206 B2 JP 3615206B2
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- Prior art keywords
- solder
- bump
- electrode
- resin film
- film
- Prior art date
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Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002247847A JP3615206B2 (ja) | 2001-11-15 | 2002-08-27 | 半導体装置の製造方法 |
US10/291,766 US6689639B2 (en) | 2001-11-15 | 2002-11-12 | Method of making semiconductor device |
KR1020020070402A KR100963372B1 (ko) | 2001-11-15 | 2002-11-13 | 반도체 장치의 제조 방법 |
TW091133424A TWI275144B (en) | 2001-11-15 | 2002-11-14 | Method of manufacturing semiconductor device |
CNB021495823A CN1220250C (zh) | 2001-11-15 | 2002-11-15 | 半导体器件的制造方法 |
KR1020080125793A KR100894929B1 (ko) | 2001-11-15 | 2008-12-11 | 반도체 장치의 제조 방법 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001-350720 | 2001-11-15 | ||
JP2001350720 | 2001-11-15 | ||
JP2002247847A JP3615206B2 (ja) | 2001-11-15 | 2002-08-27 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004238471A Division JP4025322B2 (ja) | 2001-11-15 | 2004-08-18 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2003218152A JP2003218152A (ja) | 2003-07-31 |
JP3615206B2 true JP3615206B2 (ja) | 2005-02-02 |
Family
ID=26624544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002247847A Expired - Fee Related JP3615206B2 (ja) | 2001-11-15 | 2002-08-27 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6689639B2 (ko) |
JP (1) | JP3615206B2 (ko) |
KR (2) | KR100963372B1 (ko) |
CN (1) | CN1220250C (ko) |
TW (1) | TWI275144B (ko) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6732913B2 (en) * | 2001-04-26 | 2004-05-11 | Advanpack Solutions Pte Ltd. | Method for forming a wafer level chip scale package, and package formed thereby |
JP2003198117A (ja) * | 2001-12-28 | 2003-07-11 | Matsushita Electric Ind Co Ltd | はんだ付け方法および接合構造体 |
JP2004349440A (ja) * | 2003-05-22 | 2004-12-09 | Renesas Technology Corp | フリップチップ実装方法 |
TWI220304B (en) * | 2003-06-20 | 2004-08-11 | Advanced Semiconductor Eng | Flip-chip package substrate and flip-chip bonding process thereof |
US7276801B2 (en) * | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
JP4726409B2 (ja) * | 2003-09-26 | 2011-07-20 | 京セラ株式会社 | 半導体素子及びその製造方法 |
JP2005116632A (ja) | 2003-10-03 | 2005-04-28 | Rohm Co Ltd | 半導体装置の製造方法および半導体装置 |
JP2005175128A (ja) * | 2003-12-10 | 2005-06-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP3829860B2 (ja) * | 2004-01-30 | 2006-10-04 | 株式会社デンソー | 半導体チップの製造方法 |
JP2005268425A (ja) * | 2004-03-17 | 2005-09-29 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2006032619A (ja) * | 2004-07-15 | 2006-02-02 | Hitachi Ltd | 低耐熱性表面実装部品及びこれをバンプ接続した実装基板 |
US20060024943A1 (en) * | 2004-07-30 | 2006-02-02 | Kang Sung K | Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present |
JP3964911B2 (ja) * | 2004-09-03 | 2007-08-22 | 松下電器産業株式会社 | バンプ付き基板の製造方法 |
TWI236048B (en) * | 2004-10-21 | 2005-07-11 | Advanced Semiconductor Eng | Method for flip chip bonding by utilizing an interposer with embeded bumps |
JP4822694B2 (ja) * | 2004-11-22 | 2011-11-24 | 京セラ株式会社 | 半導体素子及び半導体素子実装基板 |
JP2006165252A (ja) * | 2004-12-07 | 2006-06-22 | Shinko Electric Ind Co Ltd | チップ内蔵基板の製造方法 |
TWI253697B (en) * | 2005-04-08 | 2006-04-21 | Phoenix Prec Technology Corp | Method for fabricating a flip chip package |
US20070111500A1 (en) * | 2005-11-01 | 2007-05-17 | Cowens Marvin W | Method and apparatus for attaching solder balls to substrate |
KR100718169B1 (ko) * | 2006-01-12 | 2007-05-15 | 한국과학기술원 | 니켈 표면 처리된 전자부품과 무전해 니켈 표면 처리된전자부품의 접합방법 |
JP2007220959A (ja) * | 2006-02-17 | 2007-08-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP5162851B2 (ja) | 2006-07-14 | 2013-03-13 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US20080136019A1 (en) * | 2006-12-11 | 2008-06-12 | Johnson Michael E | Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications |
KR20090101435A (ko) * | 2006-12-25 | 2009-09-28 | 로무 가부시키가이샤 | 반도체 장치 |
JP5058714B2 (ja) * | 2007-08-21 | 2012-10-24 | スパンション エルエルシー | 半導体装置及びその製造方法 |
JP2009099589A (ja) * | 2007-10-12 | 2009-05-07 | Elpida Memory Inc | ウエハまたは回路基板およびその接続構造体 |
KR20090080623A (ko) * | 2008-01-22 | 2009-07-27 | 삼성전기주식회사 | 포스트 범프 및 그 형성방법 |
KR100975654B1 (ko) * | 2008-02-26 | 2010-08-17 | 한국과학기술원 | Co가 첨가된 Sn-3.5Ag 솔더와 Ni-P 하부금속층간의 접합 신뢰성이 향상된 솔더 접합 구조 |
US20100032194A1 (en) * | 2008-08-08 | 2010-02-11 | Ibiden Co., Ltd. | Printed wiring board, manufacturing method for printed wiring board and electronic device |
JP2010232230A (ja) * | 2009-03-25 | 2010-10-14 | Casio Computer Co Ltd | 半導体装置およびその製造方法 |
EP2449582A4 (en) * | 2009-07-02 | 2013-06-12 | Flipchip Internat L L C | METHODS AND STRUCTURES FOR VERTICAL COLUMN INTERCONNECTION |
US9627254B2 (en) | 2009-07-02 | 2017-04-18 | Flipchip International, Llc | Method for building vertical pillar interconnect |
JP5307669B2 (ja) | 2009-09-09 | 2013-10-02 | 東京エレクトロン株式会社 | 半導体装置の製造方法及び電気的接続を得る方法 |
JP5508802B2 (ja) * | 2009-09-30 | 2014-06-04 | 株式会社東芝 | 半導体装置の製造方法 |
TWM397591U (en) * | 2010-04-22 | 2011-02-01 | Mao Bang Electronic Co Ltd | Bumping structure |
CN102034721B (zh) | 2010-11-05 | 2013-07-10 | 南通富士通微电子股份有限公司 | 芯片封装方法 |
CN102034720B (zh) | 2010-11-05 | 2013-05-15 | 南通富士通微电子股份有限公司 | 芯片封装方法 |
JP6111584B2 (ja) * | 2012-03-06 | 2017-04-12 | 三菱マテリアル株式会社 | はんだバンプの製造方法 |
US20130241058A1 (en) * | 2012-03-16 | 2013-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wire Bonding Structures for Integrated Circuits |
KR101362306B1 (ko) * | 2012-06-05 | 2014-02-13 | 주식회사 심텍 | 인쇄회로기판의 도금층 형성 방법 및 이에 의해 형성된 패키지용 인쇄회로기판 |
JP2014187354A (ja) * | 2013-02-21 | 2014-10-02 | Ricoh Co Ltd | デバイス、及びデバイスの作製方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3015436B2 (ja) | 1990-09-25 | 2000-03-06 | 株式会社東芝 | 半導体装置およびその接続方法 |
JP2784122B2 (ja) | 1992-10-29 | 1998-08-06 | ローム株式会社 | 半導体装置の製法 |
JP3266414B2 (ja) | 1994-05-09 | 2002-03-18 | 三菱電機株式会社 | はんだ供給法 |
US5539153A (en) | 1994-08-08 | 1996-07-23 | Hewlett-Packard Company | Method of bumping substrates by contained paste deposition |
JPH104098A (ja) * | 1996-06-14 | 1998-01-06 | Denso Corp | バンプ電極形成方法 |
JP3352352B2 (ja) * | 1997-03-31 | 2002-12-03 | 新光電気工業株式会社 | めっき装置、めっき方法およびバンプの形成方法 |
JPH11214421A (ja) * | 1997-10-13 | 1999-08-06 | Matsushita Electric Ind Co Ltd | 半導体素子の電極形成方法 |
JPH11340270A (ja) | 1998-05-29 | 1999-12-10 | Matsushita Electric Ind Co Ltd | はんだバンプ形成方法及び半導体モジュールの製造方法 |
US6028011A (en) | 1997-10-13 | 2000-02-22 | Matsushita Electric Industrial Co., Ltd. | Method of forming electric pad of semiconductor device and method of forming solder bump |
JPH11260847A (ja) * | 1998-03-13 | 1999-09-24 | Fujitsu Ltd | 半田バンプの形成方法 |
JP3410403B2 (ja) * | 1999-09-10 | 2003-05-26 | 東京応化工業株式会社 | ホトレジスト用剥離液およびこれを用いたホトレジスト剥離方法 |
US6465879B1 (en) * | 1999-10-19 | 2002-10-15 | Citizen Watch Co., Ltd. | Structure for mounting semiconductor device, method of mounting same, semiconductor device, and method of fabricating same |
JP3397313B2 (ja) * | 1999-12-20 | 2003-04-14 | 富士通株式会社 | 半導体装置の製造方法及び電子部品の実装方法 |
JP3636429B2 (ja) | 2000-11-27 | 2005-04-06 | 株式会社ミツトヨ | 波長安定化標準光源 |
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KR100963372B1 (ko) | 2010-06-15 |
US6689639B2 (en) | 2004-02-10 |
US20030096494A1 (en) | 2003-05-22 |
JP2003218152A (ja) | 2003-07-31 |
CN1220250C (zh) | 2005-09-21 |
KR100894929B1 (ko) | 2009-04-27 |
TWI275144B (en) | 2007-03-01 |
KR20090006037A (ko) | 2009-01-14 |
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