JP2717993B2 - 導電性ポリマー及び絶縁体を使用したフリツプチツプ技術 - Google Patents

導電性ポリマー及び絶縁体を使用したフリツプチツプ技術

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Publication number
JP2717993B2
JP2717993B2 JP3502870A JP50287091A JP2717993B2 JP 2717993 B2 JP2717993 B2 JP 2717993B2 JP 3502870 A JP3502870 A JP 3502870A JP 50287091 A JP50287091 A JP 50287091A JP 2717993 B2 JP2717993 B2 JP 2717993B2
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Prior art keywords
flip chip
conductive
substrate
bond pad
layer
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JP3502870A
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JPH05503191A (ja
Inventor
エステス，リチヤード・エイチ
クレスザ，フランク・ダブリュー
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エポキシ・テクノロジー・インコーポレーテツド
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
    • Y10T156/1092—All laminae planar and face to face
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
  • Polyoxymethylene Polymers And Polymers With Carbon-To-Carbon Bonds (AREA)
  • Other Resins Obtained By Reactions Not Involving Carbon-To-Carbon Unsaturated Bonds (AREA)
  • Organic Insulating Materials (AREA)

Description

【発明の詳細な説明】 背景技術 集積回路は、通信用及び軍用技術へのほとんど万能的
な用途を何年間も持ってきた。関心のある重要なこと
は、超小形電子回路ウェーファー及び自動装置による回
路接続方法の開発であった。超小形電子回路技術の応用
についての主な限定は、費用効率及び小寸法のチップの
ためのチップ上の集積回路の相互接続の信頼性であっ
た。チップは、各回路内に何百もの接続を作ることをし
ばしば必要とする。
回路の相互接続の一方法は、フリップチップボンディ
ングと呼ばれる。フリップチップ上のボンドパッドはチ
ップの周辺には限定されずかつ通常は基板に向かい合っ
たチップの一方の面に置かれるため、フリップチップボ
ンディングは信号経路をより短縮でき、従って、テープ
ボンディング（TAB）又は通常のワイヤーボンディング
のようなその他の方法でできるより迅速な回路間の連絡
ができる。フリップチップボンディングの一方法におい
ては、チップ又はダイは、所望の集積回路、並びにこの
回路を別の印刷回路ボード又は基板のような回路ボード
上の別のチップ回路に接続するに要する接続配線を有し
て形成される。相互接続点にボンドパッドが置かれる。
フリップチップのボンドパッド上に数層の金属層をめっ
きすることによりバンプが形成される。堆積に続いて、
金属をリフローさせるようにチップが加熱され、堆積物
の表面張力のため半球状の半田の「バンプ」が形成され
る。次に、フリップチップを一部分とするウェーファー
からフリップチップが切断され、かつ基板のボンドパッ
ドと揃うように「フリップ」される。次いで、これらの
バンプは基板のボンドパッドと接触させられ均一に加熱
され、フリップチップ及び基板の揃えられたボンドパッ
ド間の接続を同時に形成する。
フリップチップ及び基板のボンドパッドを接続するた
めの金属の使用には、チタニウム（Ti）、タングステン
（Ｗ）又は窒化シリコン（Si3N4）のような金属障壁の
使用により作られるフリップチップの不活性化が要求さ
れる。不活性化（又は障壁）物質としての金属、及び基
板材としてのセラミックの両者は、フリップチップと基
板との間を、どちらにも結果として生ずる損傷を与える
ことなしに接続するために、半田バンプのリフローがで
きるに十分な加熱ができることが一般に必要である。
バンプの作られたフリップチップを使用した回路の製
作は、フリップチップと基板との間の接続を目視検査で
きないことによっても制限される。更に、仕上げられ取
り付けられた回路の生産は、フリップチップ、不活性
層、半田バンプ及び基板を含んだ種々の材料の熱膨張係
数間の相異ににより生ずる接続失敗により不利益な影響
をうけることがある。また、半田バンプの溶融は望まし
くない副産物として導電性フラックスを生じ、一般にこ
れは仕上げられた回路が適正に作動できるように基板と
フリップチップとの間から除去しなければならない。
製作中の熱応力の問題は、熱的な膨張と収縮とにより
生ずる内部応力によるフリップチップ、基板及び接続部
への損傷を最小にするために、バンプの作られたフリッ
プチップへの急速な加熱及び半田接合部からの熱の急速
な伝導によるような種々の方法で処理されてきた。しか
し、この方法は費用が非常に多くかかる。
従って、迅速で費用効果がよくかつ信頼性があり、従
ってその他の形式の超小形電子回路ウェーファー上のフ
リップチップの利点をより完全に利用しうる基板へのフ
リップチップの接続方法に対する要求が存在する。ま
た、めっき工程を実施する必要性をなくす基板への簡単
化されたフリップチップの接続方法についての要求もあ
る。更に、不活性化と基板選択の融通性を増しうる方法
もまた望ましい。これらの改良は、費用効率を向上させ
かつ超小形電子回路に適した応用を広げる。
発明の開示 本発明は、バンプ付きフリップチップの技術、及びバ
ンプ付きフリップチップのボンドパッドを基板のボンド
パッドに接続するための方法に関する。本発明により、
有機保護層が、暴露されたフリップチップのボンドパッ
ドを残してフリップチップの表面上に選択的に形成され
る。有機保護層より先に延びる「バンプ」を形成するよ
うにフリップチップのボンドパッドに導電性で重合可能
な前駆物質が置かれる。あるいは、一緒にバンプを形成
している２個の層に、各ボンドパッドにおいて導電性の
重合可能な前駆物質を形成することができる。この２層
は、バンプと基板のボンドパッドとの接続より前に、導
電性バンプを形成するようにこれを重合させることがで
きる。次いで、実質的に重合されたバンプと基板との間
を「ウエット」状態、又は電気的接続の状態とするため
に、接着剤が基板のボンドパッドに塗布される。これに
より、フリップチップのボンドパッドと基板のボンドパ
ッドとの間に選択的な導電性ポリマーが選択的に形成さ
れる。あるいは、フリップチップのボンドパッドを基板
のボンドパッドに接続した後でバンプを重合させること
ができる。
フリップチップのボンドパッドにおける導電性の重合
可能な前駆物質の形成により、フリップチップのボンド
パッドと基板のボンドパッドとの間の電気接続が得られ
る。バンプの重合は、半田のリフローに要求されるより
も低温の中間的な熱条件下で達成できる。従って、急速
加熱により、かつフリップチップ、不活性層、バンプ及
び基板における構成材料の熱膨張係数の大きな不一致に
より生ずる信頼性の問題を相当に減少させることができ
る。更に、重合条件は半田バンプのリフローに必要な条
件よりも厳しくはないので、フリップチップの金属不活
性化の必要が無くされかつ広範囲の基板形式が可能とな
る。また、半田バンプの堆積のための複雑かつ時間のか
かる蒸着及び電気めっき技術が無くされる。更に、ポリ
マー接続はフラックス無しであり、従ってフリップチッ
プと基板との間の導電性フラックスの除去に伴う困難な
問題を無くす。有機保護層はまた低い比誘電率（low di
electric constant）を持ち、このため不活性層として
作用し、フリップチップを基板に極めて接近させること
を可能とし、従って完成した回路における回路経路を短
くする。
本発明の上述の特徴及びその他の詳細は、本発明の諸
段階又は本発明の部分の組み合わせとして、付属図面を
参照してより詳細に説明され、請求範囲に説明されるで
あろう。本発明の特別の実施例は説明の方途として示さ
れ本発明を限定するものではないことが理解されよう。
本発明の原理は本発明の範囲より離れることなく種々の
実施例に使用することができる。
図面の簡単な説明 図１は、フリップチップの面の上の有機保護層の選択
形成後の本発明の一実施例の平面図である。
図２は線Ｉ−Ｉに沿って得られた図１の実施例の断面
図である。
図３は、上に有機保護層が形成された窒化シリコン又
は酸化物の層のある不活性化されたフリップチップの断
面図である。
図４は、フリップチップのボンドパッド上の導電性で
重合可能な前駆物質の第１層の形成後の図１の実施例の
断面図である。
図５はバンプを形成するための第１層上の導電性で重
合可能な前駆物質の第２層の形成後の図１の実施例の断
面図である。
図６は本発明を使用するに適切な基板の平面図であ
る。
図７は、図１の実施例、及びフリップチップのバンプ
と基板のボンドパッドとを揃えた後の図６の線VI−VIに
沿って得られた基板の断面図である。
図８は、基板のボンドパッドへのフリップチップのバ
ンプの接触後の図１の実施例の断面図である。
図９は本発明の第３の実施例の断面図であり、これに
おいては、バンプは導電性ポリマーを形成するように重
合され、また基板のボンドパッドへのフリップチップの
バンプの接触以前に基板のボンドパッドに導電性接着剤
が塗布されている。
図10は、基板のボンドパッドへのバンプの接触及びフ
リップチップのボンドパッドと基板のボンドパッドとの
間の電気接続を形成するための接着剤の重合の後の図９
の実施例の断面図である。
発明を実施するための最良の形態 図１に示された本発明の一実施例においては、フリッ
プチップ10の簡略化された図が示される。これはフリッ
プチップのダイ11の上側平面16上のボンドパッド12、14
よりなる。ダイ11は、シリコン、ガリウム砒素、ゲルマ
ニウム又はその他の通常の半導体材料で形成される。図
２に見られるように、有機保護層18がスクリーン印刷、
ステンシル、スピンエッチングにより、あるいはその他
のモノマー又はポリマー塗布方法により、（ボンドパッ
ドに接続された）回路15及びフリップチップ10の表面16
上に形成される。あるいは、図３に示されるように、フ
リップチップ10は、有機保護層18の形成以前に窒化シリ
コン層又は酸化物層19により、これを不活性化すること
もできる。有機保護層は、好ましくは誘電性ポリマーで
ある。本発明における応用に適切な有機材料の一例はエ
ポキシテクノロジー・インク（Epoxy Technology,In
c.）製造のEpo−Tek（商品名）ポリイミドである。ボン
ドパッド12、14は有機保護層18の堆積中は被覆され、次
いで図２に示されるように次の堆積工程を受ける。有機
保護層18は、図４に示されるボンドパッド12、14上の層
20、22の形成より前に、加熱により、又はその他の通常
の手段により重合されることが好ましい。有機保護層18
は不活性化され、これによりフリップチップ10の下層16
を絶縁し保護する。
図４に示されるように、導電性で重合可能な前駆物質
の第１の層20、22がボンドパッド12、14上に選択的に形
成される。ここに使用される用語、導電性で重合可能な
前駆物質は、重合の際、又は更なる重合の際に導電性で
あり、あるいは導電性物質を支持しうる熱硬化性ポリマ
ー、Ｂステージポリマー、熱可塑性ポリマー、又は適宜
のモノマー又はポリマーを含むことができる。導電性の
重合可能な前駆物質は金、銀、又はその他の導電性物質
を含有することができる。有機保護層18は、フリップチ
ップ10上のモノマーの第１の層20、22の堆積の領域を定
めるテンプレートとして作用する。本発明の好ましい実
施例においては、重合されない有機保護層は、表面16上
にパターンを保持する高度の界面活性を持つ。これによ
り、フリップチップ10は、これに続くボンドパッド12、
14上への導電性の重合可能な前駆物質の堆積中における
取り扱いをより便利にすることができる。第１の層20、
22はポリイミド層18と実質的に同一面である。図５に示
されるように、第１の層20、22の形成に使用されるよう
な導電性の重合可能な前駆物質の第２の層24、26が第１
の層20、22の上に形成される。第１の層20、22及び第２
の層24、26がフリップチップ10上のバンプ28、30を形成
する。図６に示されるように、基板36上の回路33がボン
ドパッド32、34と接続される。図７に見られるように、
基板36上のボンドパッド32、34の既知の位置に揃えられ
た位置にフリップチップ10上のバンプ28、30が置かれ
る。次いで、図８に示されるように、ボンドパッド32、
34がバンプ28、30と接触させられる。次に、加熱、又は
その他の公知方法によりバンプ28、30が重合され、フリ
ップチップのボンドパッド12、14と基板のボンドパッド
32、34との間の電気接続が形成される。本発明による使
用に適した基板は、セラミック、シリコン、ポーセレ
ン、通常の印刷回路ボード材、又は電気回路に適したそ
の他の通常の基板のような素材を含む。
導電性の重合可能な前駆物質が熱硬化性である場合
は、第１の層20、22は第２の層24、26の形成以前にこれ
を重合させることができる。第２の層24、26は基板のボ
ンドパッド32、34と接触するより前に、これを半球状の
形にすることができる。第１の層20、22及び第２の層2
4、26がバンプ28、30を形成し、重合より前に基板のボ
ンドパッド32、34と接触させることができる。続いて、
バンプ28、30が重合され、フリップチップのボンドパッ
ド12、14と基板のボンドパッド32、34との間の電気接続
を形成する。あるいは、第１の層20、22は、第２の層2
4、26の堆積以前にこれを重合させることができる。
図９に示されたような本発明の別の実施例において
は、基板のボンドパッド32、34との接触以前に重合され
る導電性の重合可能な前駆物質でバンプ28、30を形成す
ることができる。図９に示されるように、バンプ28、30
が基板のボンドパッド32、34と接触させられるより前
に、接着剤層38、40が基板のボンドパッド32、24上に形
成される。使用しうる接着剤の例は、熱硬化性、熱可塑
性及びポリマーの厚膜を含む。接着剤層38、40は、スク
リーン印刷、ステンシルにより、又はその他の通常の方
法により、基板のボンドパッド32、34上に形成される。
図11に示されるように、バンプ28、30が接着剤層38、40
と接触させられ、更に加熱により、又はその他の通常の
手段により導電性接着剤が重合され、フリップチップ10
のボンドパッド12、14と基板36のボンドパッド32、34と
の間の電気接続を形成する。
バンプ28、30の第１の層20、22及び第２の層24、26の
形成に使用される導電性の重合可能な前駆物質（precur
sor）は、Ｂステージポリマーとすることができる。適
切なＢステージポリマーの例は、熱硬化性及び熱可塑性
プラスチックを含む。バンプ28、30が基板のボンドパッ
ド32、34に接触させられる前に、バンプ28、30を構成す
る導電性の重合可能な前駆物質からＢステージポリマー
内の溶剤を実質的に蒸発させることができる。Ｂステー
ジポリマー内の溶剤の蒸発により、バンプ28、30は、フ
リップチップがバンプ28、30を基板36に接触するように
操作される間、実質的に強固な形状を保持する。Ｂステ
ージポリマーは、フリップチップのボンドパッド12、14
と基板のボンドパッド32、34との間の電気接続を形成す
るように、これを実質的に重合させることができる。
好ましい実施例においては、フリップチップ11は、ア
メリカン・オプティカル・コーポレーションのリサーチ
・デバイス・デビィジョンにより製造のモデルＭ−８の
ようなフリップチップアライナーボンダーにより基板36
上に整列される。
相当事項 好ましい実施例がここに特に説明され図解されたが、
本発明の精神及び範囲より離れることなく、以下の請求
範囲内において、上述の教示に照らし、本発明の多くの
変更及び変化が可能であることが認識されよう。例え
ば、フリップチップが１個の回路と２個のボンドパッド
とだけしかない基板上の単一のフリップチップについて
説明されたが、この理念は、各が多数の回路とボンドパ
ッドのある多数のチップを含むように容易に拡張しうる
ことを理解すべきである。

Claims (23)

    (57)【特許請求の範囲】
  1. 【請求項１】フリップチップのボンドパッドと基板のボ
    ンドパッドとの間の導電性相互接続を形成する方法にし
    て、 ａ）露出されるボンドパッドを残して、フリップチップ
    のボンドパッドの置かれる表面上に有機保護層を選択的
    に形成し； ｂ）バンプを作るためにフリップチップのボンドパッド
    上に保護層より先に延びる高さに導電性の重合可能な前
    駆物質を形成し； ｃ）バンプを基板のボンドパッドに接触し；更に ｄ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性相互接続を形成する
    ようにバンプを重合する諸段階を含んだ方法。
  2. 【請求項２】有機保護層が絶縁ポリマーであり、かつ導
    電性の重合可能な前駆物質がフリップチップのボンドパ
    ッド上にスクリーン印刷される請求項１の方法。
  3. 【請求項３】保護層が絶縁ポリマーで形成され、更に導
    電性の重合可能な前駆物質がフリップチップのボンドパ
    ッド上にステンシル塗布される請求項１の方法。
  4. 【請求項４】有機保護塗膜がフリップチップ上の導電性
    の重合可能な前駆物質を形成する領域を定める請求項１
    の方法。
  5. 【請求項５】フリップチップのボンドパッドと基板のボ
    ンドパッドとの間の導電性相互接続を形成する方法にし
    て、 ａ）露出されるボンドパッドを残して、フリップチップ
    のボンドパッドの置かれる表面上に有機保護層を選択的
    に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）第１の層の上に導電性の重合可能な前駆物質の第２
    の層を形成し、第２の層と第１の層とが一緒にバンプを
    形成し； ｄ）バンプを基板のボンドパッドに接触し；更に ｅ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性の相互接続を形成す
    るようにバンプを重合する諸段階を含んだ方法。
  6. 【請求項６】有機保護層が絶縁ポリマーである請求項５
    の方法。
  7. 【請求項７】第２の層が第１の層の上にスクリーン印刷
    される請求項６の方法。
  8. 【請求項８】第２の層が第１の層の上にステンシル塗布
    される請求項７の方法。
  9. 【請求項９】有機保護塗膜が、フリップチップ上の導電
    性の重合可能な前駆物質を形成する領域を定める請求項
    ５の方法。
  10. 【請求項１０】フリップチップのボンドパッドと基板の
    ボンドパッドとの間の導電性相互接続を形成する方法に
    して、 ａ）露出されるボンドパッドを残して、フリップチップ
    のボンドパッドの置かれる表面上に有機保護層を選択的
    に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）第１の層を乾燥し； ｄ）有機保護層より先に延びる高さに第１の層の上に導
    電性の重合可能な前駆物質の第２の層を形成し； ｅ）フリップチップ上のバンプを形成するように第２の
    層を乾燥し； ｆ）バンプを基板のボンドパッドに接触し；更に ｇ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性相互接続を形成する
    ようにバンプを重合する諸段階を含んだ方法。
  11. 【請求項１１】フリップチップのボンドパッドと基板の
    ボンドパッドとの間の導電性相互接続を形成する方法に
    して、 ａ）露出されるボンドパッドを残して、フリップチップ
    のボンドパッドの置かれる表面上に有機保護層を選択的
    に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）導電性ポリマーを形成するように第１の層を重合
    し； ｄ）第１の層の上に有機保護層より先に延びる高さに導
    電性の重合可能な前駆物質の第２の層を形成し； ｅ）フリップチップのボンドパッド上に導電性バンプを
    形成するように第２の層を重合し； ｆ）基板のボンドパッドに導電性接着剤を塗布し； ｇ）接着剤を導電性バンプに接触し；更に ｈ）導電性接着剤が基板のボンドパッド及びフリップチ
    ップのボンドパッドに接触している間に導電性接着剤を
    重合し、これによりフリップチップのボンドパッドと基
    板のボンドパッドとの間の導電性相互接続を形成する 段階を含んだ方法。
  12. 【請求項１２】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）第１の層を乾燥し； ｄ）保護層より先に延びる高さに第１の層の上に導電性
    の重合可能な前駆物質の第２の層を形成し； ｅ）フリップチップ上のバンプを形成するように第２の
    層を乾燥し； ｆ）バンプを基板のボンドパッドに接触し；更に ｇ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性の相互接続を形成す
    るようにバンプを重合する諸段階を含んだフリップチッ
    プのボンドパッドと基板のボンドパッドとを電気的に相
    互接続する方法により形成された物品。
  13. 【請求項１３】第１及び第２の層の重合される導電性の
    前駆物品がＢステージポリマーである請求項12の物品。
  14. 【請求項１４】第１及び第２の層の重合された導電性の
    前駆物品が熱可塑性ポリマーである請求項12の物品。
  15. 【請求項１５】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）導電性ポリマーを形成するように第１の層を重合
    し； ｄ）有機保護層より先に延びる高さに第１の層の上に導
    電性の重合可能な前駆物質の第２の層を形成し； ｅ）導電性ポリマーを形成するように第２の層を重合
    し、第１の層及び第２の層はこれによりフリップチップ
    のボンドパッド上の導電性バンプを形成し； ｆ）基板のボンドパッドに導電性接着剤を塗布し； ｇ）基板のボンドパッドにおける導電性接着剤を導電性
    バンプに接触し、更に ｈ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間に導電性相互接続を形成する
    ように導電性バンプを重合する諸段階を含んだフリップ
    チップのボンドパッドと基板のボンドパッドとを電気的
    に相互接続する方法により形成された物品。
  16. 【請求項１６】第１及び第２の層の導電性ポリマーが熱
    硬化性のもので形成される請求項15の物品。
  17. 【請求項１７】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）バンプを作るためにフリップチップのボンドパッド
    上に保護層より先に延びる高さに導電性の重合可能な前
    駆物質を形成し； ｃ）バンプを基板のボンドパッドに接触し；更に ｄ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間に導電性相互接続を形成する
    ようにバンプを重合する諸段階を含んだフリップチップ
    のボンドパッドと基板のボンドパッドとの間の導電性相
    互接続を形成する方法により形成された物品。
  18. 【請求項１８】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）第１の層を乾燥し； ｄ）保護層より先に延びる高さに第１の層の上に導電性
    の重合可能な前駆物質の第２の層を形成し； ｅ）フリップチップ上のバンプを形成するように第２の
    層を乾燥し； ｆ）バンプを基板のボンドパッドに接触し；更に ｇ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性の相互接続を形成す
    るようにバンプを重合する諸段階を含んだフリップチッ
    プのボンドパッドと基板のボンドパッドとを電気的に相
    互接続する方法により形成された物品。
  19. 【請求項１９】第１及び第２の層の導電性バンプがＢス
    テージポリマーである請求項18の物品。
  20. 【請求項２０】第１及び第２の層の導電性バンプが熱可
    塑性ポリマーである請求項18の物品。
  21. 【請求項２１】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）フリップチップのボンドパッド上に導電性の重合可
    能な前駆物質の第１の層を形成し； ｃ）導電性ポリマーを形成するように第１の層を重合
    し； ｄ）有機保護層より先に延びる高さに第１の層を上に導
    電性の重合可能な前駆物質の第２の層を形成し； ｅ）導電性ポリマーを形成するように第２の層を重合
    し、第１の層及び第２の層はこれによりフリップチップ
    のボンドパッド上の導電性バンプを形成し； ｆ）基板のボンドパッドに電気的接着剤を塗布し； ｇ）基板のボンドパッドにおける導電性接着剤を導電性
    バンプに接触し；更に ｈ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間に導電性相互接続を形成する
    ように導電性バンプを重合する諸段階を含んだフリップ
    チップのボンドパッドと基板のボンドパッドとを電気的
    に相互接続する方法により形成された物品。
  22. 【請求項２２】第１及び第２の層の導電性ポリマーが熱
    硬化性のもので形成される請求項21の物品。
  23. 【請求項２３】ａ）露出されるボンドパッドを残して、
    フリップチップのボンドパッドの置かれる表面上に有機
    保護層を選択的に形成し； ｂ）バンプを作るためにフリップチップのボンドパッド
    上に保護層より先に延びる高さに導電性の重合可能な前
    駆物質を形成し； ｃ）バンプを基板のボンドパッドに接触し；更に ｄ）この接触の間に、フリップチップのボンドパッドと
    基板のボンドパッドとの間の導電性相互接続を形成する
    ようにバンプを重合する諸段階を含んだフリップチップ
    のボンドパッドと基板のボンドパッドとの間の導電性相
    互接続を形成する方法により形成された物品。
JP3502870A 1989-12-18 1990-12-18 導電性ポリマー及び絶縁体を使用したフリツプチツプ技術 Expired - Fee Related JP2717993B2 (ja)

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US07/452,191 US5074947A (en) 1989-12-18 1989-12-18 Flip chip technology using electrically conductive polymers and dielectrics
US452,191 1989-12-18
PCT/US1990/007524 WO1991009419A1 (en) 1989-12-18 1990-12-18 Flip chip technology using electrically conductive polymers and dielectrics

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DE69033817T2 (de) 2002-06-06
KR920704343A (ko) 1992-12-19
EP0506859A1 (en) 1992-10-07
US5237130A (en) 1993-08-17
DE69027125T2 (de) 1996-11-28
EP0506859B1 (en) 1996-05-22
EP0690490B1 (en) 2001-10-04
EP0690490A2 (en) 1996-01-03
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JPH05503191A (ja) 1993-05-27
JP3200000B2 (ja) 2001-08-20
DE69033817D1 (de) 2001-11-08
WO1991009419A1 (en) 1991-06-27
SG71661A1 (en) 2000-04-18
US5074947A (en) 1991-12-24
SG80546A1 (en) 2001-05-22
DE69027125D1 (de) 1996-06-27
ATE206559T1 (de) 2001-10-15
KR100265616B1 (ko) 2000-09-15
JPH1092874A (ja) 1998-04-10
US5196371A (en) 1993-03-23
ATE138499T1 (de) 1996-06-15
JPH08227913A (ja) 1996-09-03

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