JPS56167340A - Junction of semicondctor pellet with substrate - Google Patents

Junction of semicondctor pellet with substrate

Info

Publication number
JPS56167340A
JPS56167340A JP6965480A JP6965480A JPS56167340A JP S56167340 A JPS56167340 A JP S56167340A JP 6965480 A JP6965480 A JP 6965480A JP 6965480 A JP6965480 A JP 6965480A JP S56167340 A JPS56167340 A JP S56167340A
Authority
JP
Japan
Prior art keywords
adhered
substrate
pellet
paint
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6965480A
Other languages
Japanese (ja)
Inventor
Katsuyuki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6965480A priority Critical patent/JPS56167340A/en
Publication of JPS56167340A publication Critical patent/JPS56167340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the cost of the face down bonding of the semiconductor pellet with the substrate by a method wherein a conductive paint is applied to electrode terminals on the surface of the wafer, a thermoplastic resin to the part other than the terminals, and the pellet and the substrate and are adhered by heating with pressure after scribing. CONSTITUTION:When the semiconductor substrate 1 to be joined with the electrodes 10 provided on the circuit substrate 9 by the filp flop chip methos is in the wafer condition, the conductive paint 13 consisted of graphite, silver, etc., being added with 1-20wt% epoxy resin, for example, is adhered to the electrode terminals 3 of the chip. While the thermoplastic paint 14 of nylon, etc., for example, is adhered samely to the part other than the terminal parts. The electrodes 10, 3 are positioned after scribing, and the chip 1 is adhered with pressure to be joined by heating at 130-180 deg.C. Because the paint 13 and the resin 14 can be adhered by simple screen printing, bonding process is simplified, and the cost can be reduced. Moreover reliability of adhesion, etc., can be enhanced by this way.
JP6965480A 1980-05-27 1980-05-27 Junction of semicondctor pellet with substrate Pending JPS56167340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6965480A JPS56167340A (en) 1980-05-27 1980-05-27 Junction of semicondctor pellet with substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6965480A JPS56167340A (en) 1980-05-27 1980-05-27 Junction of semicondctor pellet with substrate

Publications (1)

Publication Number Publication Date
JPS56167340A true JPS56167340A (en) 1981-12-23

Family

ID=13409034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6965480A Pending JPS56167340A (en) 1980-05-27 1980-05-27 Junction of semicondctor pellet with substrate

Country Status (1)

Country Link
JP (1) JPS56167340A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPS62169433A (en) * 1986-01-22 1987-07-25 Fuji Xerox Co Ltd Manufacture of semiconductor device
JPH0563031A (en) * 1992-02-06 1993-03-12 Casio Comput Co Ltd Bonding method for semiconductor device and substrate
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
WO1995005675A1 (en) * 1993-08-17 1995-02-23 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
EP0506859B1 (en) * 1989-12-18 1996-05-22 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
EP0962978A1 (en) * 1998-06-04 1999-12-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH027180B2 (en) * 1984-06-08 1990-02-15 Matsushita Electric Ind Co Ltd
JPS60262430A (en) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH0551179B2 (en) * 1986-01-22 1993-07-30 Fuji Xerox Co Ltd
JPS62169433A (en) * 1986-01-22 1987-07-25 Fuji Xerox Co Ltd Manufacture of semiconductor device
EP0506859B1 (en) * 1989-12-18 1996-05-22 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
US5879761A (en) * 1989-12-18 1999-03-09 Polymer Flip Chip Corporation Method for forming electrically conductive polymer interconnects on electrical substrates
US5918364A (en) * 1989-12-18 1999-07-06 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US6138348A (en) * 1989-12-18 2000-10-31 Polymer Flip Chip Corporation Method of forming electrically conductive polymer interconnects on electrical substrates
US5376825A (en) * 1990-10-22 1994-12-27 Seiko Epson Corporation Integrated circuit package for flexible computer system alternative architectures
JPH06103706B2 (en) * 1992-02-06 1994-12-14 カシオ計算機株式会社 Method of joining semiconductor device and substrate
JPH0563031A (en) * 1992-02-06 1993-03-12 Casio Comput Co Ltd Bonding method for semiconductor device and substrate
WO1995005675A1 (en) * 1993-08-17 1995-02-23 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
EP0962978A1 (en) * 1998-06-04 1999-12-08 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same
SG87034A1 (en) * 1998-06-04 2002-03-19 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing same
US6372548B2 (en) 1998-06-04 2002-04-16 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor package with a semiconductor device attached to a multilayered substrate
US6538315B2 (en) 1998-06-04 2003-03-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing same

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