JP2019165235A - クロスポイントメモリと、その製造方法 - Google Patents
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Abstract
Description
本出願は、2014年11月7日に出願された米国特許出願整理番号14/535,731“CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME”に対する優先権を享受する権利を主張し、米国特許出願整理番号14/535,731は、あらゆる目的でその全体において参照によって組み入れられる。
開示された技術は、概して集積回路デバイスに関し、より詳細には、クロスポイントメモリアレイと、その製造方法とに関する。
例えば、Si3N4)などの酸化物又は窒化物材料を含むことができる。幾つかの実施形態においては、間隙密封誘電体材料48および54は、異なる材料を含む。幾つかの他の実施形態においては、間隙密封誘電体材料48および54は、同一の材料を含む。
電体は、下部導線22または下部電極40および基板18のうちの、堆積中にピラー間で露出される部分も被覆することができる。
方法は、基板18上にメモリセル材料積層体を形成することと、第一のリソグラフィーマスクを用いて、メモリセル材料積層体と下部導電性材料22aをサブトラクティブパターン化して、x方向に延びる下部導電線22上のx方向に延びる複数のメモリセルライン積層体を形成することとを含む。メモリセルライン積層体と下部導線22の各々は、第一のリソグラフィーマスクを用いて、其々のブランケット材料を有する初期積層体からパターン化される。図示された実施形態においては、メモリセルライン積層体は、下部導線22上の下部電極線40aと、下部電極線40a上の第一のアクティブ素子線38a(例えば、セレクタ素子線)と、第一のアクティブ素子線38a上の中間電極線36aと、中間電極線36a上の第二のアクティブ素子線34a(例えば、ストレージ素子線)と、第二のアクティブ素子線34a上の上部電極線32aとを含む。パターン化される前に、其々のブランケット材料の積層体は、他の堆積技術の中でもとりわけ、例えば、物理蒸着(PVD)、化学蒸着(CVD)および原子層堆積(ALD)などの堆積技術によって形成されることができる。サブトラクティブパターン化の後、各メモリセルライン積層体は、x方向に延び、隣接するセル材料積層体のそれぞれは、x方向に延びる第一の間隙60によって分離され、図4Aおよび図4Bの中間アレイ構造100aが交互のメモリセルラインと第一の間隙60とを含むようにする。
20 上部導線
22 下部導線
30 メモリセル
32 上部電極
34 第二のアクティブ素子(ストレージ素子)
36 中間電極
38 第一のアクティブ素子(セレクタ素子)
40 下部電極
42 間隙
44 間隙
48 間隙密封誘電体
52 ライナー誘電体
54 間隙密封誘電体
62 埋め込みボイド
63 底部端(下端)
66 埋め込みボイド
67 底部端(下端)
84 分離領域
100、120、130 クロスポイントメモリアレイ
144a、144b、144c 間隙
148a、148b、148c 間隙密封誘電体
166a、166b、166c 埋め込みボイド
Claims (29)
- 下部導線と上部導線との間に配設された第1のメモリセルピラーであって、第1のアクティブ素子を含む第1のメモリセルピラーと、
間隙によって前記第1のメモリセルピラーから第1の方向に分離された第2のメモリセルピラーと、
前記第1及び第2のメモリセルピラー間の前記間隙内に配設された密封領域であって、前記密封領域は間隙密封誘電体を含み、前記密封領域は埋め込みボイドよりも上に形成され、前記密封領域の底面は、前記上部導線の底面に接触するように延びる前に終わっている、密封領域と、
を含むメモリデバイス。 - 前記密封領域は、前記上部導線の前記底面に接触するように、前記埋め込みボイドよりも上から延びている、請求項1に記載のメモリデバイス。
- 前記第1のメモリセルピラーは第2のアクティブ素子を含み、前記密封領域の前記底面は、上部電極と前記第2のアクティブ素子との間の垂直方向位置に形成されている、請求項1に記載のメモリデバイス。
- 前記密封領域の前記底面は、前記上部導線の上面と下部電極の上面との間に配設された垂直位置に形成されている、請求項1に記載のメモリデバイス。
- 前記埋め込みボイドは、前記密封領域の前記底面から前記下部導電線の上面まで垂直方向に延びている、請求項1に記載のメモリデバイス。
- 前記埋め込みボイドは、前記密封領域の前記底面から垂直方向に延びており、前記埋め込みボイドは、前記第1のメモリセルピラー及び前記第2のメモリセルピラーの各々の対向する側壁の少なくとも一部に接触している、請求項1に記載のメモリデバイス。
- 前記間隙密封誘電体は、前記対向する側壁の、少なくとも前記密封領域よりも下の部分に形成されている、請求項6に記載のメモリデバイス。
- 前記間隙の複数の面がライナー誘電体で裏打ちされており、前記ライナー誘電体と前記間隙密封誘電体とは異なる材料を含む、請求項1に記載のメモリデバイス。
- 前記ライナー誘電体は、前記間隙の底面、前記第1のメモリセルピラーの側壁、前記第2のメモリセルピラーの側壁、又はそれらの組み合わせ、のうちの少なくとも1つに形成されている、請求項8に記載のメモリデバイス。
- 前記埋め込みボイドの対向する側壁の一部を覆って形成された前記間隙密封誘電体の厚さは、前記密封領域の上縁における第1の厚さから、前記密封領域の下端における第2の厚さまで変化し、前記第1の厚さは前記第2の厚さよりも大きい、請求項8に記載のメモリデバイス。
- 前記第1のメモリセルピラーは第2のアクティブ素子を含み、前記第1のアクティブ素子又は前記第2のアクティブ素子の少なくとも一方はストレージ材料であり、前記第1のアクティブ素子又は前記第2のアクティブ素子の他方はセレクタ材料である、請求項1に記載のメモリデバイス。
- 第1のリソグラフィマスクを用いたサブトラクティブパターン化により、基板上に第1のメモリセルピラー及び第2のメモリセルピラーを形成することであって、前記第1のメモリセルピラー及び前記第2のメモリセルピラーは第1の方向へ延び、前記第1のメモリセルピラーと前記第2のメモリセルピラーとは第1の間隙によって分離される、ことと、
前記第1の間隙を少なくとも部分的に間隙密封誘電体で充填して密封領域を形成することであって、前記密封領域は埋め込みボイドよりも上に形成され、前記密封領域の底面は、上部導線の底面に接触するように延びる前に終わる、ことと、
を含む方法。 - 前記密封領域は、前記埋め込みボイドよりも上から、前記上部導線の前記底面に接触するように延びている、請求項12に記載の方法。
- 前記密封領域を形成することは、前記埋め込みボイドよりも上に尖端を形成することを含み、前記尖端は、その少なくとも一部分が前記密封領域の前記底面によって形成される、請求項13に記載の方法。
- 前記サブトラクティブパターン化の後に、前記第1及び第2のメモリセルピラー上にライナー誘電体を堆積すること、を更に含む、請求項12に記載の方法。
- 下部導線と上部導線との間に配設された第1のメモリセルピラーであって、第1のアクティブ素子を含む第1のメモリセルピラーと、
密封領域を形成する間隙密封誘電体で少なくとも部分的に充填された間隙によって、前記第1のメモリセルピラーから第1の方向に分離された第2のメモリセルピラーと、
前記密封領域よりも下に形成された埋め込みボイドであって、前記密封領域は、前記第1及び第2のメモリセルピラーの対向する側壁の一部分を覆う間隙密封誘電体で少なくとも部分的に充填され、前記密封領域の底面は、前記上部導線の底面に接触するように延びる前に終わっている、埋め込みボイドと、
を含むメモリデバイス。 - 前記密封領域よりも下に配設された、前記対向する側壁の前記一部分は、覆われていない、請求項16に記載のメモリデバイス。
- 前記埋め込みボイドよりも上に配設された第2の間隙を更に含み、前記第2の間隙は、前記間隙密封誘電体とは異なる材料で少なくとも部分的に充填されており、前記第2の間隙は、前記材料で少なくとも部分的に充填された分離領域を含む、請求項16に記載のメモリデバイス。
- 前記間隙密封誘電体と前記間隙を充填する誘電体とは異なる材料である、請求項18に記載のメモリデバイス。
- 前記埋め込みボイドよりも上に配設された第2の間隙を更に含み、前記第2の間隙が、前記間隙密封誘電体とは異なる材料で少なくとも部分的に充填されるか、又は、前記第2の間隙が、充填されていない分離領域を含む、請求項16に記載のメモリデバイス。
- 複数のメモリセル積層体を含むメモリデバイスであって、
各メモリセル積層体が、相変化材料を含むストレージ素子を含み、
隣接するメモリセル積層体が、閉じ込められたボイドを含む間隙によって分離されており、
密封領域が、前記閉じ込められたボイドよりも上の前記間隙内に形成され、かつ、間隙密封誘電体によって充填されており、
前記間隙は、前記密封領域よりも上に、充填されていない分離間隙を含み、
前記メモリセル積層体の各々が、前記閉じ込められたボイドによって包囲され、第1の横方向に延びる前記閉じ込められたボイドの高さが、第2の横方向に延びる前記閉じ込められたボイドの高さとは異なる、メモリデバイス。 - 各メモリセル積層体が上部アクティブ素子及び下部アクティブ素子を含み、前記上部及び下部アクティブ素子の一方が前記ストレージ素子を含み、前記上部及び下部アクティブ素子の他方がセレクタ素子を含む、請求項21に記載のメモリデバイス。
- 前記上部アクティブ素子が前記ストレージ素子を含み、前記隣接するメモリセル積層体の前記上部アクティブ素子が、前記閉じ込められたボイドによって少なくとも部分的に挟まれている、請求項22に記載のメモリデバイス。
- 前記隣接するメモリセル積層体の前記下部アクティブ素子は、前記閉じ込められたボイドによって少なくとも部分的に挟まれている、請求項23に記載のメモリデバイス。
- 各メモリセル積層体は、前記上部アクティブ素子上に形成された上部電極を含み、前記閉じ込められたボイドは、前記上部電極の上面よりも上に延びていない、請求項22に記載のメモリデバイス。
- 各メモリセル積層体は、上部導電線とそれに交差する下部導線との間に形成されており、各メモリセル積層体は、前記上部アクティブ素子上に形成された上部電極を更に含み、前記閉じ込められたボイドは、前記上部導電線の上面よりも上に延びていない、請求項22に記載のメモリデバイス。
- 第1の横方向に整列された複数のピラー行、及び、前記第1の横方向と交差する第2の横方向に整列された複数のピラー列、に配置されたメモリピラーのアレイを含む、メモリデバイスであって、
各メモリピラーは、相変化材料を含むストレージ素子を含み、
少なくとも2つの隣接するメモリピラーが、前記第1の横方向に延びる間隙密封誘電体と、それとは異なる前記第2の方向に延びる間隙密封誘電体とを含む間隙によって分離されており、
隣接するピラー行及び隣接するピラー列は、前記ピラー行及びピラー列のそれぞれの前記第1及び第2の横方向に延びる連続する埋め込みボイドによって分離されており、
前記間隙は、前記埋め込みボイドよりも上に配置された前記間隙内に形成された密封領域よりも上に、充填されていない分離間隙を含む、メモリデバイス。 - 前記第1の横方向に延びる前記連続する埋め込みボイドと、前記第2の横方向に延びる前記連続する埋め込みボイドとは、連続する埋め込みボイドによって各メモリピラーが包囲されるように、互いに交差している、請求項27に記載のメモリデバイス。
- 前記連続する埋め込みボイドが前記ストレージ素子を包囲している、請求項28に記載のメモリデバイス。
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