TWI749678B - 記憶元件及其形成方法 - Google Patents

記憶元件及其形成方法 Download PDF

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TWI749678B
TWI749678B TW109126234A TW109126234A TWI749678B TW I749678 B TWI749678 B TW I749678B TW 109126234 A TW109126234 A TW 109126234A TW 109126234 A TW109126234 A TW 109126234A TW I749678 B TWI749678 B TW I749678B
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Taiwan
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layer
structures
forming
memory element
cap
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TW109126234A
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TW202207427A (zh
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楊文忠
陳仕錫
林威璋
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力晶積成電子製造股份有限公司
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Priority to TW109126234A priority Critical patent/TWI749678B/zh
Priority to US17/019,328 priority patent/US11424340B2/en
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Publication of TWI749678B publication Critical patent/TWI749678B/zh
Publication of TW202207427A publication Critical patent/TW202207427A/zh
Priority to US17/855,832 priority patent/US11637017B2/en

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    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON

Abstract

一種記憶元件包括：基底、多個字元線結構、多個頂蓋結構以及多個空氣間隙。字元線結構配置在基底上。頂蓋結構分別配置在字元線結構上。頂蓋結構的材料包括氮化物。氮化物的氮濃度沿著靠近相應的字元線結構至遠離相應的字元線結構的方向減少。空氣間隙分別配置在字元線結構之間。空氣間隙直接接觸字元線結構。另提供一種記憶元件的形成方法。

Description

記憶元件及其形成方法
本發明是有關於一種記憶元件及其形成方法。
快閃記憶體由於具有可多次進行資料之存入、讀取、抹除等動作，且存入之資料在斷電後也不會消失之優點，所以已成為個人電腦和電子產品所廣泛採用的一種非揮發性記憶體元件。
隨著科技的進步，各類電子產品皆朝向輕薄短小的趨勢發展。然而，在這趨勢之下，快閃記憶體的臨界尺寸亦逐漸縮小，其導致快閃記憶體的製程將面臨許多挑戰。舉例來說，在快閃記憶體的積集度不斷提升的情況下，記憶胞之間的耦合干擾也隨著提高，進而影響快閃記憶體的耐用度與可靠度。
本發明提供一種記憶元件及其形成方法，其可增加字元線結構之間的空氣間隙比(air gap ratio)，以提升記憶元件的寫入速度(program speed)、耐用度(endurance)並改善字元線結構之 間的耦合干擾，進而增加記憶元件的可靠度。
本發明提供一種記憶元件包括：基底、多個字元線結構、多個頂蓋結構以及多個空氣間隙。字元線結構配置在基底上。頂蓋結構分別配置在字元線結構上。頂蓋結構的材料包括氮化物。氮化物的氮濃度沿著靠近相應的字元線結構至遠離相應的字元線結構的方向減少。空氣間隙分別配置在字元線結構之間。空氣間隙直接接觸字元線結構。
在本發明的一實施例中，上述的字元線結構包括：穿隧介電層、配置在穿隧介電層上的浮置閘極、配置在浮置閘極上的控制閘極、配置在浮置閘極與控制閘極之間的閘間介電層、配置在控制閘極上的金屬層以及配置在金屬層上的硬罩幕層。
在本發明的一實施例中，上述的頂蓋結構中的一者覆蓋硬罩幕層的頂面與側壁。
在本發明的一實施例中，上述的記憶元件更包括介電層，配置在多個頂蓋結構上並延伸至相鄰兩個頂蓋結構之間。
在本發明的一實施例中，上述的頂蓋結構包括單層結構、雙層結構或是多層結構。
在本發明的一實施例中，相鄰兩個頂蓋結構彼此相連。
本發明提供一種記憶元件的製造方法，包括：(a)在基底上形成字元線結構；(b)在字元線結構上共形形成氮化物層；(c)在氮化物層上形成犧牲圖案，以暴露出氮化物層的上部；(d)進行氮化處理，以將氮化物層的上部氮化為第一頂蓋層；(e)移除犧牲圖 案，以暴露出氮化物層的下部；(f)進行蝕刻製程，以薄化氮化物層的下部；(g)進行氧化製程，以將氮化物層的經薄化的下部氧化為氧化物層；以及(h)移除氧化物層，以暴露出字元線結構的下部，而第一頂蓋層覆蓋字元線結構的上部。
在本發明的一實施例中，上述的形成方法更包括：重複步驟(b)至步驟(h)至少一次，以在第一頂蓋層上形成第二頂蓋層，其中第一頂蓋層的氮濃度高於第二頂蓋層的氮濃度。
在本發明的一實施例中，上述的形成方法，更包括：重複步驟(b)至步驟(h)至少兩次，以在第一頂蓋層上形成第二頂蓋層並在第二頂蓋層上形成第三頂蓋層，其中第一頂蓋層的氮濃度高於第二頂蓋層的氮濃度，且第二頂蓋層的氮濃度高於第三頂蓋層的氮濃度。
在本發明的一實施例中，在形成上述的第三頂蓋層之後，更包括：在第三頂蓋層上形成介電層，以密封相鄰兩個字元線結構之間的空氣間隙，其中空氣間隙直接接觸相鄰兩個字元線結構。
在本發明的一實施例中，在進行上述的步驟(f)之後，氮化物層的經薄化的下部的厚度小於或等於2nm。
在本發明的一實施例中，在進行上述的步驟(g)之後，氧化物層更延伸覆蓋第一頂蓋層的表面。
在本發明的一實施例中，進行上述的氮化處理包括進行電漿氮化製程。
在本發明的一實施例中，進行上述的氮化處理更包括在進行電漿氮化製程之後，進行退火製程。
在本發明的一實施例中，上述的蝕刻製程包括使用稀釋氫氟酸(DHF)溶液的濕式蝕刻製程。
在本發明的一實施例中，上述的氧化製程包括通入H2、O2以及Ar的製程氣體，且H2的含量大於O2的含量。
在本發明的一實施例中，在形成上述的第一頂蓋層之後，更包括：在第一頂蓋層上形成介電層，其中介電層延伸覆蓋相鄰兩個字元線結構的側壁，以在相鄰兩個字元線結構之間形成空氣間隙。
本發明提供一種記憶元件包括：基底、多個字元線結構、多個頂蓋結構以及介電層。字元線結構配置在基底上。頂蓋結構分別配置在字元線結構上。頂蓋結構的材料包括氮化物。氮化物的氮濃度沿著靠近相應的字元線結構至遠離相應的字元線結構的方向減少。介電層配置在頂蓋結構上並延伸覆蓋字元線結構的側壁，以在字元線結構之間形成多個空氣間隙。
在本發明的一實施例中，上述的字元線結構包括：穿隧介電層、配置在穿隧介電層上的浮置閘極、配置在浮置閘極上的控制閘極、配置在浮置閘極與控制閘極之間的閘間介電層、配置在控制閘極上的金屬層以及配置在金屬層上的硬罩幕層。
在本發明的一實施例中，上述的頂蓋結構包括單層結構、雙層結構或是多層結構。
基於上述，本發明實施例將具有單層或多層結構的頂蓋結構形成在字元線結構上，以控制後續介電層填入相鄰字元線結構之間的空間的量，進而極大化字元線結構之間的空氣間隙比。在此情況下，上述的極大化的空氣間隙比可有效提升記憶元件的寫入速度、耐用度並改善字元線結構之間的耦合干擾，進而增加記憶元件的可靠度。
1、2、3:記憶元件
22、22a、22b:頂蓋結構
100:基底
102:字元線結構
102a:字元線結構的下部
102b:字元線結構的上部
104:穿隧介電層
106:浮置閘極
108:閘間介電層
110:控制閘極
112:金屬層
114:硬罩幕層
116:氮化物層
116l:氮化物層的下部
116r:經薄化的下部
116t:厚度
116u:氮化物層的上部
118:犧牲層
118a:犧牲圖案
120:氮化處理
122:第一頂蓋層
124:氧化製程
126:氧化物層
126a:氧化物層的下部
126b:氧化物層的上部
126t1、126t2:厚度
128:介電層
130、230、330:空氣間隙
130w、230w、330w:寬度
222:第二頂蓋層
322:第三頂蓋層
圖1A至圖1J是依照本發明第一實施例的一種記憶元件的製造流程的剖面示意圖。
圖2A至圖2B是依照本發明第二實施例的一種記憶元件的製造流程的剖面示意圖。
圖3A至圖3B是依照本發明第三實施例的一種記憶元件的製造流程的剖面示意圖。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1J是依照本發明第一實施例的一種記憶元件的製造流程的剖面示意圖。以下實施例所述的記憶元件是以快閃記憶體為例來進行說明，但本發明不以此為限。在其他實施例中，此記憶元件亦可以是動態隨機存取記憶體(DRAM)、反或快閃記憶體(NOR Flash)、嵌入式快閃記憶體(Embedded Flash)或其組合。
請參照圖1A，首先，提供基底100。在一些實施例中，基底100包括半導體基底、絕緣體上有矽(silicon on insulator，SOI)基底或其組合。在本實施例中，基底100可以是矽基底。
接著，在基底100上形成多個字元線結構102。具體來說，每一個字元線結構102由下而上包括穿隧介電層104、浮置閘極106、閘間介電層108、控制閘極110、金屬層112以及硬罩幕層114。在一些實施例中，穿隧介電層104包括氧化矽層，其可延伸覆蓋基底100的頂面，以連接相鄰字元線結構102。浮置閘極106包括多晶矽層。閘間介電層108包括單層結構或是多層結構，舉例來說，閘間介電層108可以是氧化物/氮化物/氧化物(ONO)所構成的複合層。控制閘極110包括多晶矽層。金屬層112包括鎢(W)層。硬罩幕層114包括氮化矽層。
請參照圖1B，在基底100上形成氮化物層116。氮化物層116共形覆蓋字元線結構102的表面以及基底100的頂面。在一些實施例中，氮化物層116可以是氮化矽層，其厚度約為3nm至5nm。在本實施例中，氮化物層116的形成方法可包括原子層 沉積法(atomic layer deposition，ALD)，但本發明不以此為限。在其他實施例中，氮化物層116可藉由化學氣相沉積法(CVD)來形成。
請參照圖1C，在氮化物層116上形成犧牲層118。犧牲層118填入字元線結構102之間的空間且延伸覆蓋氮化物層116的頂面。在一些實施例中，犧牲層118的材料包括光阻、多晶矽或其組合。
請參照圖1C與圖1D，回蝕刻犧牲層118，以在字元線結構102之間形成犧牲圖案118a。在此情況下，犧牲圖案118a暴露出氮化物層116的上部116u。在本實施例中，如圖1D所示，犧牲圖案118a的頂面實質上對齊金屬層112的頂面，但本發明不以此為限。在其他實施例中，犧牲圖案118a的頂面亦可高於金屬層112的頂面。
請參照圖1E，進行氮化處理120，以將氮化物層116的上部116u氮化為第一頂蓋層122(亦可稱為頂蓋結構22)。在本實施例中，第一頂蓋層122的材料包括氮化物，例如氮化矽。第一頂蓋層122的氮濃度可高於氮化物層116的氮濃度，且第一頂蓋層122的硬度亦可高於氮化物層116的硬度。
在一些實施例中，氮化處理120包括電漿氮化製程。值得注意的是，所述電漿氮化製程的製程溫度可低於500℃(例如，約為23℃至500℃)，以避免金屬層112變形。電漿氮化製程的製程時間可介於30秒至120秒之間，例如是90秒。在本實施例中， 氮化處理120還包括在進行電漿氮化製程之後，進行退火製程，以更固化或強化第一頂蓋層122。所述退火製程可以是後氮化退火(post-nitridation annealing，PNA)製程或是快速熱退火(rapid thermal annealing，RTA)製程。所述退火製程的製程溫度可低於900℃(例如，約為600℃至900℃)，以避免金屬層112變形。所述退火製程的製程時間可介於30秒至120秒之間，例如是30秒。
請參照圖1F，在氮化處理120之後，移除犧牲圖案118a，以暴露出氮化物層116的下部1161。
請參照圖1G，進行蝕刻製程，以薄化(thin)或削減(trim)氮化物層116的下部116l。在此情況下，氮化物層116的經薄化的下部(或剩餘部分)116r的厚度116t可小於或等於2nm，以利於後續氧化製程。也就是說，當氮化物層116的經薄化的下部116r的厚度116t大於2nm時，在後續氧化製程中，會有部分氮化物層無法被氧化，而殘留在字元線結構102的側壁，反而增加字元線結構102之間的寄生電容。
在一些實施例中，所述蝕刻製程包括使用稀釋氫氟酸(DHF)溶液的濕式蝕刻製程。由於氮化處理120已固化或強化第一頂蓋層122，因此稀釋氫氟酸溶液僅會移除大量的氮化物層116，而不會移除或是少量移除第一頂蓋層122。
請參照圖1G與圖1H，進行氧化製程124，以將氮化物層116的經薄化的下部116r氧化為氧化物層126。在一些實施例中，氧化製程124包括槽平面天線(Slot Plane Antenna，SPA)製 程。所述SPA製程是一種利用微波槽天線產生電漿來形成氧化物的製程。相較於爐管製程，SPA製程具有較低的製程溫度，以避免金屬層112變形。另外，當氮化物層116的經薄化的下部116r的厚度116t小於或等於2nm時，SPA製程亦可將經薄化的下部116r完全氧化為氧化物層126，而不會有未被氧化的氮化物層殘留在字元線結構102的側壁。在本實施例中，氧化製程124包括通入H2、O2以及Ar的製程氣體。H2可視為一種還原劑，而O2可視為一種氧化劑。當H2的含量大於O2的含量時，氧化製程124僅會將氮化物層116的經薄化的下部116r氧化為氧化物層126，而不會進一步氧化金屬層112。在本實施例中，H2與O2的比為2：1至4：1。另外，外露的第一頂蓋層122亦可被氧化製程124進一步氧化，使得氧化物層126更延伸覆蓋第一頂蓋層122的表面，在此情況下，覆蓋字元線結構102的氧化物層126的下部126a的具有厚度126t1，而覆蓋第一頂蓋層122的氧化物層126的上部126b的具有厚度126t2。厚度126t1可大於厚度126t2。此外，氧化物層126的上部126b可連續或是不連續地覆蓋第一頂蓋層122的表面。
請參照圖1I，移除氧化物層126，以暴露出第一頂蓋層122與字元線結構102的下部102a，此時第一頂蓋層122覆蓋字元線結構102的上部102b。具體來說，第一頂蓋層122可覆蓋硬罩幕層114的頂面與側壁。
請參照圖1J，在移除氧化物層126之後，可在第一頂蓋 層122上形成介電層128，由此完成記憶元件1。在一些實施例中，介電層128的材料包括氧化矽或其低介電常數材料(介電常數k小於3.9)。具體來說，如圖1J所示，介電層128可延伸覆蓋相鄰兩個字元線結構102的側壁，以在相鄰兩個字元線結構102之間形成空氣間隙130。但本發明不以此為限，在其他實施例中，當相鄰兩個第一頂蓋層122(或頂蓋結構22)之間的距離夠小，介電層128亦可不延伸至相鄰兩個字元線結構102之間的空間，以使空氣間隙130直接接觸相鄰兩個字元線結構102的側壁。
值得注意的是，隨著記憶元件的積集度不斷提升，字元線結構102之間的電容-電阻延遲(Resistor-Capacitor Delay，RC Delay)與浮置閘極106(或金屬層112)之間的耦合干擾也會隨之增加。為了解決上述問題，本實施例可藉由上述形成方法在字元線結構102之間形成空氣間隙130(其介電常數k=1)，以有效降低字元線結構102之間的寄生電容，進而降低字元線結構102之間的電容-電阻延遲並提升記憶元件1的寫入速度。另外，此空氣間隙130亦可改善字元線結構102之間的耦合干擾與耐用度，進而提升記憶元件1的可靠度。
另一方面，除了上述快閃記憶體中的字元線結構之外，本發明亦可應用在動態隨機存取記憶體(DRAM)中。具體來說，本發明可有效降低DRAM的位元線結構之間的寄生電容，以降低位元線結構之間的電容-電阻延遲並改善位元線結構之間的耦合干擾，進而提升DRAM的可靠度。當然，本發明亦可應用在其他 記憶體領域。
此外，藉由上述圖1A至圖1J的形成方法還可進一步極大化字元線結構之間的空氣間隙比，以更進一步改善記憶元件的效能與可靠度。詳細內容請參照以下實施例。
圖2A至圖2B是依照本發明第二實施例的一種記憶元件的製造流程的剖面示意圖。
請參照圖2A，圖2A的結構是將圖1I的結構重複進行圖1B至圖1I的步驟至少一次，以在第一頂蓋層122上形成第二頂蓋層222。在本實施例中，第一頂蓋層122與其上的第二頂蓋層222可稱為頂蓋結構22a。第一頂蓋層122與第二頂蓋層222可具有相同材料，例如是氮化矽。第一頂蓋層122的氮濃度可高於第二頂蓋層222的氮濃度。也就是說，頂蓋結構22a的氮濃度沿著靠近相應的字元線結構102至遠離相應的字元線結構102的方向減少。
接著，請參照圖2B，在頂蓋結構22a上形成介電層128，由此完成記憶元件2。具體來說，如圖2B所示，介電層128可延伸覆蓋相鄰兩個字元線結構102的側壁，以在相鄰兩個字元線結構102之間形成空氣間隙230。
值得注意的是，相較於記憶元件1的由單層結構所構成的頂蓋結構22，記憶元件2的由雙層結構所構成的頂蓋結構22a的厚度較厚。在此情況下，相鄰的頂蓋結構22a之間的距離較小，所以介電層128較不易填入相鄰兩個字元線結構102之間的空間。如圖1J與圖2B所示，記憶元件2的空氣間隙230的寬度230w 可大於記憶元件1的空氣間隙130的寬度130w。當記憶元件2的空氣間隙比增加，字元線結構102之間的寄生電容也會隨之降低，以降低字元線結構102之間的電容-電阻延遲並提升記憶元件2的寫入速度。此外，此空氣間隙230亦可改善字元線結構102之間的耦合干擾與耐用度，進而提升記憶元件2的可靠度。
另一方面，當記憶元件2的頂蓋結構22a之間的距離夠小，介電層128亦可不延伸至相鄰兩個字元線結構102之間的空間，以使空氣間隙230直接接觸相鄰兩個字元線結構102的側壁。
圖3A至圖3B是依照本發明第三實施例的一種記憶元件的製造流程的剖面示意圖。
請參照圖3A，圖3A的結構是將圖1I的結構重複進行圖1B至圖1I的步驟至少兩次，以在第一頂蓋層122上形成第二頂蓋層222並在第二頂蓋層222上形成第三頂蓋層322。在本實施例中，第一頂蓋層122、第二頂蓋層222以及第三頂蓋層322的三層結構可稱為頂蓋結構22b。但本發明不以此為限，在其他實施例中，可重複進行圖1B至圖1I的步驟多次，以在第一頂蓋層122上形成多個頂蓋層，進而形成具有多層結構的頂蓋結構。在本實施例中，第一頂蓋層122、第二頂蓋層222以及第三頂蓋層322可具有相同材料，例如是氮化矽。第一頂蓋層122的氮濃度可高於第二頂蓋層222的氮濃度，而第二頂蓋層222的氮濃度可高於第三頂蓋層322的氮濃度。也就是說，頂蓋結構22b的氮濃度沿著靠近相應的字元線結構102至遠離相應的字元線結構102的方 向減少。
接著，請參照圖3B，在頂蓋結構22b上形成介電層128，由此完成記憶元件3。在本實施例中，如圖3B所示，由於相鄰兩個頂蓋結構22b之間的距離過近，因此，介電層128無法填入相鄰兩個字元線結構102之間的空間，而是密封相鄰兩個字元線結構102之間的空間，以形成空氣間隙330。具體來說，空氣間隙330直接接觸相鄰兩個字元線結構102的側壁。在此情況下，如圖2B與圖3B所示，記憶元件3的空氣間隙330的寬度330w可大於記憶元件2的空氣間隙230的寬度230w。因此，記憶元件3的空氣間隙比可進一步地極大化，以有效降低字元線結構102之間的寄生電容與電容-電阻延遲，進而提升記憶元件3的效能與可靠度。
另外，雖然圖3B所繪示的介電層128的底面與頂蓋結構22b的底面齊平，但本發明不以此為限。在其他實施例中，介電層128的底面亦可高於頂蓋結構22b的底面。此外，在替代實施例中，相鄰兩個頂蓋結構22b亦可以彼此相連，以使介電層128不填入相鄰兩個頂蓋結構22b之間的空間。
綜上所述，本發明實施例將具有單層或多層結構的頂蓋結構形成在字元線結構上，以控制後續介電層填入相鄰字元線結構之間的空間的量，進而極大化字元線結構之間的空氣間隙比。在此情況下，上述的極大化的空氣間隙比可有效提升記憶元件的寫入速度、耐用度並改善字元線結構之間的耦合干擾，進而增加記憶元件的可靠度。
3:記憶元件
22b:頂蓋結構
100:基底
102:字元線結構
104:穿隧介電層
106:浮置閘極
108:閘間介電層
110:控制閘極
112:金屬層
114:硬罩幕層
122:第一頂蓋層
128:介電層
330:空氣間隙
330w:寬度
222:第二頂蓋層
322:第三頂蓋層

Claims (20)

  1. 一種記憶元件，包括：多個字元線結構，配置在基底上；多個頂蓋結構，分別配置在所述多個字元線結構上，其中所述多個頂蓋結構的材料包括氮化物，所述氮化物的氮濃度沿著靠近相應的字元線結構至遠離所述相應的字元線結構的方向減少；以及多個空氣間隙，分別配置在所述多個字元線結構之間，其中所述多個空氣間隙直接接觸所述多個字元線結構。
  2. 如請求項1所述的記憶元件，其中各所述字元線結構包括：穿隧介電層；浮置閘極，配置在所述穿隧介電層上；控制閘極，配置在所述浮置閘極上；閘間介電層，配置在所述浮置閘極與所述控制閘極之間；金屬層，配置在所述控制閘極上；以及硬罩幕層，配置在所述金屬層上。
  3. 如請求項2所述的記憶元件，其中所述多個頂蓋結構中的一者覆蓋所述硬罩幕層的頂面與側壁。
  4. 如請求項2所述的記憶元件，更包括介電層，配置在所述多個頂蓋結構上並延伸至相鄰兩個頂蓋結構之間。
  5. 如請求項1所述的記憶元件，其中各所述多個頂蓋結構包括單層結構、雙層結構或是多層結構。
  6. 如請求項1所述的記憶元件，其中相鄰兩個頂蓋結構彼此相連。
  7. 一種記憶元件的形成方法，包括：(a)在基底上形成字元線結構；(b)在所述字元線結構上共形形成氮化物層；(c)在所述氮化物層上形成犧牲圖案，以暴露出所述氮化物層的上部；(d)進行氮化處理，以將所述氮化物層的所述上部氮化為第一頂蓋層；(e)移除所述犧牲圖案，以暴露出所述氮化物層的下部；(f)進行蝕刻製程，以薄化所述氮化物層的所述下部；(g)進行氧化製程，以將所述氮化物層的經薄化的下部氧化為氧化物層；以及(h)移除所述氧化物層，以暴露出所述字元線結構的下部，而所述第一頂蓋層覆蓋所述字元線結構的上部。
  8. 如請求項7所述的記憶元件的形成方法，更包括：重複步驟(b)至步驟(h)至少一次，以在所述第一頂蓋層上形成第二頂蓋層，其中所述第一頂蓋層的氮濃度高於所述第二頂蓋層的氮濃度。
  9. 如請求項7所述的記憶元件的形成方法，更包括：重複步驟(b)至步驟(h)至少兩次，以在所述第一頂蓋層上形成第二頂蓋層並在所述第二頂蓋層上形成第三頂蓋層，其中所述第一頂蓋層的氮濃度高於所述第二頂蓋層的氮濃度，且所述第二頂蓋層的所述氮濃度高於所述第三頂蓋層的氮濃度。
  10. 如請求項9所述的記憶元件的形成方法，其中在形成所述第三頂蓋層之後，更包括：在所述第三頂蓋層上形成介電層，以密封相鄰兩個字元線結構之間的空氣間隙，其中所述空氣間隙直接接觸所述相鄰兩個字元線結構。
  11. 如請求項7所述的記憶元件的形成方法，其中在進行步驟(f)之後，所述氮化物層的所述經薄化的下部的厚度小於或等於2nm。
  12. 如請求項7所述的記憶元件的形成方法，其中在進行步驟(g)之後，所述氧化物層更延伸覆蓋所述第一頂蓋層的表面。
  13. 如請求項7所述的記憶元件的形成方法，其中進行所述氮化處理包括進行電漿氮化製程。
  14. 如請求項13所述的記憶元件的形成方法，其中進行所述氮化處理更包括在進行所述電漿氮化製程之後，進行退火製程。
  15. 如請求項7所述的記憶元件的形成方法，其中所述蝕刻製程包括使用稀釋氫氟酸溶液的濕式蝕刻製程。
  16. 如請求項7所述的記憶元件的形成方法，其中所述氧化製程包括通入H2、O2以及Ar的製程氣體，且所述H2的含量大於所述O2的含量。
  17. 如請求項7所述的記憶元件的形成方法，其中在形成所述第一頂蓋層之後，更包括：在所述第一頂蓋層上形成介電層，其中所述介電層延伸覆蓋相鄰兩個字元線結構的側壁，以在所述相鄰兩個字元線結構之間形成空氣間隙。
  18. 一種記憶元件，包括：多個字元線結構，配置在基底上；多個頂蓋結構，分別配置在所述多個字元線結構上，其中所述多個頂蓋結構的材料包括氮化物，所述氮化物的氮濃度沿著靠近相應的字元線結構至遠離所述相應的字元線結構的方向減少；以及介電層，配置在所述多個頂蓋結構上並延伸覆蓋所述多個字元線結構的側壁，以在所述多個字元線結構之間形成多個空氣間隙。
  19. 如請求項18所述的記憶元件，其中各所述字元線結構包括：穿隧介電層；浮置閘極，配置在所述穿隧介電層上；控制閘極，配置在所述浮置閘極上；閘間介電層，配置在所述浮置閘極與所述控制閘極之間； 金屬層，配置在所述控制閘極上；以及硬罩幕層，配置在所述金屬層上。
  20. 如請求項18所述的記憶元件，其中各所述多個頂蓋結構包括單層結構、雙層結構或是多層結構。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW399330B (en) * 1997-12-23 2000-07-21 Motorola Inc Semiconductor device, memory cell, and processes for forming them
US8629528B2 (en) * 2008-02-18 2014-01-14 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
TW201436317A (zh) * 2013-03-13 2014-09-16 Macronix Int Co Ltd 電阻式記憶體裝置與其製造方法
US9460958B2 (en) * 2010-06-19 2016-10-04 Sandisk Technologies Llc Air gap isolation in non-volatile memory
US9515074B2 (en) * 2010-12-14 2016-12-06 SK Hynix Inc. 3-D non-volatile memory device and method of manufacturing the same
TW201818508A (zh) * 2016-11-08 2018-05-16 Toshiba Memory Corp 半導體記憶裝置
US20200118929A1 (en) * 2016-08-08 2020-04-16 Samsung Electronics Co., Ltd. Semiconductor memory device
TW202021098A (zh) * 2018-11-22 2020-06-01 大陸商長江存儲科技有限責任公司 三維記憶體元件及其製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100559A (en) * 1998-08-14 2000-08-08 Advanced Micro Devices, Inc. Multipurpose graded silicon oxynitride cap layer
US6894341B2 (en) * 2001-12-25 2005-05-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method
KR100784860B1 (ko) 2005-10-31 2007-12-14 삼성전자주식회사 비휘발성 메모리 장치 및 그 제조 방법
KR100880310B1 (ko) * 2006-09-06 2009-01-28 주식회사 하이닉스반도체 반도체 소자의 제조방법
US20090251972A1 (en) * 2008-04-03 2009-10-08 Yue-Song He Nonvolatile memory arrays with charge trapping dielectric and with non-dielectric nanodots
US8546239B2 (en) * 2010-06-11 2013-10-01 Sandisk Technologies Inc. Methods of fabricating non-volatile memory with air gaps
KR101559345B1 (ko) * 2010-08-26 2015-10-15 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
KR20120027906A (ko) * 2010-09-14 2012-03-22 삼성전자주식회사 반도체 소자 및 반도체 소자 제조 방법
US9349740B2 (en) * 2014-01-24 2016-05-24 Sandisk Technologies Inc. Non-volatile storage element with suspended charge storage region
US9281314B1 (en) * 2014-10-10 2016-03-08 Sandisk Technologies Inc. Non-volatile storage having oxide/nitride sidewall
US9748311B2 (en) * 2014-11-07 2017-08-29 Micron Technology, Inc. Cross-point memory and methods for fabrication of same
US9748332B1 (en) * 2016-12-09 2017-08-29 Macronix International Co., Ltd. Non-volatile semiconductor memory
CN109427798A (zh) * 2017-08-28 2019-03-05 中芯国际集成电路制造(上海)有限公司 闪存器件及其制造方法
CN109494224B (zh) * 2017-09-08 2020-12-01 华邦电子股份有限公司 非挥发性存储器装置及其制造方法
TWI721546B (zh) * 2019-08-30 2021-03-11 華邦電子股份有限公司 記憶體元件及其製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW399330B (en) * 1997-12-23 2000-07-21 Motorola Inc Semiconductor device, memory cell, and processes for forming them
US8629528B2 (en) * 2008-02-18 2014-01-14 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
US9460958B2 (en) * 2010-06-19 2016-10-04 Sandisk Technologies Llc Air gap isolation in non-volatile memory
US9515074B2 (en) * 2010-12-14 2016-12-06 SK Hynix Inc. 3-D non-volatile memory device and method of manufacturing the same
TW201436317A (zh) * 2013-03-13 2014-09-16 Macronix Int Co Ltd 電阻式記憶體裝置與其製造方法
US20200118929A1 (en) * 2016-08-08 2020-04-16 Samsung Electronics Co., Ltd. Semiconductor memory device
TW201818508A (zh) * 2016-11-08 2018-05-16 Toshiba Memory Corp 半導體記憶裝置
TW201903975A (zh) * 2016-11-08 2019-01-16 日商東芝記憶體股份有限公司 半導體記憶裝置
TW202021098A (zh) * 2018-11-22 2020-06-01 大陸商長江存儲科技有限責任公司 三維記憶體元件及其製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Weon Wi Jang, Jun-BoYoon, Min-SangKim, Ji-Myoung Lee, Sung-Min Kim, Eun-JungYoon, Keun Hwi Cho, Sung-Young Lee, In-HyukChoi, Dong-Won Kim, and Donggun Park, "NEMS switch with 30 nm-thick beam and 20 nm-thick air-gap for high density non-volatile memory applications," Solid-State Electronics, October 2008. Vol. 52, No. 10, pages1578-1583. *

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