JP2014528652A - パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化 - Google Patents

パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化 Download PDF

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Publication number
JP2014528652A
JP2014528652A JP2014534655A JP2014534655A JP2014528652A JP 2014528652 A JP2014528652 A JP 2014528652A JP 2014534655 A JP2014534655 A JP 2014534655A JP 2014534655 A JP2014534655 A JP 2014534655A JP 2014528652 A JP2014528652 A JP 2014528652A
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JP
Japan
Prior art keywords
package
microelectronic
signal
terminals
terminal
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Pending
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JP2014534655A
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English (en)
Japanese (ja)
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JP2014528652A5 (enExample
Inventor
クリスプ，リチャード・デューイット
ゾーニ，ワエル
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インヴェンサス・コーポレイション
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Publication of JP2014528652A publication Critical patent/JP2014528652A/ja
Publication of JP2014528652A5 publication Critical patent/JP2014528652A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H10W70/65—
    • H10W70/68—
    • H10W72/00—
    • H10W72/60—
    • H10W90/00—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10545—Related components mounted on both sides of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H10W70/60—
    • H10W72/59—
    • H10W72/865—
    • H10W72/932—
    • H10W72/9445—
    • H10W74/00—
    • H10W74/117—
    • H10W90/734—
    • H10W90/752—
    • H10W90/754—

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Geometry (AREA)
JP2014534655A 2011-10-03 2012-10-03 パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化 Pending JP2014528652A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161542495P 2011-10-03 2011-10-03
US61/542,495 2011-10-03
PCT/US2012/058557 WO2013052544A1 (en) 2011-10-03 2012-10-03 Stub minimization with terminal grids offset from center of package

Publications (2)

Publication Number Publication Date
JP2014528652A true JP2014528652A (ja) 2014-10-27
JP2014528652A5 JP2014528652A5 (enExample) 2015-11-19

Family

ID=47116368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014534655A Pending JP2014528652A (ja) 2011-10-03 2012-10-03 パッケージの中心から端子グリッドをオフセットすることによるスタブ最小化

Country Status (6)

Country Link
US (2) US8917532B2 (enExample)
EP (1) EP2766928A1 (enExample)
JP (1) JP2014528652A (enExample)
KR (1) KR20140069343A (enExample)
TW (1) TWI515864B (enExample)
WO (1) WO2013052544A1 (enExample)

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US10389235B2 (en) 2011-05-05 2019-08-20 Psemi Corporation Power converter
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8525327B2 (en) 2011-10-03 2013-09-03 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
WO2013052544A1 (en) * 2011-10-03 2013-04-11 Invensas Corporation Stub minimization with terminal grids offset from center of package
US8659143B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
KR101894823B1 (ko) 2011-10-03 2018-09-04 인벤사스 코포레이션 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화
US8659140B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
EP2769409A1 (en) 2011-10-03 2014-08-27 Invensas Corporation Stub minimization for multi-die wirebond assemblies with orthogonal windows
US8659141B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9070423B2 (en) * 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
CN119092477A (zh) * 2023-05-29 2024-12-06 长鑫存储技术有限公司 一种封装结构和半导体结构

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